[Deepin-Kernel-SIG] [linux 6.6-y] [Upstream] [Intel] Intel RDT non-contiguous CBM support

[Avenger-285714]

bugzilla: https://bugzilla.openanolis.cn/show_bug.cgi?id=8085

About Intel RDT non-contiguous CBM support:

GNR and SRF support L3/L2 non-contiguous way masks. Linux kernel changes is needed to support this.

Legacy RDT only support contiguous bits in L3/L2 CAT Cache Bit Mask (CBM) when allocating L3/L2 cache. For example, 0x111 is a valid bit mask but 0x101 is an invalid bit mask. This is limitation of legacy RDT hardware. It limits user's capability to allocate L3/L2 cache efficiently and cause poor performance.

With non-contiguous bits in L3/L2 CAT, we can allocate L3/L2 cache in various ways and utilize the cache efficiently and improve user application performance.

About the patches:
There are 4 backported upstream patches:
aaa5fa3 Documentation/x86: Document resctrl's new sparse_masks
4dba8f1 x86/resctrl: Add sparse_masks file in info
0e3cd31 x86/resctrl: Enable non-contiguous CBMs in Intel CAT
39c6eed x86/resctrl: Rename arch_has_sparse_bitmaps

Passed tests:
Intel RDT non-contiguous CBM CAT tests: passed.

Link: https://gitee.com/anolis/cloud-kernel/pulls/2740

Summary by Sourcery

Enable and expose Intel RDT hardware support for non-contiguous cache bitmasks by backporting upstream sparse_masks functionality, updating validation logic, renaming internal fields, and updating documentation.

New Features:

• Support non-contiguous cache bitmasks (CBMs) for Intel L2/L3 CAT based on CPUID sparse_masks capability
• Expose a new "sparse_masks" info file under resctrl to report hardware support for non-contiguous CBMs

Enhancements:

• Rename internal field from arch_has_sparse_bitmaps to arch_has_sparse_bitmasks
• Update CBM validation to allow or reject non-contiguous bitmasks according to the new flag

Documentation:

• Document the resctrl sparse_masks file and its semantics in the x86 resctrl documentation

Tests:

• Add and pass Intel RDT non-contiguous CBM CAT tests

[sourcery-ai]

Reviewer's Guide

Introduce Intel RDT non-contiguous CBM support by adding a new sparse_masks sysfs attribute, parsing the noncontiguous bit from CPUID, updating validation logic to accept sparse masks when supported, refactoring internal flags and data structures, and updating documentation accordingly.

Sequence Diagram for Reading sparse_masks Sysfs Attribute

sequenceDiagram
    actor User
    participant FS as "Kernel (sysfs)"
    participant RDT as "RDT Subsystem"

    User->>+FS: Read /sys/fs/resctrl/.../info/L<N>/sparse_masks
    FS->>+RDT: rdt_has_sparse_bitmasks_show(of, seq, v)
    RDT-->>RDT: Get resctrl_schema s = of->kn->parent->priv
    RDT-->>RDT: Get rdt_resource r = s->res
    RDT-->>RDT: Access r->cache.arch_has_sparse_bitmasks
    RDT->>-FS: Output value of arch_has_sparse_bitmasks (0 or 1)
    FS->>-User: Return "0" or "1"

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Sequence Diagram: Initializing Non-Contiguous CBM Support (Intel)

sequenceDiagram
    participant KernelInit as "Kernel (RDT Init for Intel CPU)"
    participant CPUHardware as "CPU Hardware"

    KernelInit->>+KernelInit: Call rdt_get_cache_alloc_cfg(idx, r)
    KernelInit->>CPUHardware: Execute CPUID instruction (EAX=0x10, ECX=idx)
    CPUHardware-->>KernelInit: Return EAX, EBX, ECX, EDX registers
    KernelInit->>KernelInit: Parse ECX.split.noncont from returned ECX value
    KernelInit->>KernelInit: Set r->cache.arch_has_sparse_bitmasks = ecx.split.noncont
    KernelInit-->>KernelInit: Continue rdt_resource cache configuration

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Sequence Diagram for CBM Validation with Non-Contiguous Mask Support

sequenceDiagram
    participant UserProcess as "User/Process (writing CBM)"
    participant RDT as "RDT Subsystem (ctrlmondata.c)"

    UserProcess->>+RDT: Attempt to configure CBM via schemata file
    RDT->>+RDT: cbm_validate(buf, data, r)
    RDT-->>RDT: Parse CBM string to get 'val'
    RDT-->>RDT: Determine if 'val' is non-contiguous
    RDT-->>RDT: Let is_mask_non_contiguous = (find_next_bit(&val, cbm_len, zero_bit) < cbm_len)
    alt is_mask_non_contiguous AND NOT r->cache.arch_has_sparse_bitmasks
        RDT-->>RDT: Mask is non-contiguous AND hardware does not support it
        RDT-->>RDT: Report error "The mask %lx has non-consecutive 1-bits"
        RDT-->>RDT: Validation fails (return false)
    else
        RDT-->>RDT: Mask is contiguous OR hardware supports non-contiguous masks
        RDT-->>RDT: (Perform other CBM validations if any)
        RDT-->>RDT: Validation passes (return true, if other checks pass)
    end
    RDT->>-UserProcess: Acknowledge or reject CBM configuration

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Class Diagram for Updated RDT Data Structures

classDiagram
    class resctrl_cache {
        +unsigned int cbm_len
        +unsigned int min_cbm_bits
        +unsigned int shareable_bits
        +bool arch_has_sparse_bitmasks
        +bool arch_has_per_cpu_cfg
    }

    class CPUID_0x10_x_ECX_Split {
        <<struct>>
        +unsigned int reserved_bits
        +unsigned int noncont_bit
    }

    class cpuid_0x10_x_ecx {
        <<union>>
        +CPUID_0x10_x_ECX_Split split
        +unsigned int full
    }

    cpuid_0x10_x_ecx ..> CPUID_0x10_x_ECX_Split : contains

    class rdt_resource {
        +resctrl_cache cache
        # other fields...
    }
    rdt_resource *-- resctrl_cache : contains

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File-Level Changes

Change	Details	Files
Expose sparse bitmask support via new sysfs interface	Add rdt_has_sparse_bitmasks_show seq_show callback Register 'sparse_masks' attribute in resctrl info files	arch/x86/kernel/cpu/resctrl/rdtgroup.c
Allow non-contiguous CBMs in validation logic	Update comments to reflect CPUID-based detection on Intel Switch validation to use arch_has_sparse_bitmasks flag	arch/x86/kernel/cpu/resctrl/ctrlmondata.c
Detect and initialize sparse bitmask capability via CPUID	Initialize arch_has_sparse_bitmasks to false in Haswell probe Parse ECX.noncont from CPUID.0x10 and assign to flag Remove legacy arch_has_sparse_bitmaps assignments	arch/x86/kernel/cpu/resctrl/core.c
Refactor internal data structures for sparse bitmasks	Introduce union cpuid_0x10_x_ecx for ECX noncont bit Rename arch_has_sparse_bitmaps to arch_has_sparse_bitmasks	arch/x86/kernel/cpu/resctrl/internal.h include/linux/resctrl.h
Update resctrl documentation for sparse_masks	Document the new sparse_masks file in info tree Describe non-contiguous CBM support in resctrl.rst	Documentation/arch/x86/resctrl.rst

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[deepin-ci-robot]

[APPROVALNOTIFIER] This PR is NOT APPROVED

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Once this PR has been reviewed and has the lgtm label, please ask for approval from avenger-285714. For more information see the Code Review Process.

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[deepin-ci-robot]

deepin pr auto review

关键摘要:

• 在resctrl.h文件中，arch_has_sparse_bitmaps被更正为arch_has_sparse_bitmasks，这是一个重要的命名更改，需要确保所有相关的代码都已经更新以反映这一变化。
• 在core.c文件中，新增了一个成员变量arch_has_sparse_bitmasks，并在rdt_get_cache_alloc_cfg函数中根据CPUID的结果设置其值。这是一个合理的改动，但需要确保所有相关的逻辑都已经更新以处理这个新成员变量。
• 在ctrlmondata.c文件中，cbm_validate函数的注释和逻辑已经更新，以反映对非连续1s值的支持情况。这是一个重要的更新，需要确保所有相关的测试用例都已经更新以覆盖新的逻辑。
• 在rdtgroup.c文件中，新增了一个名为sparse_masks的文件操作，用于显示arch_has_sparse_bitmasks的值。这是一个合理的改动，但需要确保这个新文件操作已经添加到所有相关的资源中。
• 在Documentation/arch/x86/resctrl.rst文件中，新增了对sparse_masks的解释，这是一个好的做法，可以帮助用户更好地理解这个新特性。

是否建议立即修改:
是

• 所有提到的更改都需要立即进行，以确保代码的一致性和正确性。特别是命名更改和新增的成员变量，需要确保所有相关的代码都已经更新以反映这些变化。
• 新增的文件操作和文档更新也需要立即进行，以确保用户能够正确地使用这些新特性。

[Copilot]

Pull Request Overview

This PR backports upstream changes to support Intel RDT non-contiguous cache bitmask (CBM) functionality. Key changes include renaming internal fields from "sparse_bitmaps" to "sparse_bitmasks", updating CPUID parsing and CBM validation logic, and adding a new "sparse_masks" info file with corresponding documentation updates.

Reviewed Changes

Copilot reviewed 6 out of 6 changed files in this pull request and generated no comments.

Show a summary per file

File	Description
include/linux/resctrl.h	Renames the field to reflect non-contiguous bitmask support.
arch/x86/kernel/cpu/resctrl/rdtgroup.c	Introduces a new info file entry to expose the sparse bitmask capability.
arch/x86/kernel/cpu/resctrl/internal.h	Adds a CPUID union for non-contiguous bitmask support.
arch/x86/kernel/cpu/resctrl/ctrlmondata.c	Updates CBM validation logic to reflect the new sparse bitmask flag.
arch/x86/kernel/cpu/resctrl/core.c	Revises CPUID extraction and sets the sparse bitmask flag appropriately for Intel CPUs.
Documentation/arch/x86/resctrl.rst	Documents the new "sparse_masks" file and explains the non-contiguous bitmask support.

[sourcery-ai]

Hey @Avenger-285714 - I've reviewed your changes and they look great!

Here's what I looked at during the review

• 🟢 General issues: all looks good
• 🟢 Security: all looks good
• 🟢 Testing: all looks good
• 🟢 Complexity: all looks good
• 🟢 Documentation: all looks good

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