diff --git a/drivers/gpu/drm/arise/cbios/CBios.h b/drivers/gpu/drm/arise/cbios/CBios.h index 2db2a9d32fbd2..eb3de0cd2383f 100644 --- a/drivers/gpu/drm/arise/cbios/CBios.h +++ b/drivers/gpu/drm/arise/cbios/CBios.h @@ -1349,6 +1349,7 @@ typedef struct _CBIOS_CALLBACK_FUNCTIONS CBIOS_VOID* pFnVsprintf; CBIOS_VOID* pFnWriteRegisterU32; CBIOS_VOID* pFnReadRegisterU32; + CBIOS_VOID* pFnVDbgPrint; CBIOS_VOID* pFnDbgPrintToFile; CBIOS_VOID* pFnVsnprintf; //gpio diff --git a/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.c b/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.c index 9e2854c22eab6..82b034455d6ae 100644 --- a/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.c +++ b/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.c @@ -26,8 +26,7 @@ #include "CBiosCallbacks.h" #include "../Device/CBiosChipShare.h" -CALLBACK_cbVsprintf cbVsprintf = CBIOS_NULL; -CALLBACK_cbVsnprintf cbVsnprintf = CBIOS_NULL; +CALLBACK_cbVDbgPrint cbVDbgPrint = CBIOS_NULL; CBIOS_CALLBACK_FUNCTIONS FnCallback = {0}; @@ -60,13 +59,10 @@ CBIOS_STATUS cbSetCallBackFunctions(PCBIOS_CALLBACK_FUNCTIONS pFnCallBack) pFnCallBack->pFnDbgPrintToFile = CBIOS_NULL; - cbVsprintf = pFnCallBack->pFnVsprintf; - - cbVsnprintf = pFnCallBack->pFnVsnprintf; + cbVDbgPrint = pFnCallBack->pFnVDbgPrint; //FnCallback = *pFnCallBack; FnCallback.Size=pFnCallBack->Size; - FnCallback.pFnDbgPrint=pFnCallBack->pFnDbgPrint; FnCallback.pFnDelayMicroSeconds=pFnCallBack->pFnDelayMicroSeconds; FnCallback.pFnReadUchar=pFnCallBack->pFnReadUchar; FnCallback.pFnReadUshort=pFnCallBack->pFnReadUshort; @@ -114,20 +110,10 @@ CBIOS_STATUS cbSetCallBackFunctions(PCBIOS_CALLBACK_FUNCTIONS pFnCallBack) FnCallback.pFnRegulatorGetVoltage=pFnCallBack->pFnRegulatorGetVoltage; FnCallback.pFnRegulatorSetVoltage=pFnCallBack->pFnRegulatorSetVoltage; FnCallback.pFnRegulatorPut=pFnCallBack->pFnRegulatorPut; + FnCallback.pFnVDbgPrint = pFnCallBack->pFnVDbgPrint; return CBIOS_OK; } -CBIOS_VOID cb_DbgPrint(CBIOS_U32 DebugPrintLevel, PCBIOS_UCHAR DebugMessage) -{ - if (FnCallback.pFnDbgPrint != CBIOS_NULL) - { - ((CALLBACK_cbDbgPrint)FnCallback.pFnDbgPrint)(DebugPrintLevel,DebugMessage); - } - else - { - return; - } -} CBIOS_VOID cb_DelayMicroSeconds(CBIOS_U32 Microseconds) { @@ -299,8 +285,7 @@ CBIOS_S32 cb_strcmp(PCBIOS_UCHAR s1, const CBIOS_UCHAR* s2) } else { - //old driver has no callback function, then use standard lib function - Ret = cbstrcmp(s1, s2); + Ret = cbStrCmp(s1, s2); } return Ret; @@ -317,8 +302,7 @@ PCBIOS_CHAR cb_strcpy(PCBIOS_CHAR s1, PCBIOS_CHAR s2) } else { - //old driver has no callback function, then use standard lib function - Ret = cbstrcpy(s1, s2); + Ret = cbStrCpy(s1, s2); } return Ret; @@ -335,8 +319,7 @@ CBIOS_S32 cb_strncmp(PCBIOS_UCHAR s1, PCBIOS_UCHAR s2, CBIOS_U32 length) } else { - //old driver has no callback function, then use standard lib function - Ret = cbstrncmp(s1, s2, length); + Ret = cbStrnCmp(s1, s2, length); } return Ret; @@ -353,8 +336,7 @@ PCBIOS_VOID cb_memset(PCBIOS_VOID pBuf, CBIOS_S32 value, CBIOS_U32 length) } else { - //old driver has no callback function, then use standard lib function - Ret = cbmemset(pBuf, value, length); + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: callback func is not defined!\n", FUNCTION_NAME)); } return Ret; @@ -371,8 +353,7 @@ PCBIOS_VOID cb_memcpy(PCBIOS_VOID pBuf1, PCBIOS_VOID pBuf2, CBIOS_U32 length) } else { - //old driver has no callback function, then use standard lib function - Ret = cbmemcpy(pBuf1, pBuf2, length); + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: callback func is not defined!\n", FUNCTION_NAME)); } return Ret; @@ -389,8 +370,7 @@ CBIOS_S32 cb_memcmp(PCBIOS_VOID pBuf1, PCBIOS_VOID pBuf2, CBIOS_U32 length) } else { - //old driver has no callback function, then use standard lib function - Ret = cbmemcmp(pBuf1, pBuf2, length); + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: callback func is not defined!\n", FUNCTION_NAME)); } return Ret; @@ -409,7 +389,7 @@ CBIOS_U64 cb_do_div(CBIOS_U64 a, CBIOS_U64 b) } else { - Ret = cbdo_div(a, b); + Ret = 0; } return Ret; diff --git a/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.h b/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.h index 4fddb9f8b160d..8993902f97dd3 100644 --- a/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.h +++ b/drivers/gpu/drm/arise/cbios/Callback/CBiosCallbacks.h @@ -30,21 +30,13 @@ #define CBIOS_DBG_PRINT 1 #if CBIOS_DBG_PRINT -#ifdef __LINUX__ -#define cbDebugPrint1(DebugCtlFlag, DebugMessage, args...) \ - do{ \ - CBIOS_UCHAR* pDbgBuff = cbGetDebugBuffer(DebugCtlFlag); \ - if(pDbgBuff != CBIOS_NULL && cbVsnprintf != CBIOS_NULL) \ - { \ - CBIOS_U32 preLen = cbAddPrefix(DebugCtlFlag, pDbgBuff); \ - cbVsnprintf(pDbgBuff + preLen, CBIOSDEBUGMESSAGEMAXBYTES-preLen-1, DebugMessage, ##args); \ - cbPrintWithDbgFlag(DebugCtlFlag, pDbgBuff);\ - } \ - }while(0) -#define cbDebugPrint(arg) cbDebugPrint1 arg -#else -#define cbDebugPrint(arg) cbPrintMessage arg -#endif +#define cbDebugPrint(arg) \ +do{ \ + if(cbVDbgPrint != CBIOS_NULL) \ + { \ + cbVDbgPrint arg; \ + } \ +}while(0) #else /*else DBG*/ #define cbDebugPrint(arg) #endif @@ -85,21 +77,16 @@ typedef PCBIOS_VOID (*CALLBACK_cbMemSet)(PCBIOS_VOID pBuf, CBIOS_S32 value, CB typedef PCBIOS_VOID (*CALLBACK_cbMemCpy)(PCBIOS_VOID pBuf1, PCBIOS_VOID pBuf2, CBIOS_U32 length); typedef CBIOS_S32 (*CALLBACK_cbMemCmp)(PCBIOS_VOID pBuf1, PCBIOS_VOID pBuf2, CBIOS_U32 length); typedef CBIOS_U64 (*CALLBACK_cbDoDiv)(CBIOS_U64 a, CBIOS_U64 b); -#ifdef __LINUX__ -typedef CBIOS_S32 (*CALLBACK_cbVsprintf)(PCBIOS_UCHAR buf, PCBIOS_CHAR fmt, ...); -typedef CBIOS_S32 (*CALLBACK_cbVsnprintf)(PCBIOS_UCHAR buf, CBIOS_U32 size, PCBIOS_CHAR fmt, ...); -#else -typedef CBIOS_S32 (*CALLBACK_cbVsprintf)(PCBIOS_UCHAR buf, PCBIOS_CHAR fmt, va_list args); -typedef CBIOS_S32 (*CALLBACK_cbVsnprintf)(PCBIOS_UCHAR buf, CBIOS_U32 size, PCBIOS_CHAR fmt, va_list args); -#endif +typedef CBIOS_VOID (*CALLBACK_cbVDbgPrint)(CBIOS_BOOL bEnablePrint, CBIOS_U32 PrintLevel, PCBIOS_UCHAR PrefixStr, PCBIOS_UCHAR DbgMsg, ...); + +extern CALLBACK_cbVDbgPrint cbVDbgPrint; + -extern CALLBACK_cbVsprintf cbVsprintf; -extern CALLBACK_cbVsnprintf cbVsnprintf; CBIOS_STATUS cbSetCallBackFunctions(PCBIOS_CALLBACK_FUNCTIONS pFnCallBack); //******** Debug Print functions ******************************* -CBIOS_VOID cb_DbgPrint(CBIOS_U32 DebugPrintLevel, PCBIOS_UCHAR DebugMessage); + //******** time delay functions ******************************** CBIOS_VOID cb_DelayMicroSeconds(CBIOS_U32 Microseconds); diff --git a/drivers/gpu/drm/arise/cbios/Device/CBiosShare.c b/drivers/gpu/drm/arise/cbios/Device/CBiosShare.c index 36fb4ff6c1871..6142d631589c9 100644 --- a/drivers/gpu/drm/arise/cbios/Device/CBiosShare.c +++ b/drivers/gpu/drm/arise/cbios/Device/CBiosShare.c @@ -25,24 +25,20 @@ #include "CBiosShare.h" #include "CBiosChipShare.h" -#define BACK_BUFFER_COUNT 64 static CBIOS_U32 ModuleMask = 0; static CBIOS_U32 MaxDbgLevel = 2; static CBIOS_U32 ModuleMaskLevel = 0x3; -static CBIOS_UCHAR* pDebugBuf = CBIOS_NULL; -static CBIOS_UCHAR* pBackBuf = CBIOS_NULL; -static CBIOS_BOOL bEnableBackOutput = CBIOS_FALSE; -static CBIOS_U32 TimeStamp = 0; -static CBIOS_U32 BackBufIndex = 0; +static CBIOS_UCHAR DbgBuffer[CBIOSDEBUGMESSAGEMAXBYTES]; + CBIOS_UCHAR* ModuleName[] = { - (CBIOS_UCHAR*)"[DISP] General ", - (CBIOS_UCHAR*)"[DISP] MHL ", - (CBIOS_UCHAR*)"[DISP] DSI ", - (CBIOS_UCHAR*)"[DISP] HDMI ", - (CBIOS_UCHAR*)"[DISP] DP ", + (CBIOS_UCHAR*)"[GFDISP] General ", + (CBIOS_UCHAR*)"[GFDISP] MHL ", + (CBIOS_UCHAR*)"[GFDISP] DSI ", + (CBIOS_UCHAR*)"[GFDISP] HDMI ", + (CBIOS_UCHAR*)"[GFDISP] DP ", }; CBIOS_UCHAR* DebugLevelName[] = @@ -54,186 +50,64 @@ CBIOS_UCHAR* DebugLevelName[] = (CBIOS_UCHAR*)"Trace: ", }; - -#ifndef __LINUX__ -CBIOS_VOID cbPrintMessage(CBIOS_U32 DebugPrintLevel, CBIOS_CHAR *DebugMessage, ...) -{ - va_list args; - CBIOS_UCHAR *pDebugString; - CBIOS_BOOL isSkipPrint = CBIOS_TRUE; - CBIOS_U32 preLen = 0; - - if(((DebugPrintLevel & 0xFF) <= MaxDbgLevel) || ((DebugPrintLevel & ModuleMask) &&((DebugPrintLevel & 0xFF) <= ModuleMaskLevel ))) - { - isSkipPrint = CBIOS_FALSE; - } - - if (isSkipPrint) - { - return; - } - - pDebugString = cbGetDebugBuffer(DebugPrintLevel & 0xFFFF); - - if(pDebugString == CBIOS_NULL) - { - return; - } - - preLen = cbAddPrefix(DebugPrintLevel, pDebugString); - - va_start(args, DebugMessage); - - if (cbVsprintf != CBIOS_NULL) - { - //new driver has the callback function - cbVsprintf(pDebugString + preLen, DebugMessage, args); - } - else - { - - //old driver has no callback function, then use standard lib function - vsprintf(pDebugString + preLen, DebugMessage, args); - - } - - va_end(args); - - cb_DbgPrint((DebugPrintLevel & 0xFF), pDebugString); - - return; -} -#endif - -CBIOS_VOID cbDelayMilliSeconds(CBIOS_U32 Milliseconds) -{ - cb_DelayMicroSeconds(1000*Milliseconds); -} - -CBIOS_U32 cbAddPrefix(CBIOS_U32 Level, CBIOS_UCHAR* pBuffer) +CBIOS_UCHAR* cbGetDebugPrefix(CBIOS_U32 Level) { CBIOS_U32 index = 0; - pBuffer[0] = '\0'; - -#ifdef __LINUX__ - if((Level & 0xFF000000) == BACK_OUTPUT && cbVsnprintf != CBIOS_NULL) - { - cbVsnprintf(pBuffer, CBIOSDEBUGMESSAGEMAXBYTES, "%d.", TimeStamp); - TimeStamp++; - } -#endif + DbgBuffer[0] = '\0'; Level &= 0xFFFF; - if(Level >> 8) - { - index = cbGetLastBitIndex(Level >> 8); - } + index = Level >> 8; if (index < sizeofarray(ModuleName)) { - cbStrCat(pBuffer, ModuleName[index]); + cbStrCat(DbgBuffer, ModuleName[index]); } index = Level & 0xff; if (index < sizeofarray(DebugLevelName)) { - cbStrCat(pBuffer, DebugLevelName[index]); + cbStrCat(DbgBuffer, DebugLevelName[index]); } - return cbStrLen(pBuffer); + return DbgBuffer; } -CBIOS_VOID cbPrintWithDbgFlag(CBIOS_U32 DbgFlag, CBIOS_UCHAR* pBuffer) +CBIOS_BOOL cbCheckDebugLevel(CBIOS_U32 DbgFlag) { - if((DbgFlag & 0xFF000000) == BACK_OUTPUT) + CBIOS_U32 Level = DbgFlag & 0xFF; + CBIOS_U32 ModuIndex = (DbgFlag >> 8) & 0xFF; + + if((Level <= MaxDbgLevel) || (((1 << ModuIndex) & ModuleMask) &&(Level <= ModuleMaskLevel ))) { - return; + return CBIOS_TRUE; } - - if(((DbgFlag & 0xFF) <= MaxDbgLevel) || ((DbgFlag & ModuleMask) &&((DbgFlag & 0xFF) <= ModuleMaskLevel ))) + else { - if(pBuffer != CBIOS_NULL) - { - cb_DbgPrint(0, pBuffer); - } + return CBIOS_FALSE; } } +CBIOS_VOID cbDelayMilliSeconds(CBIOS_U32 Milliseconds) +{ + cb_DelayMicroSeconds(1000*Milliseconds); +} + CBIOS_STATUS cbDbgLevelCtl(PCBIOS_DBG_LEVEL_CTRL pDbgLevelCtl) { - CBIOS_U32 BackBufCtrl = 0; + if(pDbgLevelCtl->bGetValue) { - pDbgLevelCtl->DbgLevel = MaxDbgLevel | ModuleMask | (ModuleMaskLevel << 16); - pDbgLevelCtl->DbgLevel |= ((bEnableBackOutput)? 1 : 0) << 24; + pDbgLevelCtl->DbgLevel = MaxDbgLevel |(ModuleMask << 8)| (ModuleMaskLevel << 16); } else { ModuleMaskLevel = (pDbgLevelCtl->DbgLevel >> 16) & 0xFF; - ModuleMask = pDbgLevelCtl->DbgLevel & 0xFF00; + ModuleMask = (pDbgLevelCtl->DbgLevel >> 8) & 0xFF; MaxDbgLevel = pDbgLevelCtl->DbgLevel & 0xFF; - BackBufCtrl = pDbgLevelCtl->DbgLevel >> 24; - bEnableBackOutput = (BackBufCtrl && BackBufCtrl != 0xFF)? CBIOS_TRUE : CBIOS_FALSE; - if(BackBufCtrl == 0xFF) - { - CBIOS_U32 Index = 0; - CBIOS_UCHAR* pBuffer = CBIOS_NULL; - if(pBackBuf) - { - for(Index = 0; Index < BACK_BUFFER_COUNT; Index++) - { - pBuffer = pBackBuf + Index * CBIOSDEBUGMESSAGEMAXBYTES; - cb_DbgPrint(0, pBuffer); - } - cb_FreePool(pBackBuf); - pBackBuf = CBIOS_NULL; - } - } } return CBIOS_OK; } -CBIOS_UCHAR* cbGetDebugBuffer(CBIOS_U32 DbgFlag) -{ - CBIOS_UCHAR* pBuffer = CBIOS_NULL; - if((DbgFlag & 0xFF000000) == BACK_OUTPUT) - { - if(bEnableBackOutput) - { - if(pBackBuf == CBIOS_NULL) - { - pBackBuf = (CBIOS_UCHAR*)cb_AllocateNonpagedPool(CBIOSDEBUGMESSAGEMAXBYTES * BACK_BUFFER_COUNT); - BackBufIndex = 0; - TimeStamp = 0; - } - pBuffer = pBackBuf + BackBufIndex * CBIOSDEBUGMESSAGEMAXBYTES; - BackBufIndex = (BackBufIndex+1) % BACK_BUFFER_COUNT; - } - } - else - { - if(pDebugBuf == CBIOS_NULL) - { - pDebugBuf = (CBIOS_UCHAR*)cb_AllocateNonpagedPool(CBIOSDEBUGMESSAGEMAXBYTES); - } - pBuffer = pDebugBuf; - } - return pBuffer; -} - -CBIOS_VOID cbReleaseDebugBuffer(CBIOS_VOID) -{ - if(pDebugBuf != CBIOS_NULL) - { - cb_FreePool(pDebugBuf); - pDebugBuf = CBIOS_NULL; - } - if(pBackBuf != CBIOS_NULL) - { - cb_FreePool(pBackBuf); - pBackBuf = CBIOS_NULL; - } -} CBIOS_BOARD_VERSION cbGetBoardVersion(PCBIOS_VOID pvcbe) { @@ -387,4 +261,69 @@ CBIOS_U32 cbRound(CBIOS_U32 Dividend, CBIOS_U32 Divisor, CBIOS_ROUND_METHOD Roun } +CBIOS_S32 cbStrnCmp(CBIOS_UCHAR *pStr1, CBIOS_UCHAR * pStr2, CBIOS_U32 Lenth) +{ + CBIOS_U32 i = 0; + CBIOS_S32 Ret = 0; + + if(!pStr1 || !pStr2) + { + return 0; + } + + for(i = 0; i < Lenth; i++) + { + if(!pStr1[i] || !pStr2[i] || (pStr1[i] != pStr2[i])) + { + Ret = pStr1[i] - pStr2[i]; + break; + } + } + + return Ret; +} + +CBIOS_S32 cbStrCmp(CBIOS_UCHAR *pStr1, const CBIOS_UCHAR * pStr2) +{ + CBIOS_S32 Ret = 0; + + if(!pStr1 || !pStr2) + { + return 0; + } + + while(*pStr1 == *pStr2) + { + if(*pStr1 == '\0') + { + return 0; + } + pStr1++; + pStr2++; + } + Ret = *pStr1 -*pStr2; + + return Ret; +} + +PCBIOS_UCHAR cbStrCpy(CBIOS_UCHAR *pStrDst, CBIOS_UCHAR * pStrSrc) +{ + CBIOS_UCHAR *pTmp = pStrDst; + + if(!pStrDst || !pStrSrc) + { + return CBIOS_NULL; + } + + while(*pStrSrc) + { + *pTmp++ = *pStrSrc++; + } + + *pTmp = '\0'; + + return pStrDst; +} + + diff --git a/drivers/gpu/drm/arise/cbios/Device/CBiosShare.h b/drivers/gpu/drm/arise/cbios/Device/CBiosShare.h index dbbb0bcb0ffb5..7b53477fa90a7 100644 --- a/drivers/gpu/drm/arise/cbios/Device/CBiosShare.h +++ b/drivers/gpu/drm/arise/cbios/Device/CBiosShare.h @@ -25,25 +25,16 @@ #ifndef _CBIOS_SHARE_H_ #define _CBIOS_SHARE_H_ -#ifdef __LINUX__ -#define GCC_BUILD_CBIOS 1 -#endif +#ifndef __LINUX__ -#ifndef GCC_BUILD_CBIOS -#include -#include -#include -#pragma warning(disable:4311) -#ifndef inline -#define inline __inline -#endif #ifndef __func__ #define __func__ __FUNCTION__ #endif -#else -#ifndef __LINUX__ -#include "gcc_stdarg.h" + +#ifndef inline +#define inline __inline #endif + #endif #include "../CBios.h" @@ -57,11 +48,9 @@ #define FUNCTION_NAME __FUNCTION__ #endif -#ifdef __LINUX__ -#define LINE_NUM __LINE__ -#else + #define LINE_NUM __LINE__ -#endif + #ifndef ASSERT #if defined(DBG) && defined(WIN32) @@ -100,13 +89,10 @@ typedef enum _CBIOS_ACTIVE_TYPE { #define CBIOS_BOARD_VERSION_DEFAULT CBIOS_BOARD_VERSION_1 -#ifndef CBIOSDEBUGMESSAGEMAXBYTES -#define CBIOSDEBUGMESSAGEMAXBYTES 256 -#endif +#define CBIOSDEBUGMESSAGEMAXBYTES 64 + -#define ELT2K_HARDCODE_DP5 0 #define ELT2K_HARDCODE_DSI_CMDMODE 0 -#define ELT2K_HARDCODE_DSI_MHL 0 /******* these functions must be implemented outside *******/ /* debug print function */ @@ -117,17 +103,19 @@ typedef enum _CBIOS_ACTIVE_TYPE { #define DBG_LEVEL_DEBUG 3 #define DBG_LEVEL_TRACE 4 -#define GENERIC_MODULE (1 << 8) -#define MHL_MODULE (2 << 8) -#define DSI_MODULE (4 << 8) -#define HDMI_MODULE (8 << 8) -#define DP_MODULE (16 << 8) +typedef enum _DEBUG_MODULE +{ + GENERIC_MODULE = 0, + MHL_MODULE = 1, + DSI_MODULE = 2, + HDMI_MODULE = 3, + DP_MODULE = 4, + DBG_MODULE_NUM = 5, +}DEBUG_MODULE; + -#define STD_OUTPUT (0 << 24) -#define BACK_OUTPUT (1<< 24) -#define MAKE_LEVEL(Module, Level) (Module##_MODULE + DBG_LEVEL_##Level) -#define MAKE_LEVEL_EX(Out, Module, Level) (Out##_OUTPUT + Module##_MODULE + DBG_LEVEL_##Level) +#define MAKE_LEVEL(Module, Level) cbCheckDebugLevel((Module##_MODULE << 8) + DBG_LEVEL_##Level), DBG_LEVEL_##Level, cbGetDebugPrefix((Module##_MODULE << 8) + DBG_LEVEL_##Level) #define cbTraceEnter(Module) cbDebugPrint((MAKE_LEVEL(Module, TRACE), "%s: Enter\n", __func__)) #define cbTraceExit(Module) cbDebugPrint((MAKE_LEVEL(Module, TRACE), "%s: Exit\n", __func__)) @@ -179,19 +167,16 @@ typedef enum _CBIOS_ROUND_METHOD ROUND_NEAREST }CBIOS_ROUND_METHOD; -#ifndef __LINUX__ -CBIOS_VOID cbPrintMessage(CBIOS_U32 DebugPrintLevel, CBIOS_CHAR *DebugMessage, ...); -#endif - -CBIOS_U32 cbAddPrefix(CBIOS_U32 Level, CBIOS_UCHAR* pBuffer); -CBIOS_VOID cbPrintWithDbgFlag(CBIOS_U32 DbgFlag, CBIOS_UCHAR* pBuffer); +CBIOS_UCHAR* cbGetDebugPrefix(CBIOS_U32 Level); +CBIOS_BOOL cbCheckDebugLevel(CBIOS_U32 DbgFlag); CBIOS_STATUS cbDbgLevelCtl(PCBIOS_DBG_LEVEL_CTRL pDbgLevelCtl); -CBIOS_UCHAR* cbGetDebugBuffer(CBIOS_U32 DbgFlag); -CBIOS_VOID cbReleaseDebugBuffer(CBIOS_VOID); CBIOS_VOID cbDelayMilliSeconds(CBIOS_U32 Milliseconds); CBIOS_BOOL cbItoA(CBIOS_U32 ulValue, CBIOS_U8 *pStr, CBIOS_U8 byRadix, CBIOS_U32 ulLength); CBIOS_U32 cbStrLen(CBIOS_UCHAR * pStrSrc); PCBIOS_UCHAR cbStrCat(CBIOS_UCHAR *pStrDst, CBIOS_UCHAR * pStrSrc); +CBIOS_S32 cbStrnCmp(CBIOS_UCHAR *pStr1, CBIOS_UCHAR * pStr2, CBIOS_U32 Lenth); +CBIOS_S32 cbStrCmp(CBIOS_UCHAR *pStr1, const CBIOS_UCHAR * pStr2); +PCBIOS_UCHAR cbStrCpy(CBIOS_UCHAR *pStrDst, CBIOS_UCHAR * pStrSrc); CBIOS_U32 cbRound(CBIOS_U32 Dividend, CBIOS_U32 Divisor, CBIOS_ROUND_METHOD RoundMethod); CBIOS_BOARD_VERSION cbGetBoardVersion(PCBIOS_VOID pvcbe); CBIOS_STATUS cbGetExtensionSize(CBIOS_U32 *pulExtensionSize); @@ -217,30 +202,6 @@ static inline CBIOS_U32 cb_swab32(CBIOS_U32 x) #define cb_swab32(x) x #endif -#ifdef __LINUX__ - -#define cbstrcmp(s1, s2) 0 -#define cbstrcpy(s1, s2) CBIOS_NULL -#define cbstrncmp(s1, s2, n) 0 -#define cbmemset(s1, v, n) CBIOS_NULL -#define cbmemcpy(s1, s2, n) CBIOS_NULL -#define cbmemcmp(s1, s2, n) 0 -#define cbdo_div(a, b) 0 -#define cbvsprintf(s, f, ...) 0 - -#else - -#define cbstrcmp strcmp -#define cbstrcpy strcpy -#define cbstrncmp strncmp -#define cbmemset memset -#define cbmemcpy memcpy -#define cbmemcmp memcmp -#define cbdo_div(a, b) ((a)/(b)) - -#define cbvsprintf vsprintf - -#endif #endif /* _CBIOS_SHARE_H_ */ diff --git a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.c b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.c index 065e6f980d4e8..c619527093a18 100644 --- a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.c +++ b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.c @@ -140,8 +140,8 @@ static CBIOS_BOOL cbDPMonitor_LinkTrainingHw(PCBIOS_EXTENSION_COMMON pcbe, PCBIO bStatus = cbDIU_DP_LinkTrainingHw(pcbe, DPModuleIndex, &LinkTrainingParams); if (bStatus) { - pDPMonitorContext->LinkSpeedToUse = LinkTrainingParams.CurrLinkSpeed; - pDPMonitorContext->LaneNumberToUse = LinkTrainingParams.CurrLaneCount; + pDPMonitorContext->LinkPassSpeed = LinkTrainingParams.CurrLinkSpeed; + pDPMonitorContext->LinkPassLaneNum = LinkTrainingParams.CurrLaneCount; } cbTraceExit(DP); @@ -155,6 +155,7 @@ static CBIOS_BOOL cbDPMonitor_GetAutoTestDpcdData(PCBIOS_EXTENSION_COMMON pcbe, AUX_CONTROL AUX; DPCD_REG_00219 DPCD_00219; DPCD_REG_00220 DPCD_00220; + CBIOS_U32 LaneNum = 0, LinkSpeed = 0; AUX.Function = CBIOS_AUX_REQUEST_NATIVE_READ; AUX.Offset = 0x219; @@ -168,15 +169,15 @@ static CBIOS_BOOL cbDPMonitor_GetAutoTestDpcdData(PCBIOS_EXTENSION_COMMON pcbe, DPCD_00219.Value = AUX.Data[0] & 0x000000FF; if (DPCD_00219.TEST_LINK_RATE == CBIOS_DPCD_LINK_RATE_5400Mbps) { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_5400Mbps; + LinkSpeed = CBIOS_DP_LINK_SPEED_5400Mbps; } else if (DPCD_00219.TEST_LINK_RATE == CBIOS_DPCD_LINK_RATE_2700Mbps) { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_2700Mbps; + LinkSpeed = CBIOS_DP_LINK_SPEED_2700Mbps; } else { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_1620Mbps; + LinkSpeed = CBIOS_DP_LINK_SPEED_1620Mbps; } AUX.Function = CBIOS_AUX_REQUEST_NATIVE_READ; @@ -190,13 +191,17 @@ static CBIOS_BOOL cbDPMonitor_GetAutoTestDpcdData(PCBIOS_EXTENSION_COMMON pcbe, DPCD_00220.Value = AUX.Data[0] & 0x000000FF; if ((DPCD_00220.TEST_LANE_COUNT == 0x01) || (DPCD_00220.TEST_LANE_COUNT == 0x02) || (DPCD_00220.TEST_LANE_COUNT == 0x04)) { - pDPMonitorContext->LaneNumberToUse = DPCD_00220.TEST_LANE_COUNT; + LaneNum = DPCD_00220.TEST_LANE_COUNT; } else { - cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: Invalid lane count:%d!\n", FUNCTION_NAME, DPCD_00220.TEST_LANE_COUNT)); + cbDebugPrint((MAKE_LEVEL(DP, ERROR), "%s: Invalid lane count:%d!\n", FUNCTION_NAME, DPCD_00220.TEST_LANE_COUNT)); + return CBIOS_FALSE; } + pDPMonitorContext->LaneNumberToUse = LaneNum; + pDPMonitorContext->LinkSpeedToUse = LinkSpeed; + return CBIOS_TRUE; } @@ -214,25 +219,6 @@ static CBIOS_BOOL cbDPMonitor_GetSinkCapsFromSpecificPlace(PCBIOS_EXTENSION_COMM } else { - if (pDPMonitorContext->LaneNumberToUse > 4) - { - pDPMonitorContext->LaneNumberToUse = 4; // Default use 4 lanes - cbDebugPrint((MAKE_LEVEL(DP, DEBUG), "%s: Use default 4 lanes!\n", FUNCTION_NAME)); - } - - if ((pDPMonitorContext->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_1620Mbps) && - (pDPMonitorContext->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_2700Mbps) && - (pDPMonitorContext->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_5400Mbps)) - { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_1620Mbps; - cbDebugPrint((MAKE_LEVEL(DP, DEBUG),"%s: Use default 1.62Gbps!\n", FUNCTION_NAME)); - } - pDPMonitorContext->EnhancedMode = pDPMonitorContext->bSupportEnhanceMode; - pDPMonitorContext->AsyncMode = 0x01; - pDPMonitorContext->DynamicRange = 0; - pDPMonitorContext->YCbCrCoefficients = 0; - pDPMonitorContext->TUSize = DP_Default_TUSize; - return CBIOS_FALSE; } @@ -254,19 +240,31 @@ static CBIOS_BOOL cbDPMonitor_GetSinkCapsFromSpecificPlace(PCBIOS_EXTENSION_COMM pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_1620Mbps; } - pDPMonitorContext->bpc = pUserTiming->BitDepthPerComponet; + if(pUserTiming->DClk) + { + pDPMonitorContext->bpc = pUserTiming->BitDepthPerComponet; - pDPMonitorContext->AsyncMode = (pUserTiming->ClockSynAsyn == 0) ? 1 : 0; - pDPMonitorContext->ColorFormat = pUserTiming->ColorFormat; - pDPMonitorContext->DynamicRange = pUserTiming->DynamicRange; - pDPMonitorContext->YCbCrCoefficients = pUserTiming->YCbCrCoefficients; - pDPMonitorContext->EnhancedMode = pUserTiming->EnhancedFrameMode; + pDPMonitorContext->AsyncMode = (pUserTiming->ClockSynAsyn == 0) ? 1 : 0; + pDPMonitorContext->ColorFormat = pUserTiming->ColorFormat; + pDPMonitorContext->DynamicRange = pUserTiming->DynamicRange; + pDPMonitorContext->YCbCrCoefficients = pUserTiming->YCbCrCoefficients; + pDPMonitorContext->EnhancedMode = pUserTiming->EnhancedFrameMode; + } cbDebugPrint((MAKE_LEVEL(DP, DEBUG), "%s: LinkRate = %d, LaneCount = %d, bpc = %d, Async = %d\n", FUNCTION_NAME, pDPMonitorContext->LinkSpeedToUse, pDPMonitorContext->LaneNumberToUse, pDPMonitorContext->bpc, pDPMonitorContext->AsyncMode)); cbDebugPrint((MAKE_LEVEL(DP, DEBUG), "%s: ColorFormat = %d, DynamicRange = %d, YCbCrCoefficients = %d, EnhancedMode = %d\n", FUNCTION_NAME, pDPMonitorContext->ColorFormat,pDPMonitorContext->DynamicRange, pDPMonitorContext->YCbCrCoefficients, pDPMonitorContext->EnhancedMode)); + /*In order to pass dp cts on unigraf DPR-120, use max link rate and max lane count, + because dpcd timing perhaps don't update, but these two params update everytime. + */ + if(pcbe->SpecifyDestTimingSrc[IGAIndex].Flag == 2) + { + pDPMonitorContext->LinkSpeedToUse = pDPMonitorContext->SinkMaxLinkSpeed; + pDPMonitorContext->LaneNumberToUse = pDPMonitorContext->SinkMaxLaneCount; + } + return CBIOS_TRUE; } else @@ -282,7 +280,8 @@ static CBIOS_VOID cbDPMonitor_DetermineLinkTrainingPara(PCBIOS_EXTENSION_COMMON CBIOS_MODULE_INDEX DPModuleIndex = cbGetModuleIndex(pcbe, pDPMonitorContext->pDevCommon->DeviceType, CBIOS_MODULE_TYPE_DP); PCBIOS_DP_CONTEXT pDpContext = container_of(pDPMonitorContext->pDevCommon, PCBIOS_DP_CONTEXT, Common); PCBIOS_EDPPanel_PARAMS pEDPPanelDevice = &(pDPMonitorContext->pDevCommon->DeviceParas.EDPPanelDevice); - CBIOS_BOOL bUsingSinkMax = CBIOS_FALSE; + CBIOS_U32 LinkSpeed = 0, LaneNum = 0; + CBIOS_BOOL bGotLinkPara = CBIOS_FALSE; IGAIndex = DPModuleIndex; @@ -293,92 +292,72 @@ static CBIOS_VOID cbDPMonitor_DetermineLinkTrainingPara(PCBIOS_EXTENSION_COMMON pcbe->SpecifyDestTimingSrc[IGAIndex].Flag = 2; } - if((pcbe->SpecifyDestTimingSrc[IGAIndex].Flag == 2) && (pDPMonitorContext->TestDpcdDataTiming.DClk == 0)) - { - pcbe->SpecifyDestTimingSrc[IGAIndex].Flag = 0; - bUsingSinkMax = CBIOS_TRUE; - } - if (isAutoTest) { - cbDPMonitor_GetAutoTestDpcdData(pcbe, pDPMonitorContext); + bGotLinkPara = cbDPMonitor_GetAutoTestDpcdData(pcbe, pDPMonitorContext); } else if (pcbe->SpecifyDestTimingSrc[IGAIndex].Flag & 0x03) { - cbDPMonitor_GetSinkCapsFromSpecificPlace(pcbe, pDPMonitorContext, IGAIndex); - - /*In order to pass dp cts on unigraf DPR-120, use max link rate and max lane count, - because dpcd timing perhaps don't update, but these two params update everytime. - */ - if(pcbe->SpecifyDestTimingSrc[IGAIndex].Flag == 2) - { - pDPMonitorContext->LinkSpeedToUse = pDPMonitorContext->SinkMaxLinkSpeed; - pDPMonitorContext->LaneNumberToUse = pDPMonitorContext->SinkMaxLaneCount; - } + bGotLinkPara = cbDPMonitor_GetSinkCapsFromSpecificPlace(pcbe, pDPMonitorContext, IGAIndex); } - else + + if(!bGotLinkPara) { if(pDPMonitorContext->bpc > DP_Default_bpc) { pDPMonitorContext->bpc = DP_Default_bpc; } - pDPMonitorContext->LaneNumberToUse = pDPMonitorContext->SinkMaxLaneCount; + LaneNum = pDPMonitorContext->SinkMaxLaneCount; // choose Link Speed according to current mode's pixel clock - MaxSupportClock_2700Mbps = (CBIOS_DP_LINK_SPEED_2700Mbps / (pDPMonitorContext->bpc * 3)) - * pDPMonitorContext->LaneNumberToUse * 8; - MaxSupportClock_1620Mbps = (CBIOS_DP_LINK_SPEED_1620Mbps / (pDPMonitorContext->bpc * 3)) - * pDPMonitorContext->LaneNumberToUse * 8; + MaxSupportClock_2700Mbps = (CBIOS_DP_LINK_SPEED_2700Mbps / (pDPMonitorContext->bpc * 3)) * LaneNum * 8; + MaxSupportClock_1620Mbps = (CBIOS_DP_LINK_SPEED_1620Mbps / (pDPMonitorContext->bpc * 3)) * LaneNum * 8; if (pDPMonitorContext->TargetTiming.PixelClock < MaxSupportClock_1620Mbps) { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_1620Mbps; + LinkSpeed = CBIOS_DP_LINK_SPEED_1620Mbps; } else if (pDPMonitorContext->TargetTiming.PixelClock < MaxSupportClock_2700Mbps) { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_2700Mbps; + LinkSpeed = CBIOS_DP_LINK_SPEED_2700Mbps; } else { - pDPMonitorContext->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_5400Mbps; + LinkSpeed = CBIOS_DP_LINK_SPEED_5400Mbps; } - if (pDPMonitorContext->LinkSpeedToUse > pDPMonitorContext->SinkMaxLinkSpeed) + if (LinkSpeed > pDPMonitorContext->SinkMaxLinkSpeed) { - pDPMonitorContext->LinkSpeedToUse = pDPMonitorContext->SinkMaxLinkSpeed; - } - - if(bUsingSinkMax)//for dp cts - { - pDPMonitorContext->LinkSpeedToUse = pDPMonitorContext->SinkMaxLinkSpeed; - pDPMonitorContext->LaneNumberToUse = pDPMonitorContext->SinkMaxLaneCount; + LinkSpeed = pDPMonitorContext->SinkMaxLinkSpeed; } if(cbDPMonitor_IsEDPSupported(pcbe, DPModuleIndex)) { if(pEDPPanelDevice &&pEDPPanelDevice->EDPPanelDesc.EDPCaps.isHardcodeLinkPara) { - pDPMonitorContext->LinkSpeedToUse = pEDPPanelDevice->EDPPanelDesc.EDPCaps.LinkSpeed; - pDPMonitorContext->LaneNumberToUse = pEDPPanelDevice->EDPPanelDesc.EDPCaps.LaneNum; + LinkSpeed = pEDPPanelDevice->EDPPanelDesc.EDPCaps.LinkSpeed; + LaneNum = pEDPPanelDevice->EDPPanelDesc.EDPCaps.LaneNum; } else { - pDPMonitorContext->LinkSpeedToUse = pDPMonitorContext->SinkMaxLinkSpeed; - pDPMonitorContext->LaneNumberToUse = pDPMonitorContext->SinkMaxLaneCount; + LinkSpeed = pDPMonitorContext->SinkMaxLinkSpeed; + LaneNum = pDPMonitorContext->SinkMaxLaneCount; } } /* To avoid exceeding max clock when lighten 10bpc or higher, use default bpc*/ - MaxClockForCurrentLinkSpeed = (pDPMonitorContext->LinkSpeedToUse / (pDPMonitorContext->bpc * 3)) - * pDPMonitorContext->LaneNumberToUse * 8; - if(pDPMonitorContext->TargetTiming.PixelClock > MaxClockForCurrentLinkSpeed) + MaxClockForCurrentLinkSpeed = (LinkSpeed / (pDPMonitorContext->bpc * 3)) * LaneNum * 8; + if(pDPMonitorContext->TargetTiming.PixelClock > MaxClockForCurrentLinkSpeed + && pDPMonitorContext->bpc > DP_Default_bpc) { - cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: Current link speed(%d) can't lighten to PixelClock(%d) with %d bit, use default bpc\n", - FUNCTION_NAME, pDPMonitorContext->LinkSpeedToUse, pDPMonitorContext->TargetTiming.PixelClock, - pDPMonitorContext->bpc)); + cbDebugPrint((MAKE_LEVEL(DP, DEBUG), "%s: LinkSpeed(%d) can't support PixelClock(%d) with %d bit, use default bpc\n", + FUNCTION_NAME, LinkSpeed, pDPMonitorContext->TargetTiming.PixelClock, pDPMonitorContext->bpc)); pDPMonitorContext->bpc = DP_Default_bpc; } + + pDPMonitorContext->LinkSpeedToUse = LinkSpeed; + pDPMonitorContext->LaneNumberToUse = LaneNum; } // determine final link training params according to Source's caps @@ -446,8 +425,8 @@ CBIOS_BOOL cbDPMonitor_SetUpMainLink(PCBIOS_VOID pvcbe, PCBIOS_DP_MONITOR_CONTEX } MainLinkParams.pTiming = pTiming; - MainLinkParams.LaneNumberToUse = pDPMonitorContext->LaneNumberToUse; - MainLinkParams.LinkSpeedToUse = pDPMonitorContext->LinkSpeedToUse; + MainLinkParams.LinkedLaneNumber = pDPMonitorContext->LinkPassLaneNum; + MainLinkParams.LinkedSpeed = pDPMonitorContext->LinkPassSpeed; MainLinkParams.bpc = pDPMonitorContext->bpc; MainLinkParams.TUSize = pDPMonitorContext->TUSize; MainLinkParams.AsyncMode = pDPMonitorContext->AsyncMode; @@ -1069,10 +1048,6 @@ static CBIOS_BOOL cbDPMonitor_GetSinkCaps(PCBIOS_EXTENSION_COMMON pcbe, PCBIOS_D } } - //initialize current link speed and lane count to max value - pDPMonitorContext->LinkSpeedToUse = pDPMonitorContext->SinkMaxLinkSpeed; - pDPMonitorContext->LaneNumberToUse = pDPMonitorContext->SinkMaxLaneCount; - pDPMonitorContext->bpc = DP_Default_bpc; pDPMonitorContext->EnhancedMode = 0x01; pDPMonitorContext->AsyncMode = 0x01; @@ -1420,7 +1395,7 @@ CBIOS_VOID cbDPMonitor_OnOff(PCBIOS_VOID pvcbe, PCBIOS_DP_MONITOR_CONTEXT pDPMon } // 2. turn on DP EPHY - cbPHY_DP_DPModeOnOff(pcbe, DPModuleIndex, pDPMonitorContext->LinkSpeedToUse, bOn); + cbPHY_DP_DPModeOnOff(pcbe, DPModuleIndex, pDPMonitorContext->LinkPassSpeed, bOn); // 3. Set Sink device to D0(normal operation mode) state cbDPMonitor_SetSinkPowerState(pcbe, DPModuleIndex, CBIOS_TRUE); @@ -1478,7 +1453,7 @@ CBIOS_VOID cbDPMonitor_OnOff(PCBIOS_VOID pvcbe, PCBIOS_DP_MONITOR_CONTEXT pDPMon cbDPMonitor_SetSinkPowerState(pcbe, DPModuleIndex, CBIOS_FALSE); // 4. turn off DP EPHY - cbPHY_DP_DPModeOnOff(pcbe, DPModuleIndex, pDPMonitorContext->LinkSpeedToUse, bOn); + cbPHY_DP_DPModeOnOff(pcbe, DPModuleIndex, pDPMonitorContext->LinkPassSpeed, bOn); // 5. reset AUX cbDIU_DP_ResetAUX(pcbe, DPModuleIndex); @@ -1995,7 +1970,7 @@ static CBIOS_BOOL cbDPMonitor_ProcLinkStatusCheck(PCBIOS_EXTENSION_COMMON pcbe, // Link maintenance hot IRQ signal, need to check link/sink status field of DPCD. cbDebugPrint((MAKE_LEVEL(DP, DEBUG), "%s: Not a automated test IRQ, Link maitanance IRQ!\n", FUNCTION_NAME)); - ulLaneNum = pDPMonitorContext->LaneNumberToUse; + ulLaneNum = pDPMonitorContext->LinkPassLaneNum; AUX.Function = CBIOS_AUX_REQUEST_NATIVE_READ; AUX.Offset = 0x202; diff --git a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.h b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.h index a1fa4687a6ee0..165240cbd045c 100644 --- a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.h +++ b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosDPMonitor.h @@ -106,6 +106,8 @@ typedef struct _CBIOS_DP_MONITOR_CONTEXT { CBIOS_U32 LaneNumberToUse; // 1 ~ 4 lanes CBIOS_U32 LinkSpeedToUse; // 1.62Gbps, 2.7 Gbps or 5.4 Gbps + CBIOS_U32 LinkPassLaneNum; + CBIOS_U32 LinkPassSpeed; CBIOS_U32 bpc; // bit per channel CBIOS_U32 TUSize; // 32 ~ 64, default to 48 CBIOS_BOOL EnhancedMode; // 1 (yes) to support HDCP diff --git a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosEDPPanel.c b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosEDPPanel.c index 2e125397255ad..f2a90a353ecf6 100644 --- a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosEDPPanel.c +++ b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosEDPPanel.c @@ -36,7 +36,7 @@ static PCBIOS_EDP_PANEL_DESC EDPPanelDescTbl[] = static CBIOS_BOOL cbEDPPanel_GetMonitorID(CBIOS_U8 *pEDID, CBIOS_U8 *pMnitorID) { - CBIOS_U8 index[32] = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ[/]^_"; + CBIOS_U8 *index = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ[/]^_"; CBIOS_U8 ProductID[3] = {0}; CBIOS_BOOL bRet = CBIOS_FALSE; CBIOS_U8 *pMonitorIDinEDID = pEDID + 0x08; diff --git a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosHDMIMonitor.c b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosHDMIMonitor.c index f92781c8bd0d8..29ae6b64f4a6d 100644 --- a/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosHDMIMonitor.c +++ b/drivers/gpu/drm/arise/cbios/Device/Monitor/CBiosHDMIMonitor.c @@ -1110,7 +1110,7 @@ CBIOS_BOOL cbHDMIMonitor_SCDC_Handler(CBIOS_VOID* pvcbe, PCBIOS_DEVICE_COMMON pD CBIOS_SCDC_UPDATE_FLAGS UpdateFlags; CBIOS_BOOL bRet = CBIOS_FALSE; - if(pDevCommon->EdidStruct.Attribute.HFVSDBData.IsSCDCPresent) + if(pDevCommon->EdidStruct.Attribute.HFSCDSData.IsSCDCPresent) { cb_memset(&UpdateFlags, 0, sizeof(UpdateFlags)); bRet = cbHDMIMonitor_SCDC_ReadUpdateFlags(pcbe, pDevCommon, &UpdateFlags); @@ -1287,6 +1287,7 @@ CBIOS_BOOL cbHDMIMonitor_Detect(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT p #else cb_memcpy(pDevCommon->EdidData, FPGAHDMIEdid, sizeof(FPGAHDMIEdid)); #endif + pDevCommon->TotalBlockNum = cbEDIDModule_GetExtBlockNum(pDevCommon->EdidData) + 1; IsDevChanged = CBIOS_TRUE; bConnected = CBIOS_TRUE; } @@ -1326,7 +1327,7 @@ CBIOS_BOOL cbHDMIMonitor_Detect(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT p } cbDIU_HDMI_ConfigScrambling(pcbe, HDMIModuleIndex, pHDMIMonitorContext->ScramblingEnable); - if(pDevCommon->EdidStruct.Attribute.HFVSDBData.IsSCDCPresent) + if(pDevCommon->EdidStruct.Attribute.HFSCDSData.IsSCDCPresent) { SCDCStatusFlags.ScramblerStatus = 0; if(cbHDMIMonitor_SCDC_ReadData(pcbe, pDevCommon, &(SCDCStatusFlags.ScramblerStatus), 0x21, 0x1)) @@ -1483,7 +1484,7 @@ CBIOS_VOID cbHDMIMonitor_OnOff(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT pH CBIOS_MODULE_INDEX IGAIndex = cbGetModuleIndex(pcbe, pDevCommon->DeviceType, CBIOS_MODULE_TYPE_IGA); PCBIOS_DISP_MODE_PARAMS pModeParams = CBIOS_NULL; CBIOS_BOOL bHDMIDevice = pDevCommon->EdidStruct.Attribute.IsCEA861HDMI; - CBIOS_BOOL bSCDCPresent = pDevCommon->EdidStruct.Attribute.HFVSDBData.IsSCDCPresent; + CBIOS_BOOL bSCDCPresent = pDevCommon->EdidStruct.Attribute.HFSCDSData.IsSCDCPresent; PCBIOS_CEA_EXTENED_BLOCK pCEAExtData = &pDevCommon->EdidStruct.Attribute.ExtDataBlock[VIDEO_CAPABILITY_DATA_BLOCK_TAG]; CBIOS_BOOL bQS = pCEAExtData->VideoCapabilityData.bRGBQuantRange; CBIOS_CSC_ADJUST_PARA CSCAdjustPara = {0}; @@ -1571,9 +1572,6 @@ CBIOS_VOID cbHDMIMonitor_OnOff(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT pH } else { - //Wait vblank before turning off device to avoid flashing white lines - cbWaitVBlank(pcbe, IGAIndex); - cbDIU_HDMI_DisableVideoAudio(pcbe, HDMIModuleIndex); if(pcbe->ChipCaps.bSupportScrambling) @@ -1585,9 +1583,7 @@ CBIOS_VOID cbHDMIMonitor_OnOff(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT pH { cbDIU_HDMI_EnableReadRequest(pcbe, HDMIModuleIndex, CBIOS_FALSE); } - } - } CBIOS_VOID cbHDMIMonitor_QueryAttribute(PCBIOS_VOID pvcbe, PCBIOS_HDMI_MONITOR_CONTEXT pHDMIMonitorContext, PCBiosMonitorAttribute pMonitorAttribute) diff --git a/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDP.c b/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDP.c index d742a35f8e386..483a6b20bea6f 100644 --- a/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDP.c +++ b/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDP.c @@ -200,26 +200,29 @@ static CBIOS_BOOL cbDPPort_DeviceDetect(PCBIOS_EXTENSION_COMMON pcbe, PCBIOS_DEV CBIOS_MODULE_INDEX HDMIModuleIndex = CBIOS_MODULE_INDEX_INVALID; DP_EPHY_MODE Mode; - cbTraceEnter(DP); - if ((pDevCommon == CBIOS_NULL) || (!(pDevCommon->DeviceType & ALL_DP_TYPES))) { cbDebugPrint((MAKE_LEVEL(DP, ERROR), "%s: the 2nd param is invalid!\n", FUNCTION_NAME)); - bConnected = CBIOS_FALSE; - goto EXIT; + return CBIOS_FALSE; } DPModuleIndex = cbGetModuleIndex(pcbe, pDevCommon->DeviceType, CBIOS_MODULE_TYPE_DP); HDMIModuleIndex = cbGetModuleIndex(pcbe, pDevCommon->DeviceType, CBIOS_MODULE_TYPE_HDMI); + if(CBIOS_MODULE_INDEX_INVALID == DPModuleIndex) + { + cbDebugPrint((MAKE_LEVEL(DP, ERROR), "Invalid DP index in detect device 0x%x!\n", pDevCommon->DeviceType)); + return CBIOS_FALSE; + } + Mode = cbPHY_DP_GetEphyMode(pcbe, DPModuleIndex); pDpContext->DPPortParams.bDualMode = cbDualModeDetect(pcbe, pDevCommon); //Some monitors(like samsung UA40) can't get EDID by I2C after change brightness through DDX, and bDualMode is FALSE //So it has no chance to enter cbHDMIMonitor_Detect function to handle scramble, just clear it here when found bDualMode is FALSE - if (!pDpContext->DPPortParams.bDualMode) + if (!pDpContext->DPPortParams.bDualMode && CBIOS_MODULE_INDEX_INVALID != HDMIModuleIndex) { pDpContext->HDMIMonitorContext.ScramblingEnable = CBIOS_FALSE; - cbDIU_HDMI_ConfigScrambling(pcbe, HDMIModuleIndex, pDpContext->HDMIMonitorContext.ScramblingEnable); + cbDIU_HDMI_ConfigScrambling(pcbe, HDMIModuleIndex, CBIOS_FALSE); } if ((!bConnected) && (pDpContext->DPPortParams.bDualMode) @@ -267,8 +270,6 @@ static CBIOS_BOOL cbDPPort_DeviceDetect(PCBIOS_EXTENSION_COMMON pcbe, PCBIOS_DEV FUNCTION_NAME, pDevCommon->DeviceType)); } -EXIT: - cbTraceExit(DP); return bConnected; } @@ -286,6 +287,12 @@ static CBIOS_VOID cbDPPort_OnOff(PCBIOS_EXTENSION_COMMON pcbe, PCBIOS_DEVICE_COM } DPModuleIndex = cbGetModuleIndex(pcbe, pDevCommon->DeviceType, CBIOS_MODULE_TYPE_DP); + if(CBIOS_MODULE_INDEX_INVALID == DPModuleIndex) + { + cbDebugPrint((MAKE_LEVEL(DP, ERROR), "Invalid DP index in onoff device 0x%x!\n", pDevCommon->DeviceType)); + return; + } + bDPMode = (pDpContext->DPPortParams.DPEphyMode == DP_EPHY_DP_MODE) ? CBIOS_TRUE : CBIOS_FALSE; pSource = &(pDevCommon->DispSource); @@ -341,6 +348,8 @@ static CBIOS_VOID cbDPPort_OnOff(PCBIOS_EXTENSION_COMMON pcbe, PCBIOS_DEVICE_COM { if ((pDpContext->Common.CurrentMonitorType == CBIOS_MONITOR_TYPE_HDMI) || (pDpContext->Common.CurrentMonitorType == CBIOS_MONITOR_TYPE_DVI)) { + //Wait vblank before turning off device to avoid flashing white garbage + cbWaitNonFullVBlank(pcbe, DPModuleIndex); cbHDMIMonitor_OnOff(pcbe, &pDpContext->HDMIMonitorContext, bOn); cbPHY_DP_DualModeOnOff(pcbe, DPModuleIndex, pDpContext->HDMIMonitorContext.HDMIClock, bOn); } diff --git a/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDSI.c b/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDSI.c index 7346b61b454fd..785a1d35609f0 100644 --- a/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDSI.c +++ b/drivers/gpu/drm/arise/cbios/Device/Port/CBiosDSI.c @@ -2723,7 +2723,7 @@ static CBIOS_STATUS cbDSI_GetHostUpdatePara(PCBIOS_VOID pvcbe, PCBIOS_DSI_HOSTUP if((pUpdateParams->UpdateWindow.XStart + pUpdateParams->UpdateWindow.WinWidth) < (pTargetTiming->XRes / 2)) { pUpdateWin = &(pHostUpdateParams->HostUpdateWindow[DSI_INDEX0]); - cbmemcpy(pUpdateWin, &(pUpdateParams->UpdateWindow), sizeof(CBIOS_DSI_WINDOW)); + cb_memcpy(pUpdateWin, &(pUpdateParams->UpdateWindow), sizeof(CBIOS_DSI_WINDOW)); cbDSI_AdjustPanelUpdateWindow(pcbe, &(pHostUpdateParams->PanelUpdatePara), pUpdateWin); } else if (pUpdateParams->UpdateWindow.XStart >= (pTargetTiming->XRes / 2)) //only in right part @@ -2801,7 +2801,7 @@ static CBIOS_STATUS cbDSI_GetDMAUpdatePara(PCBIOS_VOID pvcbe, PCBIOS_DSI_DMAUPDA pDMAUpdateParams->DMABaseAddr = pUpdateParams->DSIUpdateConfig.DMABaseAddr; pDMAUpdateParams->DMAStride = pUpdateParams->DSIUpdateConfig.DMAStride; pDMAUpdateParams->isDMAAligned = pUpdateParams->DSIUpdateConfig.bDMAAligned; - cbmemcpy(&(pDMAUpdateParams->DMAUpdateWindow), &(pUpdateParams->UpdateWindow), sizeof(CBIOS_DSI_WINDOW)); + cb_memcpy(&(pDMAUpdateParams->DMAUpdateWindow), &(pUpdateParams->UpdateWindow), sizeof(CBIOS_DSI_WINDOW)); } else { diff --git a/drivers/gpu/drm/arise/cbios/Device/gcc_stdarg.h b/drivers/gpu/drm/arise/cbios/Device/gcc_stdarg.h index 2d2ee9cac8ac7..39153e2d87f53 100644 --- a/drivers/gpu/drm/arise/cbios/Device/gcc_stdarg.h +++ b/drivers/gpu/drm/arise/cbios/Device/gcc_stdarg.h @@ -1,26 +1,29 @@ +//***************************************************************************** +// Copyright (c) 2021 Glenfly Tech Co., Ltd.. +// All Rights Reserved. +// +// This is UNPUBLISHED PROPRIETARY SOURCE CODE of Glenfly Tech Co., Ltd..; +// the contents of this file may not be disclosed to third parties, copied or +// duplicated in any form, in whole or in part, without the prior written +// permission of Glenfly Tech Co., Ltd.. +// +// The copyright of the source code is protected by the copyright laws of the People's +// Republic of China and the related laws promulgated by the People's Republic of China +// and the international covenant(s) ratified by the People's Republic of China. +//***************************************************************************** + + +/* As a special exception, if you include this header file into source + files compiled by GCC, this header file does not by itself cause + the resulting executable to be covered by the GNU General Public + License. This exception does not however invalidate any other + reasons why the executable file might be covered by the GNU General + Public License. */ + /* - * Copyright © 2021 Glenfly Tech Co., Ltd. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * + * ISO C Standard: 7.15 Variable arguments */ + #ifndef _STDARG_H #ifndef _ANSI_STDARG_H_ #ifndef __need___va_list @@ -29,6 +32,8 @@ #endif /* not __need___va_list */ #undef __need___va_list +/* Define __gnuc_va_list. */ + #ifndef __GNUC_VA_LIST #define __GNUC_VA_LIST typedef __builtin_va_list __gnuc_va_list; @@ -46,6 +51,13 @@ typedef __builtin_va_list __gnuc_va_list; #endif #define __va_copy(d,s) __builtin_va_copy(d,s) +/* Define va_list, if desired, from __gnuc_va_list. */ +/* We deliberately do not define va_list when called from + stdio.h, because ANSI C says that stdio.h is not supposed to define + va_list. stdio.h needs to have access to that data type, + but must not use that name. It should use the name __gnuc_va_list, + which is safe because it is reserved for the implementation. */ + #ifdef _HIDDEN_VA_LIST /* On OSF1, this means varargs.h is "half-loaded". */ #undef _VA_LIST #endif @@ -55,7 +67,10 @@ typedef __builtin_va_list __gnuc_va_list; #endif #if defined(__svr4__) || (defined(_SCO_DS) && !defined(__VA_LIST)) - +/* SVR4.2 uses _VA_LIST for an internal alias for va_list, + so we must avoid testing it and setting it here. + SVR4 uses _VA_LIST as a flag in stdarg.h, but we should + have no conflict with that. */ #ifndef _VA_LIST_ #define _VA_LIST_ #ifdef __i860__ @@ -70,6 +85,10 @@ typedef __gnuc_va_list va_list; #endif /* _VA_LIST_ */ #else /* not __svr4__ || _SCO_DS */ +/* The macro _VA_LIST_ is the same thing used by this file in Ultrix. + But on BSD NET2 we must not test or define or undef it. + (Note that the comments in NET 2's ansi.h + are incorrect for _VA_LIST_--see stdio.h!) */ #if !defined (_VA_LIST_) || defined (__BSD_NET2__) || defined (____386BSD____) || defined (__bsdi__) || defined (__sequent__) || defined (__FreeBSD__) || defined(WINNT) /* The macro _VA_LIST_DEFINED is used in Windows NT 3.5 */ #ifndef _VA_LIST_DEFINED diff --git a/drivers/gpu/drm/arise/cbios/Display/CBiosMode.c b/drivers/gpu/drm/arise/cbios/Display/CBiosMode.c index f1531277ee244..027fdcbcc2453 100644 --- a/drivers/gpu/drm/arise/cbios/Display/CBiosMode.c +++ b/drivers/gpu/drm/arise/cbios/Display/CBiosMode.c @@ -6081,7 +6081,7 @@ CBIOS_U32 cbMode_GetDeviceModeList(PCBIOS_VOID pvcbe, { cbDebugPrint((MAKE_LEVEL(GENERIC, DEBUG),"cbMode_GetDeviceModeList: Filter mode %d x %d @ %d as it is greater than config max mode.\n", MaxMode.XResolution, MaxMode.YResolution, MaxMode.Refreshrate)); - bFilterThisMode = CBIOS_TRUE; + bFilterThisMode = CBIOS_TRUE; } } } diff --git a/drivers/gpu/drm/arise/cbios/Display/CBiosPathManager.c b/drivers/gpu/drm/arise/cbios/Display/CBiosPathManager.c index e7806274f7127..0e1ae08b54fe4 100644 --- a/drivers/gpu/drm/arise/cbios/Display/CBiosPathManager.c +++ b/drivers/gpu/drm/arise/cbios/Display/CBiosPathManager.c @@ -26,6 +26,7 @@ #include "CBiosChipShare.h" #include "../Hw/HwBlock/CBiosDIU_HDCP.h" #include "../Hw/HwBlock/CBiosDIU_HDTV.h" +#include "../Hw/HwBlock/CBiosDIU_DP.h" #include "../Hw/HwBlock/CBiosDIU_HDMI.h" @@ -356,12 +357,20 @@ CBIOS_MODULE_INDEX cbGetModuleIndex(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE Device, { case CBIOS_MODULE_TYPE_DP: ModuleIndex = pSource->ModuleList.DPModule.Index; + if(ModuleIndex >= DP_MODU_NUM) + { + ModuleIndex = CBIOS_MODULE_INDEX_INVALID; + } break; case CBIOS_MODULE_TYPE_MHL: ModuleIndex = pSource->ModuleList.MHLModule.Index; break; case CBIOS_MODULE_TYPE_HDMI: ModuleIndex = pSource->ModuleList.HDMIModule.Index; + if(ModuleIndex >= HDMI_MODU_NUM) + { + ModuleIndex = CBIOS_MODULE_INDEX_INVALID; + } break; case CBIOS_MODULE_TYPE_HDTV: ModuleIndex = pSource->ModuleList.HDTVModule.Index; @@ -374,6 +383,10 @@ CBIOS_MODULE_INDEX cbGetModuleIndex(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE Device, break; case CBIOS_MODULE_TYPE_IGA: ModuleIndex = pSource->ModuleList.IGAModule.Index; + if((CBIOS_U32)ModuleIndex >= pcbe->DispMgr.IgaCount) + { + ModuleIndex = CBIOS_MODULE_INDEX_INVALID; + } break; default: cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: invalid module type: %d!\n", FUNCTION_NAME, ModuleType)); @@ -382,7 +395,7 @@ CBIOS_MODULE_INDEX cbGetModuleIndex(PCBIOS_VOID pvcbe, CBIOS_ACTIVE_TYPE Device, if (ModuleIndex == CBIOS_MODULE_INDEX_INVALID) { - cbDebugPrint((MAKE_LEVEL(GENERIC, WARNING), "%s: invalid module index of module: %d!\n", FUNCTION_NAME, ModuleType)); + cbDebugPrint((MAKE_LEVEL(GENERIC, INFO), "%s: Invalid module %d for device 0x%x!\n", FUNCTION_NAME, ModuleType, Device)); } return ModuleIndex; diff --git a/drivers/gpu/drm/arise/cbios/Hw/Arise/CBiosVCP_Arise.c b/drivers/gpu/drm/arise/cbios/Hw/Arise/CBiosVCP_Arise.c index 5cd74af11e672..9a08b1f882575 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/Arise/CBiosVCP_Arise.c +++ b/drivers/gpu/drm/arise/cbios/Hw/Arise/CBiosVCP_Arise.c @@ -253,7 +253,7 @@ CBIOS_U32 cbGetRomRegTbl(PCBIOS_VOID VCPBase, CBIOS_U16 TblOffset, CBREGISTER** pReg = *pRegTable = cb_AllocateNonpagedPool(RegCounter * sizeof(CBREGISTER)); if(pReg == CBIOS_NULL) { - cbDebugPrint((1,"pRegTable allocate error!\n")); + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR),"pRegTable allocate error!\n")); return 0; } diff --git a/drivers/gpu/drm/arise/cbios/Hw/Arise/CBios_Arise.c b/drivers/gpu/drm/arise/cbios/Hw/Arise/CBios_Arise.c index c3acdff60610b..8b789235ad7b1 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/Arise/CBios_Arise.c +++ b/drivers/gpu/drm/arise/cbios/Hw/Arise/CBios_Arise.c @@ -1421,13 +1421,13 @@ CBIOS_STATUS cbCheckSurfaceOnDisplay_Arise(PCBIOS_EXTENSION_COMMON pcbe, PCBIOS_ { if(pChkSurfacePara->pSrcWindow) { - cbDebugPrint((MAKE_LEVEL_EX(BACK,GENERIC,DEBUG), "Check %d: Addr=%x,Pitch=%d,FixedAddr=%x, OnDisp=%d.\n\n", + cbDebugPrint((MAKE_LEVEL(GENERIC,DEBUG), "Check %d: Addr=%x,Pitch=%d,FixedAddr=%x, OnDisp=%d.\n\n", StreamType, pChkSurfacePara->pSurfaceAttr->StartAddr, pChkSurfacePara->pSurfaceAttr->Pitch, PhyAddr, bOnDisplay)); } else { - cbDebugPrint((MAKE_LEVEL_EX(BACK,GENERIC,DEBUG), "Check %d(disable): Addr=%x, OnDisp=%d.\n\n", StreamType, + cbDebugPrint((MAKE_LEVEL(GENERIC,DEBUG), "Check %d(disable): Addr=%x, OnDisp=%d.\n\n", StreamType, pChkSurfacePara->pSurfaceAttr->StartAddr, bOnDisplay)); } } @@ -2973,17 +2973,17 @@ CBIOS_STATUS cbCECEnableDisable_Arise(PCBIOS_VOID pvcbe, PCBIOS_CEC_ENABLE_DISAB if (pCECEnableDisablePara == CBIOS_NULL) { Status = CBIOS_ER_NULLPOINTER; - cbDebugPrint((DBG_LEVEL_ERROR_MSG, "CBiosCECEnableDisable_E3K: pCECEnableDisablePara is NULL!")); + cbDebugPrint((MAKE_LEVEL(HDMI, ERROR), "CBiosCECEnableDisable_E3K: pCECEnableDisablePara is NULL!")); } else if (!pcbe->ChipCaps.IsSupportCEC) { Status = CBIOS_ER_HARDWARE_LIMITATION; - cbDebugPrint((DBG_LEVEL_ERROR_MSG, "CBiosCECEnableDisable_E3K: Can't support CEC!")); + cbDebugPrint((MAKE_LEVEL(HDMI, ERROR), "CBiosCECEnableDisable_E3K: Can't support CEC!")); } else if (pCECEnableDisablePara->CECIndex >= CBIOS_CEC_INDEX_COUNT) { Status = CBIOS_ER_INVALID_PARAMETER; - cbDebugPrint((DBG_LEVEL_ERROR_MSG, "CBiosCECEnableDisable_E3K: invalid CEC index!")); + cbDebugPrint((MAKE_LEVEL(HDMI, ERROR), "CBiosCECEnableDisable_E3K: invalid CEC index!")); } else { diff --git a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.c b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.c index b69798416f745..e5aa129b658f3 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.c +++ b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.c @@ -297,11 +297,11 @@ CBIOS_VOID cbDIU_DP_SetHVSync(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleInde CBIOS_VOID cbDIU_DP_SetMaudNaud(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIndex, CBIOS_U32 LinkSpeed, CBIOS_U32 StreamFormat) { - CBIOS_U64 Naud = 0; + CBIOS_U64 Naud = 0, Maud = 0; PCBIOS_EXTENSION_COMMON pcbe = (PCBIOS_EXTENSION_COMMON)pvcbe; REG_MM8240 DPEnableRegValue, DPEnableRegMask; REG_MM8338 DPMuteRegValue, DPMuteRegMask; - //REG_MM833C DPMaudRegValue, DPMaudRegMask; + REG_MM833C DPMaudRegValue, DPMaudRegMask; REG_MM8218 DPCodecSelRegValue, DPCodecSelRegMask; if(DPModuleIndex >= DP_MODU_NUM) @@ -338,7 +338,7 @@ CBIOS_VOID cbDIU_DP_SetMaudNaud(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIn // 2. Calculate Naud Maud Naud = 0x8000; // set Naud = 32768 -#if 0 // it is SW MAUD +#if 1 //DP SW MAUD Maud = cb_do_div((Naud * 512 * StreamFormat), (LinkSpeed * 100)); DPMaudRegValue.Value = 0; @@ -349,8 +349,13 @@ CBIOS_VOID cbDIU_DP_SetMaudNaud(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIn #endif DPMuteRegValue.Value = 0; DPMuteRegValue.NAUD = (CBIOS_U32)Naud; +#if 1 //DP SW MAUD + DPMuteRegValue.Generate_MAUD = 0; // use SW MAUD + DPMuteRegValue.Generated_MAUD_Mode = 0; // use HW MAUD mode 0 +#else DPMuteRegValue.Generate_MAUD = 1; // use HW MAUD DPMuteRegValue.Generated_MAUD_Mode = 1; // use HW MAUD +#endif DPMuteRegMask.Value = 0xFFFFFFFF; DPMuteRegMask.NAUD = 0; DPMuteRegMask.Generate_MAUD = 0; @@ -634,10 +639,12 @@ CBIOS_BOOL cbDIU_DP_LinkTrainingHw(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModul REG_MM8338 DPMuteRegValue, DPMuteRegMask; REG_MM8368 DPSwingRegValue, DPSwingRegMask; REG_MM334C8 DPLinkCtrlRegValue, DPLinkCtrlRegMask; + REG_MM334E0 DPEphySetting1RegValue, DPEphySetting1RegMask; DPCD_REG_00100 DPCD_00100; DPCD_REG_00101 DPCD_00101; DPCD_REG_0010A DPCD_0010A; DPCD_REG_00102 DPCD_00102; + CBIOS_BOOL bACE = ((pcbe->ChipID == CHIPID_ARISE2030) || (pcbe->ChipID == CHIPID_ARISE2020)) ? CBIOS_TRUE : CBIOS_FALSE; //For DP test 4.3.1.4, if use SW to try 1.62 when 2.7 fail, the ulMaxRetryCount should set to 1. CBIOS_U32 ulRetryCount = 0, ulMaxRetryCount = 3; @@ -913,140 +920,266 @@ CBIOS_BOOL cbDIU_DP_LinkTrainingHw(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModul if (BitRate == CBIOS_DP_LINK_SPEED_5400Mbps) { - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 1; - DPSwingRegValue.DP1_SW_swing = 0x09; - DPSwingRegValue.DP1_SW_pp = 0; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 5; - DPSwingRegValue.DP1_SW_swing = 0x10; - DPSwingRegValue.DP1_SW_pp = 0; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 9; - DPSwingRegValue.DP1_SW_swing = 0x17; - DPSwingRegValue.DP1_SW_pp = 0x1C; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x11; - DPSwingRegValue.DP1_SW_swing = 0x11; - DPSwingRegValue.DP1_SW_pp = 0; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x15; - DPSwingRegValue.DP1_SW_swing = 0x19; - DPSwingRegValue.DP1_SW_pp = 0x08; - DPSwingRegValue.DP1_SW_post_cursor = 0; - DPSwingRegMask.Value = 0xFFFFFFFF; DPSwingRegMask.enable_SW_swing_pp = 0; DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; DPSwingRegMask.DP1_SW_swing = 0; DPSwingRegMask.DP1_SW_pp = 0; DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x19; - DPSwingRegValue.DP1_SW_swing = 0x33; - DPSwingRegValue.DP1_SW_pp = 0x1A; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x1D; - DPSwingRegValue.DP1_SW_swing = 0x1C; - DPSwingRegValue.DP1_SW_pp = 0; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x21; - DPSwingRegValue.DP1_SW_swing = 0x14; - DPSwingRegValue.DP1_SW_pp = 0; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x25; - DPSwingRegValue.DP1_SW_swing = 0x3F; - DPSwingRegValue.DP1_SW_pp = 0; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + if (bACE) + { + DPEphyCtrlRegMask.Value = 0xFF000FFF; + DPEphySetting1RegMask.Value = 0xFFFFFFFF; + DPEphySetting1RegMask.EPHY1_SR_SPD = 0; + DPEphySetting1RegMask.EPHY1_SR_DLY = 0; + DPEphySetting1RegMask.EPHY1_SR_NDLY = 0; + + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 1; + DPSwingRegValue.DP1_SW_swing = 0x09; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 5; + DPSwingRegValue.DP1_SW_swing = 0x18; + DPSwingRegValue.DP1_SW_pp = 0x9; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 3; + DPEphyCtrlRegValue.DIAJ_L1 = 3; + DPEphyCtrlRegValue.DIAJ_L2 = 3; + DPEphyCtrlRegValue.DIAJ_L3 = 3; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 9; + DPSwingRegValue.DP1_SW_swing = 0x30; + DPSwingRegValue.DP1_SW_pp = 0x1F; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x11; + DPSwingRegValue.DP1_SW_swing = 0x10; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 2; + DPEphyCtrlRegValue.DIAJ_L1 = 2; + DPEphyCtrlRegValue.DIAJ_L2 = 2; + DPEphyCtrlRegValue.DIAJ_L3 = 2; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x15; + DPSwingRegValue.DP1_SW_swing = 0x3C; + DPSwingRegValue.DP1_SW_pp = 0x1B; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 1; + DPEphySetting1RegValue.EPHY1_SR_DLY = 1; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x19; + DPSwingRegValue.DP1_SW_swing = 0x30; + DPSwingRegValue.DP1_SW_pp = 0x12; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x1D; + DPSwingRegValue.DP1_SW_swing = 0x19; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 1; + DPEphySetting1RegValue.EPHY1_SR_DLY = 1; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x21; + DPSwingRegValue.DP1_SW_swing = 0x1C; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPEphyCtrlRegValue.Value = 0; + DPEphyCtrlRegValue.DIAJ_L0 = 1; + DPEphyCtrlRegValue.DIAJ_L1 = 1; + DPEphyCtrlRegValue.DIAJ_L2 = 1; + DPEphyCtrlRegValue.DIAJ_L3 = 1; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_CTRL[DPModuleIndex], DPEphyCtrlRegValue.Value, DPEphyCtrlRegMask.Value); + DPEphySetting1RegValue.Value = 0; + DPEphySetting1RegValue.EPHY1_SR_SPD = 0; + DPEphySetting1RegValue.EPHY1_SR_DLY = 0; + DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_SETTING1[DPModuleIndex], DPEphySetting1RegValue.Value, DPEphySetting1RegMask.Value); + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x25; + DPSwingRegValue.DP1_SW_swing = 0x3F; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + } + else + { + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 1; + DPSwingRegValue.DP1_SW_swing = 0x09; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 5; + DPSwingRegValue.DP1_SW_swing = 0x10; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 9; + DPSwingRegValue.DP1_SW_swing = 0x17; + DPSwingRegValue.DP1_SW_pp = 0x1C; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x11; + DPSwingRegValue.DP1_SW_swing = 0x11; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x15; + DPSwingRegValue.DP1_SW_swing = 0x19; + DPSwingRegValue.DP1_SW_pp = 0x08; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x19; + DPSwingRegValue.DP1_SW_swing = 0x33; + DPSwingRegValue.DP1_SW_pp = 0x1A; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x1D; + DPSwingRegValue.DP1_SW_swing = 0x1C; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x21; + DPSwingRegValue.DP1_SW_swing = 0x14; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x25; + DPSwingRegValue.DP1_SW_swing = 0x3F; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + } } else { @@ -1158,8 +1291,8 @@ CBIOS_BOOL cbDIU_DP_LinkTrainingHw(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModul DPSwingRegValue.Value = 0; DPSwingRegValue.enable_SW_swing_pp = 1; DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 0x21; - DPSwingRegValue.DP1_SW_swing = 0x39; - DPSwingRegValue.DP1_SW_pp = 0xA; + DPSwingRegValue.DP1_SW_swing = bACE ? 0x3C : 0x39; + DPSwingRegValue.DP1_SW_pp = bACE ? 0x7 : 0xA; DPSwingRegValue.DP1_SW_post_cursor = 0; DPSwingRegMask.Value = 0xFFFFFFFF; @@ -1402,29 +1535,29 @@ CBIOS_BOOL cbDIU_DP_SetUpMainLink(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPCtrlRegValue.Value = cb_ReadU32(pcbe->pAdapterContext, DP_REG_CTRL[DPModuleIndex]); if (DPCtrlRegValue.LINK_bit_rate_status_1_0 == 0) { - if (pMainLinkParams->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_1620Mbps) + if (pMainLinkParams->LinkedSpeed != CBIOS_DP_LINK_SPEED_1620Mbps) { cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: why current link speed:%d is not sync with REG:0x%x?\n", - FUNCTION_NAME, pMainLinkParams->LinkSpeedToUse, DP_REG_CTRL[DPModuleIndex])); - pMainLinkParams->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_1620Mbps; + FUNCTION_NAME, pMainLinkParams->LinkedSpeed, DP_REG_CTRL[DPModuleIndex])); + pMainLinkParams->LinkedSpeed = CBIOS_DP_LINK_SPEED_1620Mbps; } } else if (DPCtrlRegValue.LINK_bit_rate_status_1_0 == 1) { - if (pMainLinkParams->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_2700Mbps) + if (pMainLinkParams->LinkedSpeed != CBIOS_DP_LINK_SPEED_2700Mbps) { cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: why current link speed:%d is not sync with REG:0x%x?\n", - FUNCTION_NAME, pMainLinkParams->LinkSpeedToUse, DP_REG_CTRL[DPModuleIndex])); - pMainLinkParams->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_2700Mbps; + FUNCTION_NAME, pMainLinkParams->LinkedSpeed, DP_REG_CTRL[DPModuleIndex])); + pMainLinkParams->LinkedSpeed = CBIOS_DP_LINK_SPEED_2700Mbps; } } else { - if (pMainLinkParams->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_5400Mbps) + if (pMainLinkParams->LinkedSpeed != CBIOS_DP_LINK_SPEED_5400Mbps) { cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: why current link speed:%d is not sync with REG:0x%x?\n", - FUNCTION_NAME, pMainLinkParams->LinkSpeedToUse, DP_REG_CTRL[DPModuleIndex])); - pMainLinkParams->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_5400Mbps; + FUNCTION_NAME, pMainLinkParams->LinkedSpeed, DP_REG_CTRL[DPModuleIndex])); + pMainLinkParams->LinkedSpeed = CBIOS_DP_LINK_SPEED_5400Mbps; } } #endif @@ -1439,27 +1572,27 @@ CBIOS_BOOL cbDIU_DP_SetUpMainLink(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule switch(DPCD_0100.LINK_BW_SET) { case CBIOS_DPCD_LINK_RATE_1620Mbps: - if (pMainLinkParams->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_1620Mbps) + if (pMainLinkParams->LinkedSpeed != CBIOS_DP_LINK_SPEED_1620Mbps) { cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: why current link speed:%d is not sync with DPCD100?\n", - FUNCTION_NAME, pMainLinkParams->LinkSpeedToUse)); - pMainLinkParams->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_1620Mbps; + FUNCTION_NAME, pMainLinkParams->LinkedSpeed)); + pMainLinkParams->LinkedSpeed = CBIOS_DP_LINK_SPEED_1620Mbps; } break; case CBIOS_DPCD_LINK_RATE_2700Mbps: - if (pMainLinkParams->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_2700Mbps) + if (pMainLinkParams->LinkedSpeed != CBIOS_DP_LINK_SPEED_2700Mbps) { cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: why current link speed:%d is not sync with DPCD100?\n", - FUNCTION_NAME, pMainLinkParams->LinkSpeedToUse)); - pMainLinkParams->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_2700Mbps; + FUNCTION_NAME, pMainLinkParams->LinkedSpeed)); + pMainLinkParams->LinkedSpeed = CBIOS_DP_LINK_SPEED_2700Mbps; } break; case CBIOS_DPCD_LINK_RATE_5400Mbps: - if (pMainLinkParams->LinkSpeedToUse != CBIOS_DP_LINK_SPEED_5400Mbps) + if (pMainLinkParams->LinkedSpeed != CBIOS_DP_LINK_SPEED_5400Mbps) { cbDebugPrint((MAKE_LEVEL(DP, WARNING), "%s: why current link speed:%d is not sync with DPCD100?\n", - FUNCTION_NAME, pMainLinkParams->LinkSpeedToUse)); - pMainLinkParams->LinkSpeedToUse = CBIOS_DP_LINK_SPEED_5400Mbps; + FUNCTION_NAME, pMainLinkParams->LinkedSpeed)); + pMainLinkParams->LinkedSpeed = CBIOS_DP_LINK_SPEED_5400Mbps; } break; } @@ -1480,7 +1613,7 @@ CBIOS_BOOL cbDIU_DP_SetUpMainLink(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule ulTemp1 = pTiming->PixelClock*3*pMainLinkParams->bpc; } - ulTemp2 = pMainLinkParams->LaneNumberToUse * pMainLinkParams->LinkSpeedToUse * 8; + ulTemp2 = pMainLinkParams->LinkedLaneNumber * pMainLinkParams->LinkedSpeed * 8; if (ulTemp2 == 0) // Prevent being divided by zero { @@ -1491,20 +1624,20 @@ CBIOS_BOOL cbDIU_DP_SetUpMainLink(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule ulTURatio = cb_do_div((ulTemp1<<15), ulTemp2); DPHWidthTURegValue.Value = 0; - if (pMainLinkParams->LaneNumberToUse == 0) // Prevent being divided by zero + if (pMainLinkParams->LinkedLaneNumber == 0) // Prevent being divided by zero { cbDebugPrint((MAKE_LEVEL(DP, ERROR), "%s: fata error -- LaneNumber is ZERO!!!\n", FUNCTION_NAME)); bStatus = CBIOS_FALSE; goto Exit; } - DPHWidthTURegValue.Horiz_Width = pTiming->HorDisEnd / pMainLinkParams->LaneNumberToUse - 1; + DPHWidthTURegValue.Horiz_Width = pTiming->HorDisEnd / pMainLinkParams->LinkedLaneNumber - 1; DPHWidthTURegValue.TU_Size = (pMainLinkParams->TUSize - 1); DPHWidthTURegValue.TU_Ratio = (CBIOS_U32)ulTURatio; DPHWidthTURegMask.Value = 0; cbMMIOWriteReg32(pcbe, DP_REG_HWIDTH_TU[DPModuleIndex], DPHWidthTURegValue.Value, DPHWidthTURegMask.Value); DPExtPacketRegValue.Value = 0; - DPExtPacketRegValue.Horizontal_Width_bit12to11 = ((pTiming->HorDisEnd / pMainLinkParams->LaneNumberToUse - 1) >> 11); + DPExtPacketRegValue.Horizontal_Width_bit12to11 = ((pTiming->HorDisEnd / pMainLinkParams->LinkedLaneNumber - 1) >> 11); DPExtPacketRegMask.Value = 0xFFFFFFFF; DPExtPacketRegMask.Horizontal_Width_bit12to11 = 0; cbMMIOWriteReg32(pcbe, DP_REG_EXT_PACKET[DPModuleIndex], DPExtPacketRegValue.Value, DPExtPacketRegMask.Value); @@ -1522,10 +1655,10 @@ CBIOS_BOOL cbDIU_DP_SetUpMainLink(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule } /*previous setting -35, will lead to audio abnormal with some specific timing(ex. 800x600@75), change it to 64*/ - ulTemp3 = (cb_do_div(ulTemp1 * pMainLinkParams->LinkSpeedToUse, pTiming->PixelClock) & 0x00000FFF) - 64; + ulTemp3 = (cb_do_div(ulTemp1 * pMainLinkParams->LinkedSpeed, pTiming->PixelClock) & 0x00000FFF) - 64; ulTemp2 = pTiming->HorTotal; - ulTemp1 = cb_do_div(ulTemp2 * pMainLinkParams->LinkSpeedToUse, pTiming->PixelClock) - 64; + ulTemp1 = cb_do_div(ulTemp2 * pMainLinkParams->LinkedSpeed, pTiming->PixelClock) - 64; DPHLineDurRegValue.Value = 0; DPHLineDurRegValue.Horiz_Line_Duration = (CBIOS_U32)ulTemp1; @@ -1544,13 +1677,13 @@ CBIOS_BOOL cbDIU_DP_SetUpMainLink(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule // M/N = Dclk / Ls_clk, but N must be 32768 to work with Parade DP // So, N = 32768, M = Dclk * 32768 / Ls_clk // Mvid and Nvid are not needed if in asynchronous mode, set it anyway - if (pMainLinkParams->LinkSpeedToUse == 0) // Prevent being divided by zero + if (pMainLinkParams->LinkedSpeed == 0) // Prevent being divided by zero { cbDebugPrint((MAKE_LEVEL(DP, ERROR), "%s: fata error -- LinkSpeed is ZERO!!!\n", FUNCTION_NAME)); bStatus = CBIOS_FALSE; goto Exit; } - ulTemp1 = cb_do_div(32768 * ((CBIOS_U64)(pTiming->PixelClock)), pMainLinkParams->LinkSpeedToUse); // N = 32768 + ulTemp1 = cb_do_div(32768 * ((CBIOS_U64)(pTiming->PixelClock)), pMainLinkParams->LinkedSpeed); // N = 32768 DPMisc0RegValue.Value = 0; DPMisc0RegValue.MVID = (CBIOS_U32)ulTemp1; diff --git a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.h b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.h index 9961c8ff017e5..93e9591716f26 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.h +++ b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_DP.h @@ -131,8 +131,8 @@ typedef struct _CBIOS_LINK_TRAINING_PARAMS typedef struct _CBIOS_MAIN_LINK_PARAMS { - CBIOS_U32 LaneNumberToUse; // 1 ~ 4 lanes - CBIOS_U32 LinkSpeedToUse; // 1.62Gbps, 2.7Gbps or 5.4Gbps + CBIOS_U32 LinkedLaneNumber; // 1 ~ 4 lanes + CBIOS_U32 LinkedSpeed; // 1.62Gbps, 2.7Gbps or 5.4Gbps CBIOS_U32 bpc; // bit per channel CBIOS_U32 TUSize; // 32 ~ 64, default to 48 CBIOS_BOOL AsyncMode; // 1 (yes), asynchronous mode diff --git a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_HDAC.c b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_HDAC.c index 02db13f7bccde..338a26966b28b 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_HDAC.c +++ b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosDIU_HDAC.c @@ -474,8 +474,21 @@ CBIOS_VOID cbDIU_HDAC_SetHDACodecPara(PCBIOS_VOID pvcbe, PCBIOS_HDAC_PARA pCbios { PCBIOS_DP_MONITOR_CONTEXT pDPMonitorContext = cbGetDPMonitorContext(pcbe, pDevCommon); CBIOS_MODULE_INDEX DPModuleIndex = cbGetModuleIndex(pcbe, Device, CBIOS_MODULE_TYPE_DP); + CBIOS_U32 LinkSpeed = pDPMonitorContext->LinkPassSpeed; - cbDIU_DP_SetMaudNaud(pcbe, DPModuleIndex, pDPMonitorContext->LinkSpeedToUse, StreamFormat); + if(!LinkSpeed) + { + if(pDPMonitorContext->SinkMaxLinkSpeed) + { + LinkSpeed = pDPMonitorContext->SinkMaxLinkSpeed; + } + else + { + LinkSpeed = CBIOS_DP_LINK_SPEED_5400Mbps; + } + } + + cbDIU_DP_SetMaudNaud(pcbe, DPModuleIndex, LinkSpeed, StreamFormat); } #endif diff --git a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosPHY_DP.c b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosPHY_DP.c index df00fb8541140..1c1b26ac8088d 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosPHY_DP.c +++ b/drivers/gpu/drm/arise/cbios/Hw/HwBlock/CBiosPHY_DP.c @@ -97,6 +97,7 @@ CBIOS_VOID cbPHY_DP_DPModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIn REG_MM8340 DPEphyMpllRegValue, DPEphyMpllRegMask; REG_MM8344 DPEphyTxRegValue, DPEphyTxRegMask; REG_MM8348 DPEphyMiscRegValue, DPEphyMiscRegMask; + CBIOS_BOOL bACE = ((pcbe->ChipID == CHIPID_ARISE2030) || (pcbe->ChipID == CHIPID_ARISE2020)) ? CBIOS_TRUE : CBIOS_FALSE; cbTraceEnter(DP); @@ -149,6 +150,15 @@ CBIOS_VOID cbPHY_DP_DPModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIn DPEphyMiscRegMask.T1V = 0; DPEphyMiscRegMask.TT = 0; cbMMIOWriteReg32(pcbe, DP_REG_EPHY_MISC[DPModuleIndex], DPEphyMiscRegValue.Value, DPEphyMiscRegMask.Value); + + if (bACE && LinkSpeed == CBIOS_DP_LINK_SPEED_5400Mbps) + { + DPEphyMpllRegValue.Value = 0; + DPEphyMpllRegValue.TPLL_N_Div = 0; + DPEphyMpllRegMask.Value = 0xFFFFFFFF; + DPEphyMpllRegMask.TPLL_N_Div = 0; + cbMMIOWriteReg32(pcbe, DP_REG_EPHY_MPLL[DPModuleIndex], DPEphyMpllRegValue.Value, DPEphyMpllRegMask.Value); + } } else//DP off { @@ -308,7 +318,6 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule } else { - DPEphyMiscRegValue.T1V = 0; DPEphyMiscRegValue.MT = 1; DPEphyMiscRegValue.EPHY1_TPLL_CP = 8; @@ -372,7 +381,7 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPEphyStatusRegValue.Value = 0; DPEphyStatusRegValue.EPHY1_TPLL_ISEL = 0; - if ((ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T)) || (ClockFreq < 3400000 && bACE)) + if ((ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T)) || (ClockFreq != 5940000 && bACE)) { DPEphyStatusRegValue.TR = 0; DPEphyStatusRegValue.TC = 7; @@ -399,13 +408,13 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPEphySetting1RegValue.EPHY1_SR_SPD = 0; DPEphySetting1RegValue.EPHY1_SR_DLY = 0; DPEphySetting1RegValue.EPHY1_SR_NDLY = 0; - if (ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T)) //signal will be better if set FBOOST = 1 when clock is 594M + if (ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T || bACE)) //signal will be better if set FBOOST = 1 when clock is 594M { DPEphySetting1RegValue.EPHY1_FBOOST = 2; } else { - DPEphySetting1RegValue.EPHY1_FBOOST = bACE ? 2 : 1; + DPEphySetting1RegValue.EPHY1_FBOOST = 1; } } else if(ClockFreq >= 1700000) @@ -537,6 +546,12 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule if(ClockFreq > 3400000) { + DPSwingRegMask.Value = 0xFFFFFFFF; + DPSwingRegMask.enable_SW_swing_pp = 0; + DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; + DPSwingRegMask.DP1_SW_swing = 0; + DPSwingRegMask.DP1_SW_pp = 0; + DPSwingRegMask.DP1_SW_post_cursor = 0; if(ClockFreq == 5940000 && (pcbe->ChipID == CHIPID_E3K || pcbe->ChipID == CHIPID_ARISE10C0T)) { DPSwingRegValue.Value = 0; @@ -545,13 +560,6 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPSwingRegValue.DP1_SW_swing = 0x3F; DPSwingRegValue.DP1_SW_pp = 0xA; DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); DPSwingRegValue.Value = 0; @@ -560,13 +568,6 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPSwingRegValue.DP1_SW_swing = 0x33; DPSwingRegValue.DP1_SW_pp = 9; DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); DPSwingRegValue.Value = 0; @@ -575,60 +576,50 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPSwingRegValue.DP1_SW_swing = 0x21; DPSwingRegValue.DP1_SW_pp = 0; DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + } + else if(ClockFreq == 5940000 && bACE) + { + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 9; + DPSwingRegValue.DP1_SW_swing = 0x2F; + DPSwingRegValue.DP1_SW_pp = 0x9; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); + + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 1; + DPSwingRegValue.DP1_SW_swing = 0x36; + DPSwingRegValue.DP1_SW_pp = 0xB; + DPSwingRegValue.DP1_SW_post_cursor = 0; + cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; + DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; + DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 5; + DPSwingRegValue.DP1_SW_swing = 0x21; + DPSwingRegValue.DP1_SW_pp = 0; + DPSwingRegValue.DP1_SW_post_cursor = 0; cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); } else { - if(bACE) - { - DPSwingRegValue.Value = 0; - DPSwingRegValue.enable_SW_swing_pp = 1; - DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 9; - DPSwingRegValue.DP1_SW_swing = 0x2E; - DPSwingRegValue.DP1_SW_pp = 0x9; - DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; - cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); - } DPSwingRegValue.Value = 0; DPSwingRegValue.enable_SW_swing_pp = 1; DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 1; - DPSwingRegValue.DP1_SW_swing = bACE ? 0x36 : 0x3F; - DPSwingRegValue.DP1_SW_pp = bACE ? 0x1A : 0x18; + DPSwingRegValue.DP1_SW_swing = 0x3F; + DPSwingRegValue.DP1_SW_pp = 0x18; DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.enable_SW_swing_pp = 0; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); DPSwingRegValue.Value = 0; + DPSwingRegValue.enable_SW_swing_pp = 1; DPSwingRegValue.SW_swing_SW_PP_SW_post_cursor_load_index = 5; DPSwingRegValue.DP1_SW_swing = 0x21; DPSwingRegValue.DP1_SW_pp = 0; DPSwingRegValue.DP1_SW_post_cursor = 0; - - DPSwingRegMask.Value = 0xFFFFFFFF; - DPSwingRegMask.SW_swing_SW_PP_SW_post_cursor_load_index = 0; - DPSwingRegMask.DP1_SW_swing = 0; - DPSwingRegMask.DP1_SW_pp = 0; - DPSwingRegMask.DP1_SW_post_cursor = 0; cbMMIOWriteReg32(pcbe, DP_REG_SWING[DPModuleIndex], DPSwingRegValue.Value, DPSwingRegMask.Value); } DPLinkRegValue.Value = 0; @@ -642,7 +633,7 @@ CBIOS_VOID cbPHY_DP_DualModeOnOff(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModule DPLinkRegValue.SW_Link_Train_State = 1; DPLinkRegValue.Software_Bit_Rate = 0; DPLinkRegValue.SW_Lane0_Swing = 0; - DPLinkRegValue.SW_Lane0_Pre_emphasis = bACE ? 2 : 0; + DPLinkRegValue.SW_Lane0_Pre_emphasis = (ClockFreq == 5940000 && bACE) ? 2 : 0; DPLinkRegValue.SW_Lane1_Swing = 0; DPLinkRegValue.SW_Lane1_Pre_emphasis = 0; DPLinkRegValue.SW_Lane2_Swing = 0; @@ -959,6 +950,7 @@ CBIOS_VOID cbPHY_DP_InitEPHY(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIndex REG_MM334E0 DPEphySetting1RegValue, DPEphySetting1RegMask; REG_MM334E4 DPEphySetting2RegValue, DPEphySetting2RegMask; REG_MM334C8 DPLinkCtrlRegValue, DPLinkCtrlRegMask; + CBIOS_BOOL bACE = ((pcbe->ChipID == CHIPID_ARISE2030) || (pcbe->ChipID == CHIPID_ARISE2020)) ? CBIOS_TRUE : CBIOS_FALSE; cbTraceEnter(DP); @@ -1332,10 +1324,21 @@ CBIOS_VOID cbPHY_DP_InitEPHY(PCBIOS_VOID pvcbe, CBIOS_MODULE_INDEX DPModuleIndex // TX output duty-cycle adjust DPEphySetting2RegValue.Value = 0; - DPEphySetting2RegValue.EPHY1_TXDU_L0 = 0x3F; - DPEphySetting2RegValue.EPHY1_TXDU_L1 = 0x3F; - DPEphySetting2RegValue.EPHY1_TXDU_L2 = 0x3F; - DPEphySetting2RegValue.EPHY1_TXDU_L3 = 0x3F; + if (bACE) + { + DPEphySetting2RegValue.EPHY1_TXDU_L0 = 0x3C; + DPEphySetting2RegValue.EPHY1_TXDU_L1 = 0x3C; + DPEphySetting2RegValue.EPHY1_TXDU_L2 = 0x3C; + DPEphySetting2RegValue.EPHY1_TXDU_L3 = 0x3C; + } + else + { + DPEphySetting2RegValue.EPHY1_TXDU_L0 = 0x3F; + DPEphySetting2RegValue.EPHY1_TXDU_L1 = 0x3F; + DPEphySetting2RegValue.EPHY1_TXDU_L2 = 0x3F; + DPEphySetting2RegValue.EPHY1_TXDU_L3 = 0x3F; + } + DPEphySetting2RegValue.EPHY1_TX_VMR = 0xF; DPEphySetting2RegValue.EPHY1_TX_VMX = 0; DPEphySetting2RegMask.Value = 0xE0000000; diff --git a/drivers/gpu/drm/arise/cbios/Hw/HwInterface/CBiosHwInterface.c b/drivers/gpu/drm/arise/cbios/Hw/HwInterface/CBiosHwInterface.c index 3d66b02e73887..cba036b402c9e 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/HwInterface/CBiosHwInterface.c +++ b/drivers/gpu/drm/arise/cbios/Hw/HwInterface/CBiosHwInterface.c @@ -177,7 +177,6 @@ CBIOS_STATUS cbHWUnload(PCBIOS_VOID pvcbe) cbDeInitDeviceArray(pcbe); cbDispMgrDeInit(pcbe); - cbReleaseDebugBuffer(); return CBIOS_OK; } @@ -691,7 +690,7 @@ CBIOS_STATUS cbHwSyncDataWithVbios(PCBIOS_VOID pvcbe, PCBIOS_VBIOS_DATA_PARAM } else { - cbDebugPrint((0, "CBiosSyncDataWithVbios_dst: null pointer is transfered!\n")); + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "CBiosSyncDataWithVbios_dst: null pointer is transfered!\n")); return CBIOS_ER_NULLPOINTER; } } @@ -1179,7 +1178,7 @@ CBIOS_STATUS cbHWCECTransmitMessage(PCBIOS_VOID pvcbe, PCBIOS_CEC_MESSAGE pCECMe } else { - cbDebugPrint((DBG_LEVEL_ERROR_MSG, "cbHWCECTransmitMessage: Message transmission fail!\n")); + cbDebugPrint((MAKE_LEVEL(HDMI, ERROR), "cbHWCECTransmitMessage: Message transmission fail!\n")); Status = CBIOS_ER_INTERNAL; } @@ -1280,7 +1279,7 @@ CBIOS_STATUS cbHWCECReceiveMessage(PCBIOS_VOID pvcbe, PCBIOS_CEC_MESSAGE pCECMes } else { - cbDebugPrint((DBG_LEVEL_ERROR_MSG, "cbHWCECReceiveMessage: Message receive fail!\n")); + cbDebugPrint((MAKE_LEVEL(HDMI, ERROR), "cbHWCECReceiveMessage: Message receive fail!\n")); Status = CBIOS_ER_INTERNAL; } diff --git a/drivers/gpu/drm/arise/cbios/Hw/HwUtil/CBiosUtilHw.c b/drivers/gpu/drm/arise/cbios/Hw/HwUtil/CBiosUtilHw.c index ebc8aafcfdbce..fbf12c93aa5b1 100644 --- a/drivers/gpu/drm/arise/cbios/Hw/HwUtil/CBiosUtilHw.c +++ b/drivers/gpu/drm/arise/cbios/Hw/HwUtil/CBiosUtilHw.c @@ -1243,7 +1243,7 @@ CBIOS_U32 cbGetProgClock(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_U32 *ClockFreq, CBI { return -1; } - if (pcbe->ChipID == CHIPID_ARISE1020 && ClockType == CBIOS_MCLKTYPE) + if ((pcbe->ChipID == CHIPID_ARISE1020 || pcbe->ChipID == CHIPID_ARISE2030) && ClockType == CBIOS_MCLKTYPE) { D300_Value = cb_ReadU32(pcbe->pAdapterContext, 0xD300); bUseNewMclk = ((D300_Value & 0xF) == 0xA) ? CBIOS_TRUE : CBIOS_FALSE; @@ -1319,8 +1319,7 @@ CBIOS_U32 cbGetProgClock(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_U32 *ClockFreq, CBI break; } - if ((pcbe->ChipID == CHIPID_ARISE10C0T && (ClockType == CBIOS_ECLKTYPE || ClockType == CBIOS_VCLKTYPE)) || - (pcbe->ChipID == CHIPID_ARISE1020 && ClockType == CBIOS_MCLKTYPE && bUseNewMclk)) + if ((pcbe->ChipID == CHIPID_ARISE10C0T && (ClockType == CBIOS_ECLKTYPE || ClockType == CBIOS_VCLKTYPE)) || bUseNewMclk) { (*ClockFreq) *= 10000; } diff --git a/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.c b/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.c index c2a996b469bc6..d6174496e0bf7 100644 --- a/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.c +++ b/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.c @@ -671,7 +671,8 @@ static CBIOS_U32 cbEDIDModule_GetCEADetailedMode(CBIOS_U8 *pEDID, PCBIOS_MODE_IN while ((i + 18) < 128) { cb_memset(&tmpExtDltTiming, 0, sizeof(CBIOS_MODE_INFO_EXT)); - if (!cbEDIDModule_ParseDtlTiming(&pEDIDBlock[i], &tmpExtDltTiming)) + if (!cbEDIDModule_ParseDtlTiming(&pEDIDBlock[i], &tmpExtDltTiming) + || ulNumOfExtDtlMode >= CBIOS_DTDTIMING_BLOCK_CNT) { break; } @@ -801,6 +802,11 @@ static CBIOS_U32 cbEDIDModule_GetHDMIAudioFormat(CBIOS_U8 *pAudioFormatDataInEDI for (j = 0; j < PayloadLength/3; j++) { + if(ulNumOfAudioFormat >= CBIOS_HDMI_AUDIO_FORMAT_COUNTS) + { + break; + } + AudioFormatCode = (pAudioFormatDataInEDID[1 + j * 3] >> 3) & 0xF; if ((AudioFormatCode > 0) && (AudioFormatCode < 16)) { @@ -890,11 +896,12 @@ static CBIOS_VOID cbEDIDPatchHDMIAudio(PCBIOS_EDID_STRUCTURE_DATA pEDIDStruct, P } } -static CBIOS_VOID cbEDIDPatchHDMICEAMode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTURE_DATA pEDIDStruct, PCBIOS_U32 pModeNumOfCEABlock) +static CBIOS_VOID cbEDIDPatchCEAModes(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTURE_DATA pEDIDStruct, PCBIOS_U32 pModeNumOfCEABlock) { PCBIOS_MONITOR_MISC_ATTRIB pMonitorAttrib = &(pEDIDStruct->Attribute); PCBIOS_HDMI_FORMAT_DESCRIPTOR pCEAVideoFormat = pEDIDStruct->HDMIFormat; CBIOS_UCHAR MonitorID[8] = {0}; + CBIOS_U32 i = 0; if ((pMonitorAttrib == CBIOS_NULL) || (pCEAVideoFormat == CBIOS_NULL)) { @@ -912,6 +919,25 @@ static CBIOS_VOID cbEDIDPatchHDMICEAMode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTURE_ cbDebugPrint((MAKE_LEVEL(GENERIC, DEBUG), "%s: filter 1080p@24Hz, ModeNumOfCEABlock = %d\n", FUNCTION_NAME, *pModeNumOfCEABlock)); } + // patch for BenQ EL2870U monitor, filter 3840x2160@29.97Hz mode in DTDTimings for no sound issue. + if ((!cb_strcmp(MonitorID, (CBIOS_UCHAR*)"BNQ7949")) && (!cb_strcmp(pMonitorAttrib->MonitorName, (CBIOS_UCHAR*)"BenQ EL2870U"))) + { + for (i = 0; i < CBIOS_DTDTIMING_BLOCK_CNT; i++) + { + if ((pEDIDStruct->DTDTimings[i].Valid) && + (pEDIDStruct->DTDTimings[i].XResolution == 3840) && + (pEDIDStruct->DTDTimings[i].YResolution == 2160) && + ((pEDIDStruct->DTDTimings[i].Refreshrate >= (3000 - 50)) && + (pEDIDStruct->DTDTimings[i].Refreshrate <= (3000 + 50)))) + { + pEDIDStruct->DTDTimings[i].Valid = CBIOS_FALSE; + *pModeNumOfCEABlock = *pModeNumOfCEABlock - 1; + cbDebugPrint((MAKE_LEVEL(GENERIC, DEBUG), "%s: filter 3840x2160@29.97Hz, ModeNumOfCEABlock = %d\n", FUNCTION_NAME, *pModeNumOfCEABlock)); + break; + } + } + } + } /*************************************************************** @@ -1268,24 +1294,43 @@ static CBIOS_U32 cbEDIDModule_ParseHDMIVSDB(CBIOS_U8 *pVSDBDataInEDID, PCBIOS_HD } +//HFVSDB + /*************************************************************** -Function: cbEDIDModule_ParseHFVSDB +Function: cbEDIDModule_ParseHFSCDS -Description: Decode HDMI Forum vendor specific data block of CEA extension +Description: Decode HF-VSDB or HF-SCDB of CEA extension -Input: pVSDBDataInEDID, HDMI Forum vendor specific data buffer +Input: pSCDSDataInEDID, HDMI Forum vendor specific data buffer, or Sink Capability data block buffer -Output: pVSDBData, decoded HDMI Forum VSDB data +Output: pSCDSData, decoded Sink capability data structure -Return: the total length of HDMI Forum vendor specific data block +Return: the total length of HDMI Forum vendor specific data block, or Sink capability data block ***************************************************************/ /* - HDMI Forum Vendor Specific Data Block + SCDS (Sink Capability Data Structure) + |-----------|---------------------------------------------------------------------------------------------------------------| + | PB1 | Version (=1) | + |-----------|---------------------------------------------------------------------------------------------------------------| + | PB2 | Max_TMDS_Character_Rate | + |-----------|---------------------------------------------------------------------------------------------------------------| + | | SCDC_ | RR_ | Rsvd | Rsvd | LTE_340Mcsc| Independent | Dual | 3D_OSD_ | + | PB3 | Present | Capable | (0) | (0) | _scramble | _view | _View | Disparity | + |-----------|---------------------------------------------------------------------------------------------------------------| + | | Rsvd | Rsvd | Rsvd | Rsvd | Rsvd | DC_48Bit | DC_36Bit | DC_30Bit | + | PB4 | (0) | (0) | (0) | (0) | (0) | _420 | _420 | _420 | + |-----------|---------------------------------------------------------------------------------------------------------------| + | ...N | ... | + |---------------------------------------------------------------------------------------------------------------------------| + +** Sinks shall include only one SCDS, in HF-VSDB or HF-SCDB + + HDMI Forum Vendor Specific Data Block ----------------------------------------------------------------------------------------------------------------------------- |Byte\Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-----------|---------------------------------------------------------------------------------------------------------------| - | | Vendor-specific tag code (=3) | Length (=N) | + | 0 | Vendor-specific tag code (=3) | Length (=N) | |-----------|---------------------------------------------------------------------------------------------------------------| | 1 | IEEE OUI, Third Octet (0xD8) | |-----------|---------------------------------------------------------------------------------------------------------------| @@ -1293,77 +1338,98 @@ Return: the total length of HDMI Forum vendor specific data block |-----------|---------------------------------------------------------------------------------------------------------------| | 3 | IEEE OUI, First Octet (0xC4) | |-----------|---------------------------------------------------------------------------------------------------------------| - | 4 | Version (=1) | + | 4..n | ** SCDS | |-----------|---------------------------------------------------------------------------------------------------------------| - | 5 | Max_TMDS_Character_Rate | + + + HDMI Forum Sink Capability Data Block + ----------------------------------------------------------------------------------------------------------------------------- + |Byte\Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-----------|---------------------------------------------------------------------------------------------------------------| - | | SCDC_ | RR_ | Rsvd | Rsvd | LTE_340Mcsc| Independent | Dual | 3D_OSD_ | - | 6 | Present | Capable | (0) | (0) | _scramble | _view | _View | Disparity | + | 0 | Vendor-specific tag code (=7) | Length (=N) | |-----------|---------------------------------------------------------------------------------------------------------------| - | | Rsvd | Rsvd | Rsvd | Rsvd | Rsvd | DC_48Bit | DC_36Bit | DC_30Bit | - | 7 | (0) | (0) | (0) | (0) | (0) | _420 | _420 | _420 | + | 1 | Extended Tag Code (0x79) | + |-----------|---------------------------------------------------------------------------------------------------------------| + | 2 | Reserved | + |-----------|---------------------------------------------------------------------------------------------------------------| + | 3 | Reserved | + |-----------|---------------------------------------------------------------------------------------------------------------| + | 4..n | ** SCDS | |-----------|---------------------------------------------------------------------------------------------------------------| - | ...N | Reserved(0)* | - |---------------------------------------------------------------------------------------------------------------------------| - */ -static CBIOS_U32 cbEDIDModule_ParseHFVSDB(CBIOS_U8 *pVSDBDataInEDID, PCBIOS_HF_HDMI_VSDB_EXTENTION pVSDBData) +static CBIOS_U32 cbEDIDModule_ParseHFSCDS(CBIOS_U8 *pSCDSDataInEDID, PCBIOS_HF_SCDS_DATA pSCDSData) { - CBIOS_U8 *pCurByte = pVSDBDataInEDID; + CBIOS_U8 *pCurByte = pSCDSDataInEDID; CBIOS_U32 PayloadLen = 0; - if ((pVSDBDataInEDID == CBIOS_NULL) || (pVSDBData == CBIOS_NULL)) + if ((pSCDSDataInEDID == CBIOS_NULL) || (pSCDSData == CBIOS_NULL)) { - cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "cbEDIDModule_ParseHFVSDB: NULL pointer!\n")); + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: NULL pointer!\n", FUNCTION_NAME)); return 0; } - //initialize CBIOS_HDMI_VSDB_EXTENTION - cb_memset(pVSDBData, 0, sizeof(CBIOS_HF_HDMI_VSDB_EXTENTION)); - - //check tag and length - cb_memcpy(&(pVSDBData->Tag), pCurByte++, sizeof(pVSDBData->Tag)); + cb_memset(pSCDSData, 0, sizeof(CBIOS_HF_SCDS_DATA)); - if ((pVSDBData->Tag.VSDBTag != VENDOR_SPECIFIC_DATA_BLOCK_TAG) - ||(pVSDBData->Tag.VSDBLength < 7)) + cb_memcpy(&(pSCDSData->Tag), pCurByte++, sizeof(pSCDSData->Tag)); + //byte 0 Tag and length + if (pSCDSData->Tag.CTATag == VENDOR_SPECIFIC_DATA_BLOCK_TAG + && pSCDSData->Tag.Length >= 7) { - cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "cbEDIDModule_ParseHFVSDB: invalid VSDB data!\n")); - pVSDBData->Tag.VSDBLength = 0; + // HF-VSDB + // byte 1-3, The IEEE Organizationally Unique Identifier (OUI) of C4-5D-D8 + pSCDSData->HFVSDBOUI.IEEEOUIByte0 = *(pCurByte++); + pSCDSData->HFVSDBOUI.IEEEOUIByte1 = *(pCurByte++); + pSCDSData->HFVSDBOUI.IEEEOUIByte2 = *(pCurByte++); + PayloadLen += 3; } - else//tag OK + else if (pSCDSData->Tag.CTATag == CEA_EXTENDED_BLOCK_TAG + && *pCurByte == HF_SINK_CAPABILITY_DATA_BLOCK + && pSCDSData->Tag.Length >= 7) { - PayloadLen = 0; - //Byte 1-3, The IEEE Organizationally Unique Identifier (OUI) of C4-5D-D8 - pVSDBData->HFVSDBOUI.IEEEOUIByte0 = *(pCurByte++); - pVSDBData->HFVSDBOUI.IEEEOUIByte1 = *(pCurByte++); - pVSDBData->HFVSDBOUI.IEEEOUIByte2 = *(pCurByte++); + // HF-SCDB + // byte 1, Extended Tag Code + pSCDSData->ExtTagCode = *(pCurByte++); + // byte 2~3, reserved + pCurByte += 2; PayloadLen += 3; + } + else + { + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: no valid HF-VSDB or HF-SCDB data!\n", FUNCTION_NAME)); + pSCDSData->Tag.Length = 0; + } - //byte 4 version - pVSDBData->Version = *(pCurByte++); + if (pSCDSData->Tag.Length) //tag ok + { + //byte 4 version + pSCDSData->Version = *(pCurByte++); PayloadLen++; - //byte 5 Max_TMDS_Character_Rate in MHz / 5 - pVSDBData->MaxTMDSCharacterRate = (CBIOS_U16)(*pCurByte) * 5; + //byte 5 Max_TMDS_Character_Rate in MHz / 5 + pSCDSData->MaxTMDSCharacterRate = (CBIOS_U16)(*pCurByte) * 5; pCurByte++; PayloadLen++; //byte 6-7 - cb_memcpy(&(pVSDBData->SupportCaps), pCurByte, sizeof(CBIOS_U16)); - pCurByte += 2; + cb_memcpy(&(pSCDSData->SupportCaps), pCurByte, sizeof(CBIOS_U16)); + // Patch for Issue 21429, Issue21458: SCDCPresent is false that can't call cbHDMIMonitor_SCDC_Configure(). + if (pSCDSData->MaxTMDSCharacterRate > 340) + { + pSCDSData->IsSCDCPresent = CBIOS_TRUE; + } + pCurByte += 2; PayloadLen += 2; } //check payload length - if (PayloadLen != pVSDBData->Tag.VSDBLength) + if (PayloadLen != pSCDSData->Tag.Length) { - cbDebugPrint((MAKE_LEVEL(GENERIC, WARNING), "cbEDIDModule_ParseHFVSDB: payload length error!\n")); + cbDebugPrint((MAKE_LEVEL(GENERIC, WARNING), "%s: payload length error !\n", FUNCTION_NAME)); } //block total length = payload len + 1 - return (pVSDBData->Tag.VSDBLength + 1); - + return (pSCDSData->Tag.Length + 1); } @@ -1421,6 +1487,12 @@ static CBIOS_U32 cbEDIDModule_ParseCEAExtBlock(CBIOS_U8 *pExtBlockDataInEDID, PC pCEAExtData = &pEDIDStruct->Attribute.ExtDataBlock[COLORIMETRY_DATA_BLOCK_TAG]; cb_memcpy(&pCEAExtData->ColorimetryData, &pExtBlockDataInEDID[2], sizeof(CBIOS_COLORIMETRY_DATA)); } + else if(ExtTagCode == HDR_STATIC_META_DATA_BLOCK) + { + + cbDebugPrint((MAKE_LEVEL(GENERIC, INFO), "%s: EDID HDR data\n", FUNCTION_NAME)); + + } else if(ExtTagCode == VIDEO_FMT_PREFERENCE_DATA_BLOCK) { /* @@ -1661,6 +1733,15 @@ static CBIOS_U32 cbEDIDModule_ParseCEAExtBlock(CBIOS_U8 *pExtBlockDataInEDID, PC Index += Len; } } + else if(ExtTagCode == HF_EDID_EXTENSION_OVERRIDE_DATA_BLOCK) + { + // HF-EEODB for ext block num, already parsed by cbEDIDModule_GetExtBlockNum + PayloadLen = (*pExtBlockDataInEDID) & 0x1F; + } + else if(ExtTagCode == HF_SINK_CAPABILITY_DATA_BLOCK) + { + PayloadLen = cbEDIDModule_ParseHFSCDS(pExtBlockDataInEDID, &(pEDIDStruct->Attribute.HFSCDSData)) - 1; + } else { cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "cbEDIDModule_ParseCEAExtBlock: ExtTagCode = 0x%x which is not parsed yet!\n", ExtTagCode)); @@ -1872,6 +1953,11 @@ static CBIOS_U32 cbEDIDModule_GetDisplayIDType1DetailedMode(CBIOS_U8 *pType1Timi for (i = 0; i < PayloadLen/DID_TYPE1_TIMING_DESCRIPTOR_LENGTH; i++) { + if(ulNumOfModes >= CBIOS_DISPLAYID_TYPE1_MODECOUNT) + { + break; + } + pDisplayIDDtlMode[ulNumOfModes].PixelClock = (((pType1TimingInEDID[5 + i*20] << 16) | (pType1TimingInEDID[4 + i*20] << 8) | (pType1TimingInEDID[3 + i*20])) * 100); if(pDisplayIDDtlMode[ulNumOfModes].PixelClock == 0) { @@ -1912,6 +1998,42 @@ static CBIOS_U32 cbEDIDModule_GetDisplayIDType1DetailedMode(CBIOS_U8 *pType1Timi return ulNumOfModes; } +CBIOS_U32 cbEDIDModule_GetExtBlockNum(CBIOS_U8 *pEDID) +{ + CBIOS_U32 ExtBlockNum = 0; + + if (!pEDID) + { + cbDebugPrint((MAKE_LEVEL(GENERIC, ERROR), "%s: invalid EDID\n", FUNCTION_NAME)); + return 0; + } + + if (!pEDID[0x7E]) // Extension Flag + { + ExtBlockNum = 0; + } + else + { + if ((pEDID[0x84] >> 5 == CEA_EXTENDED_BLOCK_TAG) && + (pEDID[0x85] == HF_EDID_EXTENSION_OVERRIDE_DATA_BLOCK)) // be HF-EEODB + { + ExtBlockNum = pEDID[0x86]; + } + else + { + ExtBlockNum = pEDID[0x7E]; + } + } + + if(ExtBlockNum > (CBIOS_EDIDMAXBLOCKCOUNT - 1)) + { + cbDebugPrint((MAKE_LEVEL(GENERIC, WARNING), "%s: block num > %d, need refine!\n", FUNCTION_NAME, CBIOS_EDIDMAXBLOCKCOUNT)); + ExtBlockNum = CBIOS_EDIDMAXBLOCKCOUNT - 1; + } + + return ExtBlockNum; +} + /*************************************************************** Function: cbEDIDModule_GetCEADetailedMode @@ -1974,7 +2096,7 @@ static CBIOS_U32 cbEDIDModule_GetCEA861Mode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTU //audio data block AudioFormatDataOffset = (CBIOS_U8)i; PayloadLength = pEDIDBlock[i++] & 0x1F; - pEDIDStruct->TotalHDMIAudioFormatNum += cbEDIDModule_GetHDMIAudioFormat(&pEDIDBlock[AudioFormatDataOffset], pEDIDStruct->HDMIAudioFormat); + pEDIDStruct->TotalHDMIAudioFormatNum = cbEDIDModule_GetHDMIAudioFormat(&pEDIDBlock[AudioFormatDataOffset], pEDIDStruct->HDMIAudioFormat); i += PayloadLength; } else if (((pEDIDBlock[i] >> 5) & 0x07) == VIDEO_DATA_BLOCK_TAG) @@ -1997,7 +2119,7 @@ static CBIOS_U32 cbEDIDModule_GetCEA861Mode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTU (pEDIDBlock[i + 2] == 0x5D) && (pEDIDBlock[i + 3] == 0xC4)) { - i += cbEDIDModule_ParseHFVSDB(&pEDIDBlock[i], &(pEDIDStruct->Attribute.HFVSDBData)); + i += cbEDIDModule_ParseHFSCDS(&pEDIDBlock[i], &(pEDIDStruct->Attribute.HFSCDSData)); } else { @@ -2024,8 +2146,6 @@ static CBIOS_U32 cbEDIDModule_GetCEA861Mode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTU } //some monitor's AUDIO_DATA_BLOCK not support LPCM,but it indicates support basic audio, should patch here cbEDIDPatchHDMIAudio(pEDIDStruct,&pEDIDStruct->HDMIAudioFormat[0]); - //patch for some monitor can't display some CEA modes. - cbEDIDPatchHDMICEAMode(pEDID, pEDIDStruct, &ulModeNumOfCEABlock); // get the detailed timing in CEA extension ulModeNumOfCEABlock += cbEDIDModule_GetCEADetailedMode(pEDID, pEDIDStruct->DTDTimings, TotalBlocks); @@ -2055,6 +2175,9 @@ static CBIOS_U32 cbEDIDModule_GetCEA861Mode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRUCTU } } + //patch for some monitor can't display some CEA modes. + cbEDIDPatchCEAModes(pEDID, pEDIDStruct, &ulModeNumOfCEABlock); + return ulModeNumOfCEABlock; } @@ -2067,7 +2190,7 @@ static CBIOS_U32 cbEDIDModule_GetDisplayIDMode(CBIOS_U8 *pEDID, PCBIOS_EDID_STRU CBIOS_U32 i = 0; CBIOS_U32 ulModeNumOfDisplayIDBlock = 0; - TotalBlocks = pEDID[0x7E] + 1; // Ext. blocks plus base block. + TotalBlocks = 1 + cbEDIDModule_GetExtBlockNum(pEDID); // Ext. blocks plus base block. if (TotalBlocks > MAX_EDID_BLOCK_NUM) { // TBD: support for more than 8 blocks @@ -2459,9 +2582,9 @@ CBIOS_STATUS cbEDIDModule_GetMonitor3DCaps(PCBIOS_EDID_STRUCTURE_DATA pEDIDStruc pModeList->RefreshRate = CEAVideoFormatTable[i].RefRate[pSupportFormat[i].RefreshIndex]; pModeList->bIsInterlace = (CBIOS_BOOL)CEAVideoFormatTable[i].Interlace; pModeList->SupportCaps = pSupportFormat[i].Video3DSupportCaps & CBIOS_3D_VIDEO_FORMAT_MASK; - pModeList->IsSupport3DOSDDisparity = pEDIDStruct->Attribute.HFVSDBData.IsSupport3DOSDDisparity; - pModeList->IsSupport3DDualView = pEDIDStruct->Attribute.HFVSDBData.IsSupport3DDualView; - pModeList->IsSupport3DIndependentView = pEDIDStruct->Attribute.HFVSDBData.IsSupport3DIndependentView; + pModeList->IsSupport3DOSDDisparity = pEDIDStruct->Attribute.HFSCDSData.IsSupport3DOSDDisparity; + pModeList->IsSupport3DDualView = pEDIDStruct->Attribute.HFSCDSData.IsSupport3DDualView; + pModeList->IsSupport3DIndependentView = pEDIDStruct->Attribute.HFSCDSData.IsSupport3DIndependentView; pModeList++; } @@ -2570,7 +2693,7 @@ Return: CBIOS_TRUE if get monitor ID successfully ***************************************************************/ CBIOS_BOOL cbEDIDModule_GetMonitorID(CBIOS_U8 *pEDID, CBIOS_U8 *pMonitorID) { - CBIOS_U8 index[32] = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ[/]^_"; + CBIOS_U8 *index = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ[/]^_"; CBIOS_U8 ProductID[3] = {0}; CBIOS_BOOL bRet = CBIOS_FALSE; CBIOS_U8 *pMonitorIDinEDID = pEDID + MONITORIDINDEX; diff --git a/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.h b/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.h index 454652ffe1dcc..bfea11024e46a 100644 --- a/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.h +++ b/drivers/gpu/drm/arise/cbios/Util/CBiosEDID.h @@ -93,7 +93,9 @@ typedef enum _CBIOS_CEA_EXTENDED_BLOCK_TAG RSVD_VESA_VIDEO_DATA_BLOCK_TAG, RSVD_HDMI_VIDEO_DATA_BLOCK, COLORIMETRY_DATA_BLOCK_TAG, - //6-12 reserved for video-related blocks + HDR_STATIC_META_DATA_BLOCK, + HDR_DYNAMIC_META_DATA_BLOCK, + //8-12 reserved for video-related blocks VIDEO_FMT_PREFERENCE_DATA_BLOCK = 0xD, YCBCR420_VIDEO_DATA_BLOCK, YCBCR420_CAP_MAP_DATA_BLOCK, @@ -103,6 +105,8 @@ typedef enum _CBIOS_CEA_EXTENDED_BLOCK_TAG //19-31 reserved for audio-related blocks INFOFRAME_DATA_BLOCK = 0x20, //33-255 reserved for general + HF_EDID_EXTENSION_OVERRIDE_DATA_BLOCK = 0x78, + HF_SINK_CAPABILITY_DATA_BLOCK, MAX_CEA_EXT_DATA_BLOCK_NUM, }CBIOS_CEA_EXTENDED_BLOCK_TAG; @@ -259,20 +263,31 @@ typedef struct _CBIOS_HDMI_VSDB_EXTENTION CBIOS_U32 HDMI3DFormatCount; }CBIOS_HDMI_VSDB_EXTENTION, *PCBIOS_HDMI_VSDB_EXTENTION; -typedef struct _CBIOS_HF_HDMI_VSDB_EXTENTION +typedef struct _CBIOS_HF_SCDS_DATA { struct { - CBIOS_U8 VSDBLength :5; - CBIOS_U8 VSDBTag :3; + CBIOS_U8 Length :5; + CBIOS_U8 CTATag :3; }Tag; - struct + + union { - CBIOS_U8 IEEEOUIByte0; - CBIOS_U8 IEEEOUIByte1; - CBIOS_U8 IEEEOUIByte2; + struct // for HF-VSDB + { + CBIOS_U8 IEEEOUIByte0; + CBIOS_U8 IEEEOUIByte1; + CBIOS_U8 IEEEOUIByte2; + }HFVSDBOUI; - }HFVSDBOUI; + struct // for HF-SCDB + { + CBIOS_U8 ExtTagCode; + CBIOS_U16 Reserved; + }; + }; + + // Sink Capability Data Structure (SCDS) CBIOS_U8 Version; CBIOS_U16 MaxTMDSCharacterRate; union @@ -294,8 +309,7 @@ typedef struct _CBIOS_HF_HDMI_VSDB_EXTENTION }; CBIOS_U16 SupportCaps; }; -}CBIOS_HF_HDMI_VSDB_EXTENTION, *PCBIOS_HF_HDMI_VSDB_EXTENTION; - +}CBIOS_HF_SCDS_DATA, *PCBIOS_HF_SCDS_DATA; typedef struct _CBIOS_COLORIMETRY_DATA { @@ -473,7 +487,7 @@ typedef struct _CBIOS_MONITOR_MISC_ATTRIB CBIOS_U8 RevisionNumber; CBIOS_U8 OffsetOfDetailedTimingBlock; CBIOS_HDMI_VSDB_EXTENTION VSDBData; - CBIOS_HF_HDMI_VSDB_EXTENTION HFVSDBData; + CBIOS_HF_SCDS_DATA HFSCDSData; CBIOS_CEA_SVD_DATA SVDData[CBIOS_EDIDMAXBLOCKCOUNT - 1]; CBIOS_CEA_EXTENED_BLOCK ExtDataBlock[MAX_CEA_EXT_DATA_BLOCK_NUM]; CBIOS_BOOL bStereoViewSupport; // stereo Viewing Support for row-interlace @@ -491,6 +505,8 @@ typedef struct _CBIOS_MONITOR_MISC_ATTRIB CBIOS_SVR_DESC ShortVideoRef[MAX_SVR_LEN]; }CBIOS_MONITOR_MISC_ATTRIB, *PCBIOS_MONITOR_MISC_ATTRIB; +#define CBIOS_DTDTIMING_BLOCK_CNT (CBIOS_DTDTIMINGCOUNTS*2) + typedef struct _CBIOS_EDID_STRUCTURE_DATA { CBIOS_U8 Version; CBIOS_MODE_INFO EstTimings[CBIOS_ESTABLISHMODECOUNT]; @@ -499,12 +515,13 @@ typedef struct _CBIOS_EDID_STRUCTURE_DATA { CBIOS_MONITOR_MISC_ATTRIB Attribute; CBIOS_HDMI_FORMAT_DESCRIPTOR HDMIFormat[CBIOS_HDMIFORMATCOUNTS]; CBIOS_HDMI_AUDIO_INFO HDMIAudioFormat[CBIOS_HDMI_AUDIO_FORMAT_COUNTS]; - CBIOS_MODE_INFO_EXT DTDTimings[CBIOS_DTDTIMINGCOUNTS*2]; //may meet two CEA data block(edid has 4 block) + CBIOS_MODE_INFO_EXT DTDTimings[CBIOS_DTDTIMING_BLOCK_CNT]; //may meet two CEA data block(edid has 4 block) CBIOS_U32 TotalModeNum; // total number of modes that supported in EDID CBIOS_U32 TotalHDMIAudioFormatNum; // total number of hdmi audio formats that supported in EDID CBIOS_MODE_INFO_EXT DisplayID_TYPE1_Timings[CBIOS_DISPLAYID_TYPE1_MODECOUNT]; } CBIOS_EDID_STRUCTURE_DATA, *PCBIOS_EDID_STRUCTURE_DATA; +CBIOS_U32 cbEDIDModule_GetExtBlockNum(CBIOS_U8 *pEDID); CBIOS_U32 cbEDIDModule_GetMonitorAttrib(CBIOS_U8 *pEDID, PCBIOS_MONITOR_MISC_ATTRIB pMonitorAttrib, CBIOS_U32 TotalBlocks); CBIOS_STATUS cbEDIDModule_GetMonitor3DCaps(PCBIOS_EDID_STRUCTURE_DATA pEDIDStruct, PCBIOS_MONITOR_3D_CAPABILITY_PARA p3DCapability, diff --git a/drivers/gpu/drm/arise/cbios/Util/CBiosUtil.c b/drivers/gpu/drm/arise/cbios/Util/CBiosUtil.c index 9f30126b6c07d..3ae1a26911e3a 100644 --- a/drivers/gpu/drm/arise/cbios/Util/CBiosUtil.c +++ b/drivers/gpu/drm/arise/cbios/Util/CBiosUtil.c @@ -41,26 +41,25 @@ static CBIOS_U32 cbGetVsyncWidth(PCBIOS_EXTENSION_COMMON pcbe, CBIOS_U32 XRes, C return ulRet; } ulTemp = XRes*100/YRes; - if((ulTemp<134)&&(ulTemp>132)) + switch(ulTemp) { - ulRet = 4; - } - else if((ulTemp<178)&&(ulTemp>176)) - { - ulRet = 5; - } - else if((ulTemp<161)&&(ulTemp>159)) - { - ulRet = 6; - } - else if((ulTemp<167)&&(ulTemp>165)) - { - ulRet = 7; - } - else - { - ulRet = 10; + case 133: + ulRet = 4; + break; + case 177: + ulRet = 5; + break; + case 160: + ulRet = 6; + break; + case 166: + ulRet = 7; + break; + default: + ulRet = 10; + break; } + return ulRet; } diff --git a/drivers/gpu/drm/arise/cbios/cbios.mk b/drivers/gpu/drm/arise/cbios/cbios.mk index c464f777b68c5..0756379d1f1c7 100644 --- a/drivers/gpu/drm/arise/cbios/cbios.mk +++ b/drivers/gpu/drm/arise/cbios/cbios.mk @@ -55,10 +55,9 @@ cbios-objs := \ Hw/HwBlock/CBiosDIU_DVO.o \ Hw/HwBlock/CBiosDIU_VIP.o \ Hw/HwBlock/CBiosDIU_CSC.o \ - Hw/HwBlock/CBiosDIU_VIP.o \ Hw/HwBlock/CBiosPHY_DP.o \ Hw/Arise/CBios_Arise.o \ - Hw/Arise/CBiosVCP_Arise.o + Hw/Arise/CBiosVCP_Arise.o $(DRIVER_NAME)-objs += $(addprefix cbios/, $(cbios-objs)) diff --git a/drivers/gpu/drm/arise/core/Makefile b/drivers/gpu/drm/arise/core/Makefile index 821a86b70c9c1..1be248536a32d 100644 --- a/drivers/gpu/drm/arise/core/Makefile +++ b/drivers/gpu/drm/arise/core/Makefile @@ -6,7 +6,6 @@ ccflags-y += \ -I${GFGPU_FULL_PATH}/core/vidmm \ -I${GFGPU_FULL_PATH}/core/vidsch \ -I${GFGPU_FULL_PATH}/core/util \ - -I${GFGPU_FULL_PATH}/core/isr \ -I${GFGPU_FULL_PATH}/core/perfevent \ -I${GFGPU_FULL_PATH}/shared diff --git a/drivers/gpu/drm/arise/core/context/context.c b/drivers/gpu/drm/arise/core/context/context.c index bdabb162dae74..f229c20700d50 100644 --- a/drivers/gpu/drm/arise/core/context/context.c +++ b/drivers/gpu/drm/arise/core/context/context.c @@ -217,13 +217,6 @@ gpu_context_t* cm_create_context(gpu_device_t *device, create_context_t *create_ context->engine_index = cm_get_hw_ringbuffer_index(device->adapter, create_context->node_ordinal); context->is_kernel = is_kernel; - context->context_ctrl = 1; - if(context->context_ctrl) - { - context->context_sema = gf_create_sema(CONTEXT_TASK_QUEUE_LENGTH); - } - - cm_device_lock(device); list_add(&context->list_node, &device->context_list); @@ -280,7 +273,7 @@ void cm_wait_context_idle(gpu_context_t *context) { vidsch_dump(NULL,adapter); } - gf_assert(idle, "context not idle"); + gf_warning("wait context not idle\n"); } } @@ -290,11 +283,6 @@ void cm_destroy_context(gpu_device_t *device, gpu_context_t *context) cm_wait_context_idle(context); remove_handle(&device->adapter->hdl_mgr, context->handle); - if(context->context_ctrl) - { - gf_destroy_sema(context->context_sema); - } - cm_device_lock(device); diff --git a/drivers/gpu/drm/arise/core/context/context.h b/drivers/gpu/drm/arise/core/context/context.h index fc98151aec4c6..66be62b7fa95b 100644 --- a/drivers/gpu/drm/arise/core/context/context.h +++ b/drivers/gpu/drm/arise/core/context/context.h @@ -27,12 +27,12 @@ #include "util.h" #include "list.h" + #define USER_MODE_DMA_SIZE 64 * 1024 /* Set to 64KB to pass MaxContexts test */ #define SYNCOBJECTLIST_SIZE 256 #define ALLOCATIONLIST_SIZE (USER_MODE_DMA_SIZE / 64) * 4 /* Set to 2KB for every 64KB of command buffer to pass MaxContexts test */ #define PATCHLOCATIONLIST_SIZE (USER_MODE_DMA_SIZE / 64) * 16 /* Set to 2KB for every 64KB of command buffer to pass MaxContexts test */ -#define MAX_SYNC_OBJECT_SIZE_PER_DEVICE 512*4 -#define CONTEXT_TASK_QUEUE_LENGTH 8 +#define MAX_SYNC_OBJECT_SIZE_PER_DEVICE 64 * 1024 #ifdef GFX_ONLY_FPGA #define CM_DESTROY_TIMEOUT 20000 @@ -84,8 +84,6 @@ typedef struct gpu_context unsigned long long wait_delta_check_end; int is_kernel; - unsigned int context_ctrl; - struct os_sema *context_sema; struct os_atomic *ref_cnt; //dma_ref_cnt diff --git a/drivers/gpu/drm/arise/core/e3k/global/global_e3k.c b/drivers/gpu/drm/arise/core/e3k/global/global_e3k.c index e8efb40bb50ca..e021e43ac89ee 100644 --- a/drivers/gpu/drm/arise/core/e3k/global/global_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/global/global_e3k.c @@ -35,3 +35,29 @@ void glb_init_power_caps(adapter_t *adapter) { gf_warning("%s(): is blank, maybe implemented in other function()\n", util_remove_name_suffix(__func__)); } + +int glb_detect_power_switch(adapter_t *adapter) +{ + int enabled = FALSE; + unsigned int value, tmp, retry; + + gf_write32(adapter->mmio + 0x8E080, 0x1); + + retry = 100; + while (retry > 0) + { + tmp = gf_read32(adapter->mmio + 0x8E000); + value = (tmp & 0x00ff0000) >> 16; + if (value == 0x22) + { + enabled = TRUE; + break; + } + + retry--; + gf_udelay(1000); + } + + return enabled; +} + diff --git a/drivers/gpu/drm/arise/core/e3k/include/chip_include_e3k.h b/drivers/gpu/drm/arise/core/e3k/include/chip_include_e3k.h index 0112774b95846..3e3913a221811 100644 --- a/drivers/gpu/drm/arise/core/e3k/include/chip_include_e3k.h +++ b/drivers/gpu/drm/arise/core/e3k/include/chip_include_e3k.h @@ -76,12 +76,12 @@ typedef enum // Above are stored in context buffer //Slot used by video - HWM_SYNC_VCP0_FE_SLOT = 11, - HWM_SYNC_VCP0_BE_SLOT = 12, - HWM_SYNC_VCP1_FE_SLOT = 13, - HWM_SYNC_VCP1_BE_SLOT = 14, - HWM_SYNC_VPP_SLOT = 15, - + HWM_SYNC_VCP0_FE_SLOT = 16, + HWM_SYNC_VCP0_BE_SLOT = 17, + HWM_SYNC_VCP1_FE_SLOT = 18, + HWM_SYNC_VCP1_BE_SLOT = 19, + HWM_SYNC_VPP_SLOT = 20, + HWM_SYNC_VCP_BANDWIDTH = 21, } HWM_SYNC_SLOT_E3K; diff --git a/drivers/gpu/drm/arise/core/e3k/include/mm_e3k.h b/drivers/gpu/drm/arise/core/e3k/include/mm_e3k.h index 4fbf6e38fe498..3d7476d671ae0 100644 --- a/drivers/gpu/drm/arise/core/e3k/include/mm_e3k.h +++ b/drivers/gpu/drm/arise/core/e3k/include/mm_e3k.h @@ -472,12 +472,12 @@ static inline unsigned int NearestLog2(unsigned int val) */ typedef enum _SEGMENT_ID_E3K { - SEGMENT_ID_INVALID_E3K = 0x0, - SEGMENT_ID_LOCAL_E3K = 0x1, - SEGMENT_ID_GART_UNSNOOPABLE_E3K = 0x2, - SEGMENT_ID_GART_SNOOPABLE_E3K = 0x3, - SEGMENT_ID_LOCAL_CPU_UNVISIABLE_E3K = 0x4, - SEGMENT_ID_LOCAL_CPU_UNVISIABLE_E3K_1 = 0x5, + SEGMENT_ID_INVALID_E3K = 0x0, //invalid + SEGMENT_ID_LOCAL_E3K = 0x1, //local low /local cpu visible/pcie bar memory range + SEGMENT_ID_GART_UNSNOOPABLE_E3K = 0x2, //pcie unsnoop + SEGMENT_ID_GART_SNOOPABLE_E3K = 0x3, //pcie snoonp + SEGMENT_ID_LOCAL_CPU_UNVISIABLE_E3K = 0x4, //local video/local cpu unvisible and inside 4G + SEGMENT_ID_LOCAL_CPU_UNVISIABLE_E3K_1 = 0x5, //local high/local cpu unvisible and outside 4G SEGMENT_ID_SECURE_RANGE_E3K = 0x6, SEGMENT_ID_SECURE_RANGE_E3K_1 = 0x7, SEGMENT_ID_MAX_E3K = 0x8, diff --git a/drivers/gpu/drm/arise/core/e3k/include/stm_context_e3k.h b/drivers/gpu/drm/arise/core/e3k/include/stm_context_e3k.h index cdb44fecbeb0b..76ada22b2cc20 100644 --- a/drivers/gpu/drm/arise/core/e3k/include/stm_context_e3k.h +++ b/drivers/gpu/drm/arise/core/e3k/include/stm_context_e3k.h @@ -56,7 +56,7 @@ typedef struct CONTEXT_REGISTER_BUFFER_E3K #define MAX_HW_SLICE_NUM 8 #define SLICE_ILA_COUNTERS_ALIGN_SIZE 32 -#define FENCE_COUNTER_NUM 16 +#define FENCE_COUNTER_NUM 8 #define HW_MAX_GPC_NUM_E3K 3 diff --git a/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_allocate_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_allocate_e3k.c index 809670aebebc0..0d420ef0553ff 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_allocate_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_allocate_e3k.c @@ -544,7 +544,6 @@ static void vidmmi_calc_allocation_pitch_e3k(vidmm_allocation_t *allocation) unsigned int TileWidth, TileHeight; unsigned int UnitWidth, UnitHeight; unsigned int P2Width0, P2Height0; - unsigned int UnitSize; unsigned int Pitch; unsigned int WidthAligned; unsigned int HeightAligned; @@ -552,7 +551,6 @@ static void vidmmi_calc_allocation_pitch_e3k(vidmm_allocation_t *allocation) BitCount = allocation->bit_count; TileWidth = calcTileWidth_e3k(BitCount); TileHeight = calcTileHeight_e3k(BitCount); - UnitSize = UNIT_SIZE_E3K; UnitWidth = calcUnitWidth_e3k(BitCount); UnitHeight = calcUnitHeight_e3k(BitCount); diff --git a/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_e3k.c index 0ce285ff5d4fd..fdbf1d9fbb044 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidmm/vidmm_e3k.c @@ -22,7 +22,6 @@ * */ #include "gf_adapter.h" -#include "gf_def.h" #include "vidmm.h" #include "vidsch.h" #include "vidmmi.h" diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_blt_e3k.h b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_blt_e3k.h index 369e781390ca7..493b93df9f261 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_blt_e3k.h +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_blt_e3k.h @@ -25,7 +25,6 @@ #define __VIDSCH_3DBLT_E3K_H #include "vidmm.h" -#include "context.h" #include "chip_include_e3k.h" #include "util.h" diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_compatible_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_compatible_e3k.c index 41fce4886041e..e5eb3bc71b314 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_compatible_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_compatible_e3k.c @@ -29,7 +29,6 @@ #include "vidsch_debug_hang_e3k.h" #include "vidsch_engine_e3k.h" #include "mm_e3k.h" -#include "context.h" #include "global.h" typedef enum dump_data_type{ diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_e3k.c index fa007d5ef4af8..5946d71833d44 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_debug_hang_e3k.c @@ -29,7 +29,6 @@ #include "vidsch_debug_hang_e3k.h" #include "vidsch_engine_e3k.h" #include "mm_e3k.h" -#include "context.h" #include "global.h" #include "bit_op.h" diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.c index a5ae4bf256d35..b2b3e34bd7981 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.c @@ -134,6 +134,394 @@ int vidsch_power_clock_on_off_vcp(vidsch_mgr_t *sch_mgr, unsigned int off) return S_OK; } +int vidsch_engine_power_state_e3k(adapter_t *adapter) +{ + unsigned int power_state; + unsigned char overclock = 0; + + if ((adapter->usage_vpp > 90) || (adapter->usage_vcp > 90) || (adapter->usage_3d > 90)) + overclock = 1; + + power_state = adapter->power_state; + + if (adapter->usage_vcp || adapter->usage_vpp) + power_state = power_state > ENG_POWER_STATE_E1 ? ENG_POWER_STATE_E1 : power_state; + + if (adapter->disp_state == 3) + power_state = power_state > ENG_POWER_STATE_E3 ? ENG_POWER_STATE_E3 : power_state; + + if (overclock) + { + if (power_state > ENG_POWER_STATE_E0) + power_state -= 1; + } + else + { + if (power_state == ENG_POWER_STATE_E0) + { + if ((adapter->usage_vpp < 45) && (adapter->usage_vcp < 45) && (adapter->usage_3d < 45)) + power_state = ENG_POWER_STATE_E1; + } + else if (power_state == ENG_POWER_STATE_E1) + { + if (!adapter->usage_vpp && !adapter->usage_vcp) + power_state = ENG_POWER_STATE_E2; + } + else if (power_state == ENG_POWER_STATE_E2) + { + if (adapter->usage_3d < 20) + power_state = ENG_POWER_STATE_E3; + } + else if (power_state == ENG_POWER_STATE_E3) + { + if (adapter->disp_state == 2) + power_state = ENG_POWER_STATE_E4; + else if (adapter->disp_state == 1) + power_state = ENG_POWER_STATE_E5; + } + else if (power_state == ENG_POWER_STATE_E4) + { + if (adapter->disp_state == 3) + power_state = ENG_POWER_STATE_E3; + else if (adapter->disp_state == 1) + power_state = ENG_POWER_STATE_E5; + } + else if (power_state == ENG_POWER_STATE_E5) + { + if (adapter->disp_state == 3) + power_state = ENG_POWER_STATE_E3; + else if (adapter->disp_state == 2) + power_state = ENG_POWER_STATE_E4; + } + else + { + power_state = ENG_POWER_STATE_E0; + } + } + + return power_state; +} + +static int vidsch_engine_power_switch_wait(adapter_t *adapter) +{ + unsigned int ret = -1, value, tmp, retry; + + retry = 100; + while (retry > 0) + { + tmp = gf_read32(adapter->mmio + 0x8E000); + value = (tmp & 0x00ff0000) >> 16; + if (value == 0x22 || !value) + { + ret = 0; + break; + } + else if (value == 0x33) + { + break; + } + + retry--; + gf_udelay(1000); + } + + return ret; +} + +int vidsch_engine_power_state_check_e3k(adapter_t *adapter, int *switching) +{ + unsigned int power_state, value, tmp; + static unsigned int max_fail = 10; + unsigned long long timestamp = 0ll; + + tmp = gf_read32(adapter->mmio + 0x8E000); + + value = (tmp & 0x00ff0000) >> 16; + + if (switching) + { + *switching = !((value == 0x00) || (value == 0x22)); + + if (*switching) + return -1; + } + + power_state = (tmp & 0xff000000) >> 24; + + switch (power_state) + { + case 0x00: + power_state = ENG_POWER_STATE_E0; + break; + + case 0x10: + power_state = ENG_POWER_STATE_E1; + break; + + case 0x12: + power_state = ENG_POWER_STATE_E2; + break; + + case 0x22: + power_state = ENG_POWER_STATE_E3; + break; + + case 0x24: + power_state = ENG_POWER_STATE_E4; + break; + + case 0x44: + power_state = ENG_POWER_STATE_E5; + break; + + default: + power_state = ENG_POWER_STATE_NONE; + break; + } + + if (power_state != adapter->power_state) + { + gf_error("power state check error last: E%u current: E%u\n", adapter->power_state, power_state); + + if (max_fail > 0) + { + max_fail--; + } + else + { + vidsch_engine_power_switch_wait(adapter); + + tmp = gf_read32(adapter->mmio + 0x8E000); + tmp &= 0xff00ff00; + tmp |= 0x00110000; + + gf_write32(adapter->mmio + 0x8E000, tmp); + gf_write32(adapter->mmio + 0x8E080, 0x1); + + gf_get_nsecs(×tamp); + timestamp = gf_do_div(timestamp, 1000000); + + adapter->ctl_flags.boost = FALSE; + adapter->power_state = ENG_POWER_STATE_E0; + adapter->power_holding_time = timestamp + 10 * 1000; + vidsch_engine_power_switch_wait(adapter); + + max_fail = 10; + + gf_error("too many power state check fail, disable power state switch.\n"); + } + + return -1; + } + + return 0; +} + +void vidsch_power_switch_e3k(adapter_t *adapter, unsigned int power_state, unsigned int holding_ms, unsigned int force, unsigned int sync_wait) +{ + unsigned long long timestamp = 0ll; + unsigned int switching = 0, index = 0, tmp = 0, ret; + unsigned char value; + vidschedule_t *schedule = adapter->schedule; + unsigned long flags = 0; + + if (!adapter->ctl_flags.boost || !adapter->pwm_level.EnablePowerSwitch) + return; + + gf_get_nsecs(×tamp); + timestamp = gf_do_div(timestamp, 1000000); + + flags = gf_spin_lock_irqsave(schedule->power_status_lock); + + vidsch_engine_power_state_check_e3k(adapter, &switching); + + if (!force) + { + if (adapter->power_state == power_state) + { + if (timestamp + holding_ms > adapter->power_holding_time) + adapter->power_holding_time = timestamp + holding_ms; + + goto exit_unlock; + } + + if ((adapter->power_state < power_state) && (timestamp < adapter->power_holding_time)) + goto exit_unlock; + } + + if (sync_wait && switching) + vidsch_engine_power_switch_wait(adapter); + else if (!sync_wait && switching) + goto exit_unlock; + + switch (power_state) + { + case ENG_POWER_STATE_E0: + value = 0x00; + break; + + case ENG_POWER_STATE_E1: + value = 0x10; + break; + + case ENG_POWER_STATE_E2: + value = 0x12; + break; + + case ENG_POWER_STATE_E3: + value = 0x22; + break; + + case ENG_POWER_STATE_E4: + value = 0x24; + break; + + case ENG_POWER_STATE_E5: + value = 0x44; + break; + + default: + value = 0x00; + power_state = ENG_POWER_STATE_E0; + break; + } + + tmp = gf_read32(adapter->mmio + 0x8E000); + tmp &= 0xff00ff00; + tmp |= 0x00110000; + tmp |= value; + + gf_write32(adapter->mmio + 0x8E000, tmp); + gf_write32(adapter->mmio + 0x8E080, 0x1); + + gf_get_nsecs(×tamp); + timestamp = gf_do_div(timestamp, 1000000); + + if (timestamp + holding_ms > adapter->power_holding_time) + adapter->power_holding_time = timestamp + holding_ms; + + adapter->power_state = power_state; + gf_spin_unlock_irqrestore(schedule->power_status_lock, flags); + + ret = vidsch_engine_power_switch_wait(adapter); + if (ret) + gf_error("switch power state timeout\n\n"); + + gf_get_nsecs(×tamp); + timestamp = gf_do_div(timestamp, 1000000); + + gf_debug("switch to E%u done, ts:0x%llu\n", power_state, timestamp); + + return; + +exit_unlock: + + gf_spin_unlock_irqrestore(schedule->power_status_lock, flags); + return; +} + +static int vidsch_engine_boost_allow(adapter_t *adapter, unsigned int power_state) +{ + unsigned long long timestamp = 0ll; + vidschedule_t *schedule = adapter->schedule; + unsigned int allow = FALSE; + + if (!adapter->ctl_flags.boost || !adapter->pwm_level.EnablePowerSwitch) + return allow; + + gf_get_nsecs(×tamp); + timestamp = gf_do_div(timestamp, 1000000); + + if (adapter->power_state == power_state) + return FALSE; + + if (adapter->power_state > power_state) + return TRUE; + + if (timestamp > adapter->power_holding_time) + allow = TRUE; + + return allow; +} + +void vidsch_boost_e3k(adapter_t *adapter, unsigned int power_state, unsigned int holding_ms, unsigned int force) +{ + vidschedule_t *schedule = adapter->schedule; + vidsch_mgr_t *sch_mgr; + unsigned long long timestamp = 0ll; + unsigned long flags = 0; + unsigned int i, sync_wait = FALSE, allow = FALSE; + + if (!adapter->ctl_flags.boost || !adapter->pwm_level.EnablePowerSwitch) + return; + + if (power_state == ENG_POWER_STATE_AUTO) + goto auto_boost; + + flags = gf_spin_lock_irqsave(schedule->power_status_lock); + if (adapter->power_state > power_state) + { + gf_debug("try boost to E%u\n", power_state); + allow = TRUE; + sync_wait = TRUE; + gf_spin_unlock_irqrestore(schedule->power_status_lock, flags); + goto boost; + } + else if (adapter->power_state == power_state) + { + gf_get_nsecs(×tamp); + timestamp = gf_do_div(timestamp, 1000000); + if (timestamp + holding_ms > adapter->power_holding_time) + adapter->power_holding_time = timestamp + holding_ms; + } + else if (force) + { + allow = TRUE; + sync_wait = TRUE; + gf_spin_unlock_irqrestore(schedule->power_status_lock, flags); + goto boost; + } + + gf_spin_unlock_irqrestore(schedule->power_status_lock, flags); + +auto_boost: + power_state = vidsch_engine_power_state_e3k(adapter); + allow = vidsch_engine_boost_allow(adapter, power_state); + +boost: + if (!allow) + return; + + for (i = 0; i < adapter->active_engine_count; i++) + { + sch_mgr= adapter->sch_mgr[i]; + if (!sch_mgr) + continue; + + gf_mutex_lock(sch_mgr->engine_lock); + } + + for (i = 0; i < adapter->active_engine_count; i++) + { + sch_mgr= adapter->sch_mgr[i]; + if (!sch_mgr) + continue; + + vidsch_wait_fence_back(adapter, sch_mgr->engine_index, sch_mgr->last_send_fence_id); + } + + vidsch_power_switch_e3k(adapter, power_state, holding_ms, force, sync_wait); + + for (i = 0; i < adapter->active_engine_count; i++) + { + sch_mgr= adapter->sch_mgr[i]; + if (!sch_mgr) + continue; + + gf_mutex_unlock(sch_mgr->engine_lock); + } +} + void vidsch_power_tuning_e3k(adapter_t *adapter, unsigned int gfx_only) { vidschedule_t *schedule = adapter->schedule; diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.h b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.h index 9ef00fc872657..ef33d588f414b 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.h +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_dfs_e3k.h @@ -30,4 +30,6 @@ int vidsch_power_clock_on_off_e3k(vidsch_mgr_t *sch_mgr, unsigned int off); int vidsch_power_clock_on_off_vcp(vidsch_mgr_t *sch_mgr, unsigned int off); void vidsch_power_tuning_e3k(adapter_t *adapter, unsigned int gfx_only); +void vidsch_power_switch_e3k(adapter_t *adapter, unsigned int power_state, unsigned int holding_ms, unsigned int force, unsigned int sync_wait); +void vidsch_boost_e3k(adapter_t *adapter, unsigned int power_state, unsigned int holding_ms, unsigned int force); #endif diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_setup_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_setup_e3k.c index 7cd2caa45a58c..28f5d8aa9de2b 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_setup_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_setup_e3k.c @@ -639,6 +639,8 @@ int engine_gfx_low_init_e3k(adapter_t *adapter, vidsch_mgr_t *sch_mgr) return S_OK; } + sch_mgr->boost_level = ENG_POWER_STATE_E2; + start_align = ((local_reserved_start + HW_CONTEXT_E3K_ALIGN)& ~HW_CONTEXT_E3K_ALIGN) - local_reserved_start; current_low_offset += start_align; @@ -718,6 +720,8 @@ int engine_gfx_high_init_e3k(adapter_t *adapter, vidsch_mgr_t *sch_mgr) return S_OK; } + sch_mgr->boost_level = ENG_POWER_STATE_E2; + start_align = ((local_reserved_start + HW_CONTEXT_E3K_ALIGN)& ~HW_CONTEXT_E3K_ALIGN) - local_reserved_start; current_low_offset += start_align; @@ -751,7 +755,7 @@ int engine_vcp_init_e3k(adapter_t *adapter, vidsch_mgr_t *sch_mgr) gf_error("%s, out of mem.\n", util_remove_name_suffix(__func__)); gf_assert(0, "engine_vcp_init"); } - + sch_mgr->boost_level = ENG_POWER_STATE_E1; enginei_common_init_e3k(sch_mgr, engine, ¤t_pcie_offset, ¤t_low_offset); return S_OK; @@ -769,6 +773,7 @@ int engine_vpp_init_e3k(adapter_t *adapter, vidsch_mgr_t *sch_mgr) gf_assert(0, "engine_vpp_init"); } + sch_mgr->boost_level = ENG_POWER_STATE_E1; enginei_common_init_e3k(sch_mgr, engine, ¤t_pcie_offset, ¤t_low_offset); return S_OK; @@ -780,7 +785,8 @@ void engine_gfx_low_restore_e3k(vidsch_mgr_t *sch_mgr, unsigned int pm) engine_gfx_e3k_t *engine = sch_mgr->private_data; engine_share_e3k_t *share = engine->common.share; - vidschi_reset_adapter_e3k(sch_mgr->adapter); + if (!adapter->in_suspend_resume) + vidschi_reset_adapter_e3k(sch_mgr->adapter); //fix issue 18315, before system sleep, vcp clk is off, //when resume, open vcp clk before disable vcp decouple in vidmm_init_mem_settings_e3k diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_submit_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_submit_e3k.c index f22b15d5eaf4e..3f571697a1066 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_submit_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_engine_submit_e3k.c @@ -27,7 +27,6 @@ #include "vidsch_engine_e3k.h" #include "vidsch_debug_hang_e3k.h" #include "ring_buffer.h" -#include "context.h" #include "perfevent.h" reg_debug_mode_e3k debug_mode_e3k = {0}; @@ -304,7 +303,6 @@ static int enginei_submit_to_gfx_high_e3k(engine_e3k_t *engine, task_dma_t *task unsigned int * pRB1 = NULL; Cmd_Blk_Cmd_Csp_Indicator_Dword1 trigger_Dw = {0}; Csp_Opcodes_cmd cmd = {0}; - unsigned int dwRealRBSize; RINGBUFFER_COMMANDS_E3K *pRingBufferCommands = (RINGBUFFER_COMMANDS_E3K*)share->RingBufferCommands; RB_PREDEFINE_DMA *pPredefine = (RB_PREDEFINE_DMA*)share->begin_end_vma->virt_addr; CONTEXT_RESTORE_DMA_E3K *pRestoreDMA = &(pPredefine->RestoreDMA); @@ -520,14 +518,6 @@ static int enginei_submit_to_gfx_high_e3k(engine_e3k_t *engine, task_dma_t *task cmd.cmd_Tbr_Indicator.Indicator_Info = TBR_INDICATOR_INDICATOR_INFO_BEGIN; *pRB++ = cmd.uint; - dwRealRBSize = pRB - pRB0; - -// dwAlignRBSize = (((dwRealRBSize) + 15) & ~15); -// if (dwAlignRBSize != dwRbSize) -// { -// *pRB++ = SEND_SKIP_E3K(dwRbSize - dwRealRBSize); -// } - gf_memcpy(pRB1, pRB0, (dwRbSize<<2)); //util_dump_memory(pRB1, dwRbSize<<2, "high dma in rb"); diff --git a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_setup_e3k.c b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_setup_e3k.c index 6b9036a5fcc35..3728a69477c16 100644 --- a/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_setup_e3k.c +++ b/drivers/gpu/drm/arise/core/e3k/vidsch/vidsch_setup_e3k.c @@ -713,6 +713,7 @@ vidschedule_chip_func_t vidschedule_chip_func = .dump_info = vidsch_dump_info_e3k, .dump_debugbus = vidsch_dump_debugbus_e3k, .power_tuning = vidsch_power_tuning_e3k, + .boost = vidsch_boost_e3k, .get_set_reg = vidsch_get_set_reg_e3k, }; diff --git a/drivers/gpu/drm/arise/core/global/global.c b/drivers/gpu/drm/arise/core/global/global.c index 7e535a3a9dfee..de54c27c82664 100644 --- a/drivers/gpu/drm/arise/core/global/global.c +++ b/drivers/gpu/drm/arise/core/global/global.c @@ -27,6 +27,8 @@ void glb_init_chip_id(adapter_t *adapter, krnl_adapter_init_info_t *info) { + unsigned int enabled; + adapter->hw_caps.support_snooping = TRUE; adapter->pm_caps.pwm_mode = info->gf_pwm_mode; @@ -88,6 +90,8 @@ void glb_init_chip_id(adapter_t *adapter, krnl_adapter_init_info_t *info) adapter->chip_id = CHIP_ARISE1010; else if((adapter->bus_config.device_id & CHIP_MASK) == CHIP_MASK_ARISE10C0T) adapter->chip_id = CHIP_ARISE10C0T; + else if((adapter->bus_config.device_id & CHIP_MASK) == CHIP_MASK_ARISE10D0) + adapter->chip_id = CHIP_ARISE10C0T; else if((adapter->bus_config.device_id & CHIP_MASK) == CHIP_MASK_ARISE2030) adapter->chip_id = CHIP_ARISE2030; else if((adapter->bus_config.device_id & CHIP_MASK) == CHIP_MASK_ARISE2020) @@ -105,6 +109,7 @@ void glb_init_chip_id(adapter_t *adapter, krnl_adapter_init_info_t *info) { unsigned int cg_manual_mode = info->gf_pwm_mode & 0x1; unsigned int cg_auto_mode = (info->gf_pwm_mode >> 4) & 0x7; + unsigned int power_switch_mode = (info->gf_pwm_mode >> 8) & 0x1; if (adapter->chip_id < CHIP_ARISE2030) { @@ -115,6 +120,22 @@ void glb_init_chip_id(adapter_t *adapter, krnl_adapter_init_info_t *info) adapter->pm_caps.pwm_auto = cg_auto_mode; adapter->pwm_level.EnableClockGating = cg_auto_mode ? 0 : (cg_manual_mode ? 1 : 0); } + + if (power_switch_mode) + { + enabled = glb_detect_power_switch(adapter); + if (enabled) + { + adapter->ctl_flags.perf_event_enable = TRUE; + adapter->ctl_flags.hwq_event_enable = TRUE; + } + + adapter->pwm_level.EnablePowerSwitch = enabled; + } + else + { + adapter->pwm_level.EnablePowerSwitch = 0; + } } } @@ -123,6 +144,10 @@ void glb_init_chip_id(adapter_t *adapter, krnl_adapter_init_info_t *info) // qemu will set default subsystem id to PCI_SUBVENDOR_ID_REDHAT_QUMRANET:PCI_SUBDEVICE_ID_QEMU adapter->ctl_flags.run_on_qemu_device = adapter->bus_config.sub_sys_vendor_id == 0x1AF4 && adapter->bus_config.sub_sys_id == 0x1100; adapter->ctl_flags.hang_dump = info->gf_hang_dump; + adapter->ctl_flags.boost = TRUE; + + adapter->power_state = ENG_POWER_STATE_E0; + adapter->power_state_hold = FALSE; if(info->gf_hang_dump) { diff --git a/drivers/gpu/drm/arise/core/global/global.h b/drivers/gpu/drm/arise/core/global/global.h index c6e4d72b822e3..4994d1d5da2c8 100644 --- a/drivers/gpu/drm/arise/core/global/global.h +++ b/drivers/gpu/drm/arise/core/global/global.h @@ -32,4 +32,5 @@ extern void glb_init_chip_interface(adapter_t *adapter); extern void glb_fini_bus_config(adapter_t *adapter); extern void glb_init_power_caps(adapter_t *adapter); +extern int glb_detect_power_switch(adapter_t *adapter); #endif diff --git a/drivers/gpu/drm/arise/core/include/gf_adapter.h b/drivers/gpu/drm/arise/core/include/gf_adapter.h index c90ed377935b4..40ca52423d4e0 100644 --- a/drivers/gpu/drm/arise/core/include/gf_adapter.h +++ b/drivers/gpu/drm/arise/core/include/gf_adapter.h @@ -229,17 +229,34 @@ typedef struct ctl_flags unsigned int vesa_tempbuffer_enable :1; unsigned int hwq_event_enable :1; unsigned int run_on_qemu_device :1; - unsigned int reserved :14; + unsigned int boost :1; + unsigned int reserved :13; }ctl_flags_t; #define PATCH_E2UMA_FENCE_ID_LOST (1 << 0) #define PATCH_FENCE_INTERRUPT_LOST (1 << 1) #define PATCH_E2UMA_HW66 (1<<2) +#define ENG_POWER_MIN_HOLDING_TIME_MS 300 + +enum engine_power_state +{ + ENG_POWER_STATE_E0 = 0, // ECLK Default(650Mhz) + ENG_POWER_STATE_E1, // ECLK 250Mhz + ENG_POWER_STATE_E2, // ECLK 250Mhz + VCLK OFF + ENG_POWER_STATE_E3, // ECLK 150Mhz + VCLK OFF + ENG_POWER_STATE_E4, // ECLK 150Mhz + VCLK OFF + VCORE + LOW VCC (short idle) + ENG_POWER_STATE_E5, // ECLK 50Mhz + VCLK OFF + VCORE + LOW VCC (long idle) + ENG_POWER_STATE_HOLD, + ENG_POWER_STATE_AUTO, + ENG_POWER_STATE_NONE +}; + typedef struct { int EnableClockGating; int EnablePowerGating; + int EnablePowerSwitch; int DonotInitPowerSet; }pwm_level_t; @@ -391,6 +408,10 @@ typedef struct unsigned long long hw_hang_max_timeout_ns; unsigned long long hw_hang_fast_timeout_ns; unsigned long long sync_max_server_wait_time_ns; + unsigned int power_state; + unsigned int disp_state; + unsigned long long power_holding_time; + unsigned int power_state_hold; } adapter_t; #endif diff --git a/drivers/gpu/drm/arise/core/include/gf_chip_id.h b/drivers/gpu/drm/arise/core/include/gf_chip_id.h index 7f45e40af3f09..2847f6586bc85 100644 --- a/drivers/gpu/drm/arise/core/include/gf_chip_id.h +++ b/drivers/gpu/drm/arise/core/include/gf_chip_id.h @@ -40,6 +40,7 @@ #define PCI_ID_ARISE1010 0x3D04 //ARISE1010 #define PCI_ID_ARISE2030 0x3D07 //ARISE2030 #define PCI_ID_ARISE2020 0x3D08 //ARISE2020 +#define PCI_ID_ARISE10D0 0x3D0E //ARISE10D0 #define PCI_ID_GENERIC_EXCALIBUR PCI_ID_EXC2UMA #define PCI_ID_GENERIC_ELITE PCI_ID_ELT @@ -72,6 +73,7 @@ #define CHIP_MASK_ARISE10C0T (PCI_ID_ARISE10C0T & CHIP_MASK) #define CHIP_MASK_ARISE2030 (PCI_ID_ARISE2030 & CHIP_MASK) #define CHIP_MASK_ARISE2020 (PCI_ID_ARISE2020 & CHIP_MASK) +#define CHIP_MASK_ARISE10D0 (PCI_ID_ARISE10D0 & CHIP_MASK) enum { diff --git a/drivers/gpu/drm/arise/core/include/kernel_import.h b/drivers/gpu/drm/arise/core/include/kernel_import.h index 42d24a579ae69..e72af52591799 100644 --- a/drivers/gpu/drm/arise/core/include/kernel_import.h +++ b/drivers/gpu/drm/arise/core/include/kernel_import.h @@ -249,6 +249,10 @@ typedef struct gf_drm_callback struct { unsigned int (*get_from_handle)(void *file, unsigned int handle); } gem; + + struct { + void (*check_touch_primary) (void* driver, void *bo); + } kms; } gf_drm_callback_t; struct os_printer; diff --git a/drivers/gpu/drm/arise/core/include/kernel_interface.h b/drivers/gpu/drm/arise/core/include/kernel_interface.h index 6b57cc727546a..dad21e705e8a6 100644 --- a/drivers/gpu/drm/arise/core/include/kernel_interface.h +++ b/drivers/gpu/drm/arise/core/include/kernel_interface.h @@ -170,6 +170,9 @@ typedef struct int (*hwq_process_vsync_event)(void *data, unsigned long long time); void (*task_timeout_update)(void* data, unsigned long long *value, int update); void (*reset_dvfs_power_flag)(void* data); + void (*disp_state_update)(void* data, unsigned int state); + int (*get_power_state)(void* data, unsigned int *state); + int (*set_power_state)(void* data, unsigned int state, unsigned int holding_ms, unsigned int force, unsigned int lcok, unsigned int unlock); } core_interface_t; extern core_interface_t *gf_core_interface; diff --git a/drivers/gpu/drm/arise/core/kernel_interface.c b/drivers/gpu/drm/arise/core/kernel_interface.c index d10f095f858f4..d6e72997259d8 100644 --- a/drivers/gpu/drm/arise/core/kernel_interface.c +++ b/drivers/gpu/drm/arise/core/kernel_interface.c @@ -52,6 +52,7 @@ static void* krnl_pre_init_adapter(void *pdev, krnl_adapter_init_info_t *info, k { adapter_t *adapter = NULL; platform_caps_t caps = {0}; + unsigned int enabled = FALSE; gf = import; @@ -124,7 +125,7 @@ static void krnl_init_adapter(void* adp, int reserved_vmem, void *disp_info) gf_register_trace_events(); - arise_perf_event_init(adapter); + perf_event_init(adapter); gf_hwq_event_init(adapter); @@ -143,8 +144,8 @@ static void krnl_init_adapter(void* adp, int reserved_vmem, void *disp_info) adapter->hw_caps.page_64k_enable, adapter->ctl_flags.paging_enable, adapter->pwm_level.EnableClockGating, adapter->hw_caps.dfs_enable); - gf_info("power caps: ClockGating:%d, PowerGating:%d\n", - adapter->pwm_level.EnableClockGating, adapter->pwm_level.EnablePowerGating); + gf_info("power caps: ClockGating:%d, PowerGating:%d PowerSwitch:%d\n", + adapter->pwm_level.EnableClockGating, adapter->pwm_level.EnablePowerGating, adapter->pwm_level.EnablePowerSwitch); gf_info("Ctrl: Recovery:%d, WK-thread:%d, Hang-Dump:%d, RunOnQT:%d, PwmMode:0x%x, NonsnoopEnable:%d\n", adapter->ctl_flags.recovery_enable, adapter->ctl_flags.worker_thread_enable, @@ -1330,6 +1331,57 @@ static void krnl_reset_dvfs_power_flag(void* data) vidsch_dvfs_power_flag_reset(adapter); } +static void krnl_disp_state_update(void *data, unsigned int state) +{ + adapter_t *adapter = data; + + adapter->disp_state = state; +} + +static int krnl_get_power_state(void *data, unsigned int *state) +{ + adapter_t *adapter = data; + + if (!adapter->pwm_level.EnablePowerSwitch) + return -1; + + if (state) + *state = adapter->power_state; + + return 0; +} + +static int krnl_set_power_state(void *data, unsigned int state, unsigned int holding_ms, unsigned int force, unsigned int lock, unsigned int unlock) +{ + adapter_t *adapter = data; + + if (!adapter->pwm_level.EnablePowerSwitch) + return -1; + + if (state == ENG_POWER_STATE_HOLD) + adapter->power_state_hold = !adapter->power_state_hold; + + if (adapter->power_state_hold) + return 0; + + if (state >= ENG_POWER_STATE_AUTO) + { + state = ENG_POWER_STATE_AUTO; + lock = FALSE; + unlock = TRUE; + } + + if (lock || unlock) + adapter->ctl_flags.boost = TRUE; + + vidsch_set_power_state(adapter, state, holding_ms, force); + + if (lock) + adapter->ctl_flags.boost = FALSE; + + return 0; +} + static core_interface_t gfe3k_gpu_core = { #define INTERFACE(item) .item = krnl_##item INTERFACE(pre_init_adapter), @@ -1390,6 +1442,9 @@ static core_interface_t gfe3k_gpu_core = { INTERFACE(hwq_process_vsync_event), INTERFACE(task_timeout_update), INTERFACE(reset_dvfs_power_flag), + INTERFACE(disp_state_update), + INTERFACE(get_power_state), + INTERFACE(set_power_state), #undef INTERFACE }; diff --git a/drivers/gpu/drm/arise/core/perfevent/perfevent.c b/drivers/gpu/drm/arise/core/perfevent/perfevent.c index b4f351b18021d..e77cca0a688e8 100644 --- a/drivers/gpu/drm/arise/core/perfevent/perfevent.c +++ b/drivers/gpu/drm/arise/core/perfevent/perfevent.c @@ -22,7 +22,6 @@ * */ #include "gf_adapter.h" -#include "gf_def.h" #include "perfeventi.h" #include "perfevent.h" @@ -38,7 +37,7 @@ -int arise_perf_event_init(adapter_t *adapter) +int perf_event_init(adapter_t *adapter) { perf_event_mgr_t *perf_event_mgr; int ret = 0; @@ -402,7 +401,6 @@ int perf_event_get_miu_event(adapter_t *adapter, gf_get_miu_dump_perf_event_t *g perf_event_mgr_t *perf_event_mgr = adapter->perf_event_mgr; perf_event_node *event_node = NULL; perf_event_node *event_node_next = NULL; - gf_perf_event_header_t *perf_event = NULL; int event_fill_num = 0; char *dst_buf = get_perf_event->event_buffer; @@ -441,8 +439,6 @@ int perf_event_get_miu_event(adapter_t *adapter, gf_get_miu_dump_perf_event_t *g gf_copy_to_user(dst_buf, &event_node->perf_event, event_node->perf_event.size); dst_buf += event_node->perf_event.size; - perf_event = &event_node->perf_event; - list_del(&event_node->list_node); gf_free(event_node); @@ -483,7 +479,6 @@ int perf_event_get_event(adapter_t *adapter, gf_get_perf_event_t *get_perf_event int i = 0; int ret = 0; char *dst_buf = get_perf_event->event_buffer; - gf_perf_event_header_t *perf_event; perf_event_trace("perf_event_get_event enter\n"); @@ -518,8 +513,6 @@ int perf_event_get_event(adapter_t *adapter, gf_get_perf_event_t *get_perf_event gf_copy_to_user(dst_buf, &event_node->perf_event, event_node->perf_event.size); dst_buf += event_node->perf_event.size; - perf_event = &event_node->perf_event; - list_del(&event_node->list_node); gf_free(event_node); @@ -931,8 +924,12 @@ int hwq_process_vsync_event(adapter_t *adapter, unsigned long long time) } p_hwq_event->idle_time+=(e_idle_time - s_idle_time); } - p_hwq_event->engine_usage = 100 - gf_do_div(p_hwq_event->idle_time*100, time - hwq_event_mgr->start_time); - //gf_info("\n EngineNum=%d engine_usage ALL=%llu%%\n",engine,p_hwq_event->engine_usage); + + if (time != hwq_event_mgr->start_time) + { + p_hwq_event->engine_usage = 100 - gf_do_div(p_hwq_event->idle_time*100, time - hwq_event_mgr->start_time); + //gf_info("\n EngineNum=%d engine_usage ALL=%llu%%\n",engine,p_hwq_event->engine_usage); + } p_hwq_event->idle_time=0; p_hwq_event->engine_status.active=0; diff --git a/drivers/gpu/drm/arise/core/perfevent/perfevent.h b/drivers/gpu/drm/arise/core/perfevent/perfevent.h index 76bacc8f672de..5c38b83131267 100644 --- a/drivers/gpu/drm/arise/core/perfevent/perfevent.h +++ b/drivers/gpu/drm/arise/core/perfevent/perfevent.h @@ -24,9 +24,7 @@ #ifndef __PERF_EVENT_H__ #define __PERF_EVENT_H__ -#include "gf_def.h" - -extern int arise_perf_event_init(adapter_t *adapter); +extern int perf_event_init(adapter_t *adapter); extern int perf_event_deinit(adapter_t *adapter); extern int perf_event_begin(adapter_t *adapter, gf_begin_perf_event_t *begin); extern int perf_event_end(adapter_t *adapter, gf_end_perf_event_t *end); diff --git a/drivers/gpu/drm/arise/core/perfevent/perfeventi.h b/drivers/gpu/drm/arise/core/perfevent/perfeventi.h index 0ae983a31940f..b9da5b1d0cbd1 100644 --- a/drivers/gpu/drm/arise/core/perfevent/perfeventi.h +++ b/drivers/gpu/drm/arise/core/perfevent/perfeventi.h @@ -25,7 +25,6 @@ #define __PERF_EVENTI_H__ #include "gf_adapter.h" -#include "gf_def.h" #include "list.h" diff --git a/drivers/gpu/drm/arise/core/powermgr/powermgr.c b/drivers/gpu/drm/arise/core/powermgr/powermgr.c index 26039b4acfa5c..446d196d8c88b 100644 --- a/drivers/gpu/drm/arise/core/powermgr/powermgr.c +++ b/drivers/gpu/drm/arise/core/powermgr/powermgr.c @@ -24,14 +24,18 @@ #include "gf_adapter.h" #include "vidsch.h" #include "vidmm.h" -#include "context.h" #include "global.h" +#include "vidschi.h" #include "powermgr.h" int pm_save_state(adapter_t *adapter, int need_save_memory) { int ret = S_OK; + struct vidschedule *schedule = adapter->schedule; + schedule->chip_func->boost(adapter, ENG_POWER_STATE_E0, 60 * 1000, FALSE); + + adapter->ctl_flags.boost = FALSE; adapter->in_suspend_resume = TRUE; ret = cm_save(adapter, need_save_memory); @@ -87,6 +91,7 @@ int pm_restore_state(adapter_t *adapter) cm_restore(adapter); util_print_time("cm_restore finish, cur time"); + adapter->ctl_flags.boost = TRUE; adapter->in_suspend_resume = FALSE; return ret; diff --git a/drivers/gpu/drm/arise/core/util/bit_op.h b/drivers/gpu/drm/arise/core/util/bit_op.h index 1519bbc10e500..be3cc5c258193 100644 --- a/drivers/gpu/drm/arise/core/util/bit_op.h +++ b/drivers/gpu/drm/arise/core/util/bit_op.h @@ -31,6 +31,36 @@ #define VERIFY_BIT_OP 0 +#if defined(__riscv) +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} +#endif static __inline__ unsigned char _BitScanForward(volatile unsigned int *Index, unsigned int Mask) { @@ -48,6 +78,8 @@ static __inline__ unsigned char _BitScanForward(volatile unsigned int *Index, un :"=r"(Mask) :"r" (Mask) ); +#elif defined(__riscv) + Mask = ffs(Mask)-1; #else Mask = __builtin_ffs(Mask)-1; #endif diff --git a/drivers/gpu/drm/arise/core/vidmm/vidmm.c b/drivers/gpu/drm/arise/core/vidmm/vidmm.c index 378c49eddd1e9..a65ca7620be67 100644 --- a/drivers/gpu/drm/arise/core/vidmm/vidmm.c +++ b/drivers/gpu/drm/arise/core/vidmm/vidmm.c @@ -742,6 +742,12 @@ int vidmm_save(adapter_t *adapter) if (adapter->fence_buf_local->backup) gf_memcpy(adapter->fence_buf_local->backup, adapter->fence_buf_local->reserved_memory->vma->virt_addr, 68 * 1024); + if (!adapter->fence_buf->reserved_memory->pages_mem) + { + adapter->fence_buf->backup = gf_malloc(512 * 1024); + if (adapter->fence_buf->backup) + gf_memcpy(adapter->fence_buf->backup, adapter->fence_buf->reserved_memory->vma->virt_addr, 512 * 1024); + } return result; } @@ -783,12 +789,28 @@ void vidmm_restore(adapter_t *adapter) } #endif + if (gart_table_L3->backup) + { + gf_mutex_lock(adapter->gart_table_lock); + gart_table_L3->dirty = TRUE; + gart_table_L3->gart_table_dirty_addr = 0; + gart_table_L3->gart_table_dirty_mask = -1; + gf_mutex_unlock(adapter->gart_table_lock); + } + if (adapter->fence_buf_local->backup) { gf_memcpy(adapter->fence_buf_local->reserved_memory->vma->virt_addr, adapter->fence_buf_local->backup, 68 * 1024); gf_free(adapter->fence_buf_local->backup); } + if (adapter->fence_buf->backup) + { + gf_memcpy(adapter->fence_buf->reserved_memory->vma->virt_addr, adapter->fence_buf->backup, 512 * 1024); + gf_free(adapter->fence_buf->backup); + } + + adapter->fence_buf->backup = NULL; adapter->fence_buf_local->backup = NULL; gart_table_L3->backup = NULL; gart_table_L2->backup = NULL; diff --git a/drivers/gpu/drm/arise/core/vidmm/vidmm.h b/drivers/gpu/drm/arise/core/vidmm/vidmm.h index e423c88d29dbb..2d033c67ff624 100644 --- a/drivers/gpu/drm/arise/core/vidmm/vidmm.h +++ b/drivers/gpu/drm/arise/core/vidmm/vidmm.h @@ -27,7 +27,6 @@ #include "heap_manager.h" #include "list.h" #include "context.h" -#include "gf_def.h" #define SEGMENT_ID_INVALID 0x0 #define SEGMENT_ID_LOCAL 0x1 diff --git a/drivers/gpu/drm/arise/core/vidmm/vidmm_allocate.c b/drivers/gpu/drm/arise/core/vidmm/vidmm_allocate.c index 02b8a75c6007a..2c2728db2a74c 100644 --- a/drivers/gpu/drm/arise/core/vidmm/vidmm_allocate.c +++ b/drivers/gpu/drm/arise/core/vidmm/vidmm_allocate.c @@ -203,6 +203,8 @@ int vidmmi_allocate_video_memory_try(vidmm_mgr_t *mm_mgr, vidmm_allocation_t *al if(list_node == NULL) { + gf_warning("!!!!!!!!!!!!!!!!!!! kmd can't allocate first prefered segment %d , try allocate segment : %d !!!!!!!!!!!!!!!!!!!!!", + preferred_segment->segment_id_0, preferred_segment->segment_id_1); segment_id = preferred_segment->segment_id_1; direction = preferred_segment->direction_1; @@ -215,6 +217,8 @@ int vidmmi_allocate_video_memory_try(vidmm_mgr_t *mm_mgr, vidmm_allocation_t *al if(list_node == NULL) { + gf_warning("!!!!!!!!!!!!!!!!!!! kmd can't allocate first prefered segment %d , try allocate segment : %d !!!!!!!!!!!!!!!!!!!!!", + preferred_segment->segment_id_0, preferred_segment->segment_id_2); segment_id = preferred_segment->segment_id_2; direction = preferred_segment->direction_2; @@ -227,6 +231,8 @@ int vidmmi_allocate_video_memory_try(vidmm_mgr_t *mm_mgr, vidmm_allocation_t *al if(list_node == NULL) { + gf_warning("!!!!!!!!!!!!!!!!!!! kmd can't allocate first prefered segment %d , try allocate segment : %d !!!!!!!!!!!!!!!!!!!!!", + preferred_segment->segment_id_0, preferred_segment->segment_id_3); segment_id = preferred_segment->segment_id_3; direction = preferred_segment->direction_3; segment = &mm_mgr->segment[segment_id]; @@ -240,6 +246,8 @@ int vidmmi_allocate_video_memory_try(vidmm_mgr_t *mm_mgr, vidmm_allocation_t *al if(list_node == NULL) { + gf_warning("!!!!!!!!!!!!!!!!!!! kmd can't allocate first prefered segment %d , try allocate segment : %d !!!!!!!!!!!!!!!!!!!!!", + preferred_segment->segment_id_0, preferred_segment->segment_id_4); segment_id = preferred_segment->segment_id_4; direction = preferred_segment->direction_4; diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch.c b/drivers/gpu/drm/arise/core/vidsch/vidsch.c index 99c1b96f8b6a5..0b5e947693149 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch.c @@ -84,7 +84,7 @@ int vidsch_create(adapter_t *adapter) adapter->active_engine_count = query_data.engine_count; - adapter->fence_buf = vidschi_create_fence_buffer(adapter, query_data.fence_buffer_segment_id, 68*1024); + adapter->fence_buf = vidschi_create_fence_buffer(adapter, query_data.fence_buffer_segment_id, 512 * 1024); adapter->fence_buf_local = vidschi_create_fence_buffer(adapter, 0x1, 68*1024); adapter->fence_buf_snoop = vidschi_create_fence_buffer(adapter, 0x3, 68*1024); @@ -253,6 +253,8 @@ int vidsch_create(adapter_t *adapter) } } + schedule->chip_func->boost(adapter, ENG_POWER_STATE_E0, 90 * 1000, FALSE); + vidschi_init_daemon_thread(adapter); //vidschi_dump_buffer(adapter); @@ -703,12 +705,22 @@ void vidsch_dvfs_power_flag_reset(adapter_t *adapter) } } +void vidsch_set_power_state(adapter_t *adapter, unsigned int state, unsigned int holding_ms, unsigned int force) +{ + struct vidschedule *schedule = adapter->schedule; + + if (!adapter->pwm_level.EnablePowerSwitch) + return; + + schedule->chip_func->boost(adapter, state, holding_ms, force); +} + static vidsch_fence_buffer_t *vidschi_create_fence_buffer(adapter_t *adapter, unsigned int segment_id, int buffer_size) { vidsch_fence_buffer_t *fence_buf = gf_calloc(sizeof(vidsch_fence_buffer_t)); vidmm_segment_memory_t *reserved_memory = NULL; vidmm_map_flags_t map_flags = {0}; - unsigned short total_num = 0; + unsigned int total_num = 0; reserved_memory = vidmm_allocate_segment_memory(adapter, segment_id, buffer_size, 0); diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch.h b/drivers/gpu/drm/arise/core/vidsch/vidsch.h index 779fb72ca4059..22b8296f99008 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch.h +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch.h @@ -26,7 +26,6 @@ #include "vidmm.h" #include "context.h" -#include "gf_def.h" #include "list.h" #include "kernel_interface.h" @@ -236,6 +235,7 @@ extern void vidsch_wait_engine_idle(adapter_t *adapter, int idx); extern int vidsch_save(adapter_t *adapter); extern void vidsch_restore(adapter_t *adapter); extern void vidsch_dvfs_power_flag_reset(adapter_t *adapter); +extern void vidsch_set_power_state(adapter_t *adapter, unsigned int state, unsigned int holding_ms, unsigned int force); extern task_dma_t *vidsch_allocate_task_dma(adapter_t *adapter, unsigned int engine_index, vidsch_allocate_task_dma_t *dma_arg); extern task_paging_t *vidsch_allocate_paging_task(adapter_t *adapter, int dma_size, int allocation_num); diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_daemon_thread.c b/drivers/gpu/drm/arise/core/vidsch/vidsch_daemon_thread.c index 977d6bb545a38..63cfd0d460e36 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_daemon_thread.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_daemon_thread.c @@ -177,6 +177,19 @@ static int vidschi_check_hang_and_recovery(adapter_t *adapter) return 0; } +static int vidsch_daemon_engine_status(void *data, gf_event_status_t ret) +{ + vidschedule_t *schedule = data; + adapter_t *adapter = schedule->adapter; + unsigned long long timestamp; + + gf_get_nsecs(×tamp); + gf_core_interface->hwq_process_vsync_event(adapter, timestamp); + schedule->chip_func->boost(adapter, ENG_POWER_STATE_AUTO, ENG_POWER_MIN_HOLDING_TIME_MS, FALSE); + + return 0; +} + static int vidsch_daemon_delay_allocation(void *data, gf_event_status_t ret) { vidschedule_t *schedule = data; @@ -220,6 +233,8 @@ int vidschi_init_daemon_thread(adapter_t *adapter) util_create_event_thread(vidsch_daemon_check_hang, schedule, "daemon_check_hang", DAEMON_THREAD_INTERVAL); schedule->daemon_thread_destory_allocation = util_create_event_thread(vidsch_daemon_delay_allocation, schedule, "daemon_delay_allocation", DAEMON_THREAD_INTERVAL); + schedule->daemon_thread_power_control = + util_create_event_thread(vidsch_daemon_engine_status, schedule, "daemon_engine_status", DAEMON_THREAD_INTERVAL / 5); return 0; } @@ -232,11 +247,17 @@ int vidschi_deinit_daemon_thread(adapter_t *adapter) { util_destroy_event_thread(schedule->daemon_thread_check_hang); } + if (schedule->daemon_thread_destory_allocation) { util_destroy_event_thread(schedule->daemon_thread_destory_allocation); } + if (schedule->daemon_thread_power_control) + { + util_destroy_event_thread(schedule->daemon_thread_power_control); + } + return 0; } diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_render.c b/drivers/gpu/drm/arise/core/vidsch/vidsch_render.c index 8d7af4c46ff8f..45210a7fd2465 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_render.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_render.c @@ -29,7 +29,6 @@ #include "vidsch_workerthread.h" #include "vidsch_sync.h" #include "vidmm.h" -#include "context.h" #include "global.h" #include "perfevent.h" @@ -73,6 +72,11 @@ void vidschi_emit_dma_fence(vidsch_mgr_t *sch_mgr, task_desc_t *task) adapter->drm_cb->fence.attach_buffer( adapter->drm_cb_argu, allocation->bo, task->dma_fence, sch_allocation_list[i].write_operation ? 0 : 1); + + if (sch_allocation_list[i].write_operation) + { + adapter->drm_cb->kms.check_touch_primary(adapter->drm_cb_argu, allocation->bo); + } } } } diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_submit.c b/drivers/gpu/drm/arise/core/vidsch/vidsch_submit.c index 78de3ff4e46e9..2b929dd08e20e 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_submit.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_submit.c @@ -26,7 +26,6 @@ #include "vidschi.h" #include "vidsch_render.h" #include "vidmm.h" -#include "context.h" #include "vidsch_submit.h" #include "perfevent.h" @@ -37,16 +36,20 @@ static int vidschi_submit_dma(vidsch_mgr_t *sch_mgr, task_dma_t *task_dma) gpu_context_t *context = task_dma->desc.context; vidmm_allocation_t *mm_allocation = NULL; vidsch_allocation_t *sch_allocation = NULL; - unsigned long long fence_id, last_send_fence_id; + unsigned long long fence_id; int i, ret = S_OK; gf_down_read(schedule->rw_lock); + if (task_dma->desc.Flags.normal_recovery) + schedule->chip_func->boost(adapter, ENG_POWER_STATE_E0, ENG_POWER_MIN_HOLDING_TIME_MS * 10, FALSE); + else + schedule->chip_func->boost(adapter, sch_mgr->boost_level, ENG_POWER_MIN_HOLDING_TIME_MS, FALSE); + gf_mutex_lock(sch_mgr->engine_lock); //gf_mutex_lock(adapter->hw_reset_lock); - last_send_fence_id = sch_mgr->last_send_fence_id; fence_id = vidschi_inc_send_fence_id(sch_mgr, task_dma->prepare_submit); task_dma->prepare_submit = FALSE; @@ -79,7 +82,6 @@ static int vidschi_submit_dma(vidsch_mgr_t *sch_mgr, task_dma_t *task_dma) sch_allocation->segment_id = mm_allocation->segment_id; sch_allocation->phy_addr = mm_allocation->phys_addr; - } } @@ -161,6 +163,8 @@ void vidsch_submit_paging_task(adapter_t *adapter, task_paging_t *paging_task) gf_down_read(schedule->rw_lock); + schedule->chip_func->boost(adapter, sch_mgr->boost_level, ENG_POWER_MIN_HOLDING_TIME_MS, FALSE); + /* lock engine */ gf_mutex_lock(sch_mgr->engine_lock); diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_sync.c b/drivers/gpu/drm/arise/core/vidsch/vidsch_sync.c index c5af5ebe6c473..467ab333c4e1b 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_sync.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_sync.c @@ -528,7 +528,7 @@ static int vidschi_wait_fence_sync_object_signaled(task_wait_t *task, vidsch_wai adapter_t *adapter = context->device->adapter; vidsch_mgr_t *sch_mgr = adapter->sch_mgr[context->engine_index]; condition_func_t condition = (condition_func_t)&vidschi_is_fence_sync_object_signaled; - unsigned int msec = gf_do_div(instance->timeout, 1000); + unsigned int msec = gf_do_div(instance->timeout, 1000 * 1000); unsigned int e_status = 0, status = 0; vidsch_wait_fence_signaled_arg_t argu = {0}; @@ -577,7 +577,7 @@ static int vidschi_client_wait_instance_signaled(task_wait_t *task, vidsch_wait_ adapter_t *adapter = task->desc.context->device->adapter; vidsch_sync_object_t *sync_obj = instance->sync_obj; - int status = GF_SYNC_OBJ_CONDITION_SATISFIED; + int ret = 0, status = GF_SYNC_OBJ_CONDITION_SATISFIED; switch (sync_obj->type) { @@ -601,7 +601,13 @@ static int vidschi_client_wait_instance_signaled(task_wait_t *task, vidsch_wait_ case GF_SYNC_OBJ_TYPE_DMAFENCE: - status = adapter->drm_cb->fence.dma_sync_object_wait(adapter->drm_cb_argu, sync_obj->dma.dma_sync_obj, 1000); + ret = adapter->drm_cb->fence.dma_sync_object_wait(adapter->drm_cb_argu, sync_obj->dma.dma_sync_obj, 1000); + if (ret > 0) + status = GF_SYNC_OBJ_ALREAD_SIGNALED; + else if (!ret) + status = GF_SYNC_OBJ_TIMEOUT_EXPIRED; + else + status = GF_SYNC_OBJ_ERROR; break; diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_task.c b/drivers/gpu/drm/arise/core/vidsch/vidsch_task.c index 7bd7305096ea1..718ad14bb3573 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_task.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_task.c @@ -22,7 +22,6 @@ * */ #include "gf_adapter.h" -#include "context.h" #include "vidsch.h" #include "vidschi.h" #include "vidsch_sync.h" diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.c b/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.c index 97ff232736acd..7c54d00701548 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.c +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.c @@ -27,7 +27,6 @@ #include "vidsch_workerthread.h" #include "vidsch_sync.h" #include "vidsch_submit.h" -#include "context.h" #include "perfevent.h" void vidschi_dump_task_pool(struct os_printer *p, adapter_t *adapter, pending_task_pool_t *pool, const char *log_str) @@ -70,7 +69,7 @@ static int vidschi_try_submit_pending_task(vidsch_mgr_t *sch_mgr, pending_task_p unsigned long long global_task_id = 0ll; int submited_count = 0; - int submitted = FALSE, signaled = FALSE; + int submitted = FALSE; vidschi_init_task_pool(&schedule_pool, TRUE); vidschi_init_task_pool(&unready_pool, FALSE); @@ -148,7 +147,6 @@ static int vidschi_try_submit_pending_task(vidsch_mgr_t *sch_mgr, pending_task_p if(vidschi_try_signal(task->task_signal) == S_OK) { - signaled = TRUE; submitted = TRUE; context->last_submit_to_sw = task_id; @@ -194,11 +192,6 @@ static int vidschi_try_submit_pending_task(vidsch_mgr_t *sch_mgr, pending_task_p if(pool == &sch_mgr->normal_task_pool) { gf_up(sch_mgr->normal_pool_sema); - if(context->context_ctrl) - { - gf_up(context->context_sema); - } - } } else @@ -214,13 +207,6 @@ static int vidschi_try_submit_pending_task(vidsch_mgr_t *sch_mgr, pending_task_p vidschi_splice_task_pool(pool, &unready_pool); } -#if 0 - if(signaled) - { - /* try wakeup all thread for none fence syncobj*/ - } -#endif - vidschi_fini_task_pool(&schedule_pool); vidschi_fini_task_pool(&unready_pool); diff --git a/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.h b/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.h index 3b12a9b7b7748..202f3478d27cf 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.h +++ b/drivers/gpu/drm/arise/core/vidsch/vidsch_workerthread.h @@ -153,11 +153,6 @@ static inline int vidschi_add_task_to_pending_queue(vidsch_mgr_t *sch_mgr, task_ gf_down(sch_mgr->normal_pool_sema); - if(context->context_ctrl) - { - gf_down(context->context_sema); - } - if (sch_mgr->task_id_lock) { diff --git a/drivers/gpu/drm/arise/core/vidsch/vidschi.h b/drivers/gpu/drm/arise/core/vidsch/vidschi.h index dcf1ac46d6640..d38b300835de6 100644 --- a/drivers/gpu/drm/arise/core/vidsch/vidschi.h +++ b/drivers/gpu/drm/arise/core/vidsch/vidschi.h @@ -256,6 +256,7 @@ typedef struct _vidsch_mgr unsigned long long last_busy; unsigned int completely_idle; unsigned long long idle_elapse; + unsigned int boost_level; }vidsch_mgr_t; /* for histroy issue, vidsch_mgr_t acctuall mean HW engine, and vidsch_global is engine manager */ @@ -267,6 +268,7 @@ typedef struct vidschedule util_event_thread_t *daemon_thread_destory_allocation; util_event_thread_t *daemon_thread_check_hang; + util_event_thread_t *daemon_thread_power_control; unsigned int hw_hang; /* one bit for one engine, added for video module checking hw hang by looping */ @@ -314,6 +316,7 @@ struct vidschedule_chip_func { void (*dvfs_tuning)(adapter_t* adapter); void (*power_tuning)(adapter_t* adapter, unsigned int gfx_only); + void (*boost)(adapter_t *adapter, unsigned int state, unsigned int holding_ms, unsigned int force); void (*dump_info)(struct os_seq_file *seq_file, adapter_t *adapter); void (*dump_debugbus)(struct os_printer *p, adapter_t *adapter); diff --git a/drivers/gpu/drm/arise/gf_version.h b/drivers/gpu/drm/arise/gf_version.h index 7c50ebbc00473..8634986b1f6ac 100644 --- a/drivers/gpu/drm/arise/gf_version.h +++ b/drivers/gpu/drm/arise/gf_version.h @@ -21,16 +21,17 @@ * IN THE SOFTWARE. * */ -#define DRIVER_DATE "10/08/2024" + +#define DRIVER_DATE "05/19/2025" #define DRIVER_MAJOR 0x25 #define DRIVER_MINOR 0x00 -#define DRIVER_PATCHLEVEL 0x36 +#define DRIVER_PATCHLEVEL 0x46 #define DRIVER_CLASS "" #define DRIVER_NAME arise #define DRIVER_VENDOR "Glenfly Tech Co., Ltd." #define DRIVER_LICENSE "Glenfly" #define DRIVER_VERSION ((DRIVER_MAJOR<<24)|(DRIVER_MINOR<<16)|DRIVER_PATCHLEVEL) -#define DRIVER_VERSION_CHAR "25.00.36" +#define DRIVER_VERSION_CHAR "25.00.46" #define OS_VERSION "" #define CC_VERSION "" #define LD_VERSION "" diff --git a/drivers/gpu/drm/arise/linux/gf.c b/drivers/gpu/drm/arise/linux/gf.c index 82f2bf6ceed2a..ba02e6f3c010a 100644 --- a/drivers/gpu/drm/arise/linux/gf.c +++ b/drivers/gpu/drm/arise/linux/gf.c @@ -71,6 +71,7 @@ module_init(gf_init); module_exit(gf_exit); MODULE_LICENSE("GPL"); MODULE_VERSION(DRIVER_VERSION_CHAR); +MODULE_DESCRIPTION("Glenfly DRM PRO Driver"); #ifndef KERNEL_2_4 module_param(gf_fb, int, 0); diff --git a/drivers/gpu/drm/arise/linux/gf_atomic.c b/drivers/gpu/drm/arise/linux/gf_atomic.c index 19edd390cb192..5b3be1e941640 100644 --- a/drivers/gpu/drm/arise/linux/gf_atomic.c +++ b/drivers/gpu/drm/arise/linux/gf_atomic.c @@ -22,6 +22,7 @@ * */ #include "gf_atomic.h" +#include "gf_disp.h" #include "gf_kms.h" #include "gf_sink.h" #include "gf_splice.h" @@ -255,6 +256,9 @@ static void gf_update_crtc_sink(struct drm_atomic_state *old_state) void gf_atomic_helper_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *dev = old_state->dev; + gf_card_t *gf_card = dev->dev_private; + disp_info_t *disp_info = (disp_info_t*)gf_card->disp_info; + struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; int i; @@ -265,6 +269,8 @@ void gf_atomic_helper_commit_tail(struct drm_atomic_state *old_state) bool flags = false; #endif + gf_acquire_display(disp_info, DISP_FLIP_REF); + drm_atomic_helper_commit_modeset_disables(dev, old_state); drm_atomic_helper_commit_modeset_enables(dev, old_state); @@ -306,6 +312,8 @@ void gf_atomic_helper_commit_tail(struct drm_atomic_state *old_state) drm_atomic_helper_cleanup_planes(dev, old_state); + gf_release_display(disp_info, DISP_FLIP_REF); + gf_rpm_mark_last_busy(dev->dev); } diff --git a/drivers/gpu/drm/arise/linux/gf_audio.c b/drivers/gpu/drm/arise/linux/gf_audio.c index d7f967763b104..de4818922e0c1 100644 --- a/drivers/gpu/drm/arise/linux/gf_audio.c +++ b/drivers/gpu/drm/arise/linux/gf_audio.c @@ -29,9 +29,13 @@ #include #endif +#if DRM_VERSION_CODE >= KERNEL_VERSION(6, 14, 0) +static int gf_audio_match(struct device *dev, const void *data) +#else static int gf_audio_match(struct device *dev, void *data) +#endif { - int *addr = data; + const int *addr = data; #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) struct hdac_device *hdev = dev_to_hdac_dev(dev); @@ -70,6 +74,7 @@ void gf_audio_set_connect(gf_connector_t *gf_connector, int enable) gf_card_t *gf_card; int addr = 0; struct device *dev = NULL; + int pm_ret = 0, pm_req = 0; if (!gf_connector) { @@ -83,12 +88,18 @@ void gf_audio_set_connect(gf_connector_t *gf_connector, int enable) { if (gf_connector->hda_codec_index & (1 << addr)) { - dev = gf_audio_find_device(gf_card, addr+1); // Our codec addr in hdaudio driver is 1-based. if (dev) { - pm_runtime_get_sync(dev); // set codec device to RPM_ACTIVE + if(!(gf_card->flags & GF_SHUT_DOWN)) + { + pm_req = 1; + } + if (pm_req) + { + pm_ret = pm_runtime_get_sync(dev); // set codec device to RPM_ACTIVE + } } if (enable && gf_connector->support_audio) @@ -103,15 +114,24 @@ void gf_audio_set_connect(gf_connector_t *gf_connector, int enable) if (dev) { - pm_runtime_mark_last_busy(dev); - pm_runtime_put_autosuspend(dev); + if (pm_req) + { + if (pm_ret < 0) + { + pm_runtime_put_noidle(dev); + } + else + { + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + } + } put_device(dev); } break; } } - } diff --git a/drivers/gpu/drm/arise/linux/gf_cbios.c b/drivers/gpu/drm/arise/linux/gf_cbios.c index 627c02b03aefb..dc73009076521 100644 --- a/drivers/gpu/drm/arise/linux/gf_cbios.c +++ b/drivers/gpu/drm/arise/linux/gf_cbios.c @@ -552,7 +552,6 @@ int disp_init_cbios(disp_info_t *disp_info) fnCallBack.Size = sizeof(CBIOS_CALLBACK_FUNCTIONS); - fnCallBack.pFnDbgPrint = disp_dbg_print; fnCallBack.pFnDelayMicroSeconds = disp_delay_micro_seconds; fnCallBack.pFnReadUchar = disp_read_uchar; fnCallBack.pFnReadUshort = disp_read_ushort; @@ -582,6 +581,7 @@ int disp_init_cbios(disp_info_t *disp_info) fnCallBack.pFnDodiv = gf_do_div; fnCallBack.pFnVsprintf = gf_vsprintf; fnCallBack.pFnVsnprintf = gf_vsnprintf; + fnCallBack.pFnVDbgPrint = gf_cb_vdbgprint; if(CBiosSetCallBackFunctions(&fnCallBack) != CBIOS_OK) { @@ -853,6 +853,29 @@ int disp_cbios_get_adapter_modes(disp_info_t *disp_info, void* buffer, int buf_s return real_num; } +CBiosModeInfoExt* disp_cbios_get_preferred_mode(CBiosModeInfoExt *dev_mode_list, unsigned int mode_num) +{ + CBiosModeInfoExt *pcbios_mode = NULL; + int i = 0; + + for (i = 0; i < mode_num; i++) + { + pcbios_mode = dev_mode_list + i; + + if (pcbios_mode->isPreferredMode) + { + break; + } + } + + return pcbios_mode; +} + +CBiosModeInfoExt* disp_cbios_get_maxium_mode(CBiosModeInfoExt *dev_mode_list) +{ + return &dev_mode_list[0]; +} + int disp_cbios_merge_modes(CBiosModeInfoExt* merge_mode_list, CBiosModeInfoExt * adapter_mode_list, unsigned int const adapter_mode_num, CBiosModeInfoExt const * dev_mode_list, unsigned int const dev_mode_num) { @@ -1945,6 +1968,8 @@ int disp_cbios_crtc_flip(disp_info_t *disp_info, gf_crtc_flip_t *arg) disp_plane.FlipMode.FlipType = CBIOS_PLANE_FLIP_WITH_DISABLE; } + gf_card->primary_addr[arg->crtc] = gfb ? gfb->obj->info.gpu_virt_addr:0; + if(fb) { input_stream.SurfaceAttrib.StartAddr = gfb->obj->info.gpu_virt_addr; @@ -2562,64 +2587,34 @@ int disp_cbios_wb_ctl(disp_info_t *disp_info, gf_wb_set_t *wb_set) int disp_wait_idle(void *_disp_info) { disp_info_t *disp_info = _disp_info; - - unsigned long timeout_j = jiffies + msecs_to_jiffies(50) + 1; - unsigned int in_vblank; - int ret = DISP_OK; - gf_get_counter_t get_cnt = {0}; + void *pcbe = NULL; unsigned int i = 0; + int cb_status = CBIOS_OK; - if(!disp_info) + if (!disp_info) { gf_info("why disp_info is null, 0x%x 0x%x\n",disp_info,_disp_info); - return -1; + return -EINVAL; } - i = 0; - while(i < disp_info->num_crtc) + pcbe = disp_info->cbios_ext; + + while (i < disp_info->num_crtc) { - if(disp_info->active_output[i]) + if (disp_info->active_output[i]) { break; } i++; } - //case1): has one active crtc, wait the crtc's vblank - //case2): no active crtc, no need to wait. - if(i != disp_info->num_crtc) //has active crtc + //only wait the first active crtc's vblank + if (i != disp_info->num_crtc) { - get_cnt.crtc_index = i; - get_cnt.in_vblk = &in_vblank; - - disp_cbios_get_counter(disp_info, &get_cnt); - - while(in_vblank == 1) - { - if(time_after(jiffies, timeout_j)) - { - gf_error("wait in vblank tiemout \n"); - ret = -ETIMEDOUT; - break; - } - disp_cbios_get_counter(disp_info, &get_cnt); - } - - timeout_j = jiffies + msecs_to_jiffies(50) + 1; - - while(in_vblank == 0) - { - if(time_after(jiffies, timeout_j)) - { - gf_error("wait in active timeout\n"); - ret = -ETIMEDOUT; - break; - } - disp_cbios_get_counter(disp_info, &get_cnt); - } + cb_status = CBiosWaitVBlank(pcbe, i); } - return ret; + return (cb_status == CBIOS_TRUE) ? DISP_OK : DISP_FAIL; } static unsigned int cal_bits(unsigned int v) diff --git a/drivers/gpu/drm/arise/linux/gf_cbios.h b/drivers/gpu/drm/arise/linux/gf_cbios.h index 98dfbcb89839a..da3c0c79027a6 100644 --- a/drivers/gpu/drm/arise/linux/gf_cbios.h +++ b/drivers/gpu/drm/arise/linux/gf_cbios.h @@ -123,6 +123,8 @@ int disp_cbios_get_adapter_modes_size(disp_info_t *disp_info); int disp_cbios_get_adapter_modes(disp_info_t *disp_info, void* buffer, int buf_size); int disp_cbios_merge_modes(CBiosModeInfoExt* merge_mode_list, CBiosModeInfoExt * adapter_mode_list, unsigned int const adapter_mode_num, CBiosModeInfoExt const * dev_mode_list, unsigned int const dev_mode_num); +CBiosModeInfoExt* disp_cbios_get_preferred_mode(CBiosModeInfoExt *dev_mode_list, unsigned int mode_num); +CBiosModeInfoExt* disp_cbios_get_maxium_mode(CBiosModeInfoExt *dev_mode_list); int disp_cbios_cbmode_to_drmmode(disp_info_t *disp_info, int output, void* cbmode, int i, struct drm_display_mode *drm_mode); int disp_cbios_3dmode_to_drmmode(disp_info_t *disp_info, int output, void* mode, int i, struct drm_display_mode *drm_mode); int disp_cbios_get_3dmode_size(disp_info_t* disp_info, int output); diff --git a/drivers/gpu/drm/arise/linux/gf_connector.c b/drivers/gpu/drm/arise/linux/gf_connector.c index a8a74172abd9a..32750de7ca503 100644 --- a/drivers/gpu/drm/arise/linux/gf_connector.c +++ b/drivers/gpu/drm/arise/linux/gf_connector.c @@ -306,7 +306,11 @@ static int gf_connector_get_modes(struct drm_connector *connector) } static enum drm_mode_status +#if DRM_VERSION_CODE >= KERNEL_VERSION(6, 15, 0) +gf_connector_mode_valid(struct drm_connector *connector, const struct drm_display_mode *mode) +#else gf_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) +#endif { gf_connector_t *gf_connector = to_gf_connector(connector); int max_clock; diff --git a/drivers/gpu/drm/arise/linux/gf_crtc.c b/drivers/gpu/drm/arise/linux/gf_crtc.c index 6215fac30192b..4051d184de711 100644 --- a/drivers/gpu/drm/arise/linux/gf_crtc.c +++ b/drivers/gpu/drm/arise/linux/gf_crtc.c @@ -263,8 +263,12 @@ void gf_crtc_update_lut(struct drm_crtc_state *crtc_state) gamma[i] = ((b >> 6) & 0x3FF) + ((g << 4) & 0xFFC00) + ((r << 14) & 0x3FF00000); } + gf_mutex_lock(disp_info->gamma_lock); + disp_cbios_set_gamma(disp_info, gf_crtc->pipe, gamma); + gf_mutex_unlock(disp_info->gamma_lock); + gf_free(gamma); } @@ -284,10 +288,10 @@ void gf_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc //do some prepare on specified crtc before update planes //for intel chip, it will wait until scan line is not in (vblank-100us) ~ vblank //will implement it later - if(crtc_state->color_mgmt_changed || + if (crtc_state->color_mgmt_changed || drm_atomic_crtc_needs_modeset(crtc_state)) { - if(crtc_state->gamma_lut) + if (crtc_state->gamma_lut) { gf_crtc_update_lut(crtc_state); } @@ -518,7 +522,12 @@ void gf_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, gf_crtc->lut_entry[i] = (blue[i] >> 6) | ((green[i] << 4) & 0xFFC00) | ((red[i] << 14) & 0x3FF00000); } + gf_mutex_lock(disp_info->gamma_lock); + disp_cbios_set_gamma(disp_info, gf_crtc->pipe, gf_crtc->lut_entry); + + gf_mutex_unlock(disp_info->gamma_lock); + #ifdef PHYTIUM_2000 return 0; #endif diff --git a/drivers/gpu/drm/arise/linux/gf_disp.c b/drivers/gpu/drm/arise/linux/gf_disp.c index e5d145159b086..9296b1c8b0836 100644 --- a/drivers/gpu/drm/arise/linux/gf_disp.c +++ b/drivers/gpu/drm/arise/linux/gf_disp.c @@ -25,6 +25,7 @@ #include "gf_cbios.h" #include "gf_atomic.h" #include "gf_crtc.h" +#include "gf_modifies.h" #include "gf_plane.h" #include "gf_drmfb.h" #include "gf_irq.h" @@ -40,8 +41,10 @@ static const struct drm_mode_config_funcs gf_kms_mode_funcs = { #if DRM_VERSION_CODE < KERNEL_VERSION(4, 19, 0) .output_poll_changed = gf_fbdev_poll_changed, #else +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 12, 0) .output_poll_changed = drm_fb_helper_output_poll_changed, #endif +#endif #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 8, 0) .atomic_check = drm_atomic_helper_check, @@ -92,6 +95,20 @@ static const unsigned int vsync_int_tbl[] = { static char* cursor_name = "cursor"; +#if DRM_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +static const uint64_t chx_cursor_modifiers[] = { + DRM_FORMAT_MOD_GF_LINEAR, + DRM_FORMAT_MOD_GF_INVALID +}; + +static const uint64_t chx_plane_modifiers[] = { + DRM_FORMAT_MOD_GF_DISPLAY, + DRM_FORMAT_MOD_GF_LINEAR, + DRM_FORMAT_MOD_GF_INVALID +}; + +#endif + #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 8, 0) #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) @@ -204,6 +221,7 @@ static void disp_info_pre_init(disp_info_t* disp_info) disp_info->hpd_lock = gf_create_spinlock(0); disp_info->hda_lock = gf_create_spinlock(0); disp_info->hdcp_lock = gf_create_spinlock(0); + disp_info->gamma_lock = gf_create_mutex(); disp_info->cbios_inner_spin_lock = gf_create_spinlock(0); disp_info->cbios_aux_mutex = gf_create_mutex(); @@ -240,6 +258,9 @@ static void disp_info_deinit(disp_info_t* disp_info) gf_destroy_spinlock(disp_info->hdcp_lock); disp_info->hdcp_lock = NULL; + gf_destroy_mutex(disp_info->gamma_lock); + disp_info->gamma_lock = NULL; + #if 0 int i = 0; gf_destroy_spinlock(disp_info->cbios_inner_spin_lock); @@ -443,6 +464,7 @@ void disp_create_plane_property(struct drm_device* dev, gf_plane_t* gf_plane) drm_plane_create_zpos_immutable_property(&gf_plane->base_plane, zpos); //we do not support dynamic plane order } + static gf_plane_t* disp_gene_plane_create(disp_info_t* disp_info, int index, GF_PLANE_TYPE type, int is_cursor) { gf_card_t* gf_card = disp_info->gf_card; @@ -450,7 +472,8 @@ static gf_plane_t* disp_gene_plane_create(disp_info_t* disp_info, int index, gf_plane_t* gf_plane = NULL; gf_plane_state_t* gf_pstate = NULL; int ret = 0; - const int* formats = 0; + const int* formats = NULL; + const uint64_t *modifiers = NULL; int fmt_count = 0; int drm_ptype; char* name; @@ -489,6 +512,9 @@ static gf_plane_t* disp_gene_plane_create(disp_info_t* disp_info, int index, { formats = chx_cursor_formats; fmt_count = sizeof(chx_cursor_formats)/sizeof(chx_cursor_formats[0]); + #if DRM_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) + modifiers = chx_cursor_modifiers; + #endif name = cursor_name; drm_ptype = DRM_PLANE_TYPE_CURSOR; } @@ -496,6 +522,9 @@ static gf_plane_t* disp_gene_plane_create(disp_info_t* disp_info, int index, { formats = chx_plane_formats; fmt_count = sizeof(chx_plane_formats)/sizeof(chx_plane_formats[0]); + #if DRM_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) + modifiers = chx_plane_modifiers; + #endif name = plane_name[type]; drm_ptype = (type == GF_PLANE_PS)? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; } @@ -509,7 +538,7 @@ static gf_plane_t* disp_gene_plane_create(disp_info_t* disp_info, int index, #else ret = drm_universal_plane_init(drm, &gf_plane->base_plane, (1 << index), &gf_plane_funcs, - formats, fmt_count, NULL, + formats, fmt_count, modifiers, drm_ptype, "IGA%d-%s", (index+1), name); #endif @@ -1141,16 +1170,13 @@ static int disp_mode_config_init(disp_info_t* disp_info) drm->mode_config.max_width = 3840*4; // 4*4k drm->mode_config.max_height = 2160*4; - drm->mode_config.cursor_width = 64; - drm->mode_config.cursor_height = 64; + drm->mode_config.cursor_width = 128; + drm->mode_config.cursor_height = 128; drm->mode_config.preferred_depth = 24; drm->mode_config.prefer_shadow = 1; - -#if DRM_VERSION_CODE >= KERNEL_VERSION(5, 18, 0) - drm->mode_config.fb_modifiers_not_supported = TRUE; -#elif DRM_VERSION_CODE < KERNEL_VERSION(5, 14, 0) +#if DRM_VERSION_CODE < KERNEL_VERSION(5, 14, 0) drm->mode_config.allow_fb_modifiers = TRUE; #endif @@ -1315,6 +1341,98 @@ static int disp_modeset_create_properties(disp_info_t *disp_info) return 0; } +#if DRM_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) +void gf_disp_state_timer_fn(struct timer_list *t) +#else +void gf_disp_state_timer_fn(unsigned long data) +#endif +{ +#if DRM_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) + disp_state_info_t *pstate_info = from_timer(pstate_info, t, state_timer); +#else + disp_state_info_t *pstate_info = (disp_state_info_t *)data; +#endif + disp_info_t *disp_info = (disp_info_t *)pstate_info->disp_info; + gf_card_t *gf_card = (gf_card_t *)disp_info->gf_card; + struct drm_device *drm_dev = gf_card->drm_dev; + struct drm_crtc *crtc = NULL; + bool all_crtcs_off = true; + + list_for_each_entry(crtc, &(drm_dev->mode_config.crtc_list), head) + { + if (to_gf_crtc(crtc)->enabled) + { + all_crtcs_off = false; + break; + } + + } + + if (all_crtcs_off) + { + gf_core_interface->disp_state_update(gf_card->adapter, DISP_LONGIDLE_STATE); + + } + else + { + gf_core_interface->disp_state_update(gf_card->adapter, DISP_SHORTIDLE_STATE); + } + + if (all_crtcs_off) + { + atomic_set(&pstate_info->curr_state, DISP_LONGIDLE_STATE); + } + else + { + atomic_set(&pstate_info->curr_state, DISP_SHORTIDLE_STATE); + } +} + +int disp_init_state_info(disp_info_t *disp_info) +{ + disp_state_info_t *pstate_info = NULL; + + pstate_info = gf_calloc(sizeof(disp_state_info_t)); + + if (!pstate_info) + { + return -1; + } + + disp_info->state_info = pstate_info; + pstate_info->disp_info = disp_info; + + pstate_info->ref_lock = gf_create_spinlock(0); + + atomic_set(&pstate_info->curr_state, DISP_INIT_STATE); + +#if DRM_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) + timer_setup(&pstate_info->state_timer, gf_disp_state_timer_fn, 0); +#else + setup_timer(&pstate_info->state_timer, gf_disp_state_timer_fn, (unsigned long)pstate_info); +#endif + + return 0; +} + +void disp_deinit_state_info(disp_info_t* disp_info) +{ + disp_state_info_t* pstate_info = disp_info->state_info; + +#if DRM_VERSION_CODE >= KERNEL_VERSION(6, 15, 0) + timer_delete_sync(&pstate_info->state_timer); +#else + del_timer_sync(&pstate_info->state_timer); +#endif + + gf_destroy_spinlock(pstate_info->ref_lock); + pstate_info->ref_lock = NULL; + + gf_free(pstate_info); + + disp_info->state_info = NULL; +} + int gf_init_modeset(struct drm_device *dev) { gf_card_t* gf_card = dev->dev_private; @@ -1401,6 +1519,8 @@ int gf_init_modeset(struct drm_device *dev) disp_capture_init(disp_info); + disp_init_state_info(disp_info); + disp_info_print(disp_info); return ret; @@ -1454,6 +1574,8 @@ void gf_deinit_modeset(struct drm_device *dev) disp_cbios_cleanup(disp_info); + disp_deinit_state_info(disp_info); + disp_info_deinit(disp_info); gf_free(disp_info); @@ -1685,12 +1807,12 @@ int gf_get_chip_fanspeed(void* dispi, int index) int gf_get_chip_fanspeed_legacy(void* dispi, int index) { - static int fanspeed = 0,pwm = 0; + static int fanspeed = 0; disp_info_t* disp_info = (disp_info_t*)dispi; adapter_info_t* adp_info = disp_info->adp_info; int ctrl_reg_8x000, ctrl_reg_8x008, ctrl_reg_8x014, out_8x01c; - unsigned int *pRegAddr_8x000, *pRegAddr_8x004, *pRegAddr_8x008, *pRegAddr_8x00c, *pRegAddr_8x014, *pRegAddr_8x01c, *pRegAddr_d00xc; - int temp = 0, fanbase = 0, pwmoffset = 0; + unsigned int *pRegAddr_8x000, *pRegAddr_8x004, *pRegAddr_8x008, *pRegAddr_8x014, *pRegAddr_8x01c; + int temp = 0, fanbase = 0; if(adp_info->mmio_size < 0x8F024) { @@ -1705,12 +1827,10 @@ int gf_get_chip_fanspeed_legacy(void* dispi, int index) return fanspeed; fanbase = 0x8c000; - pwmoffset = 0x10; } else if(index == 0) { fanbase = 0x8d000; - pwmoffset = 0x0; } else { @@ -1720,10 +1840,8 @@ int gf_get_chip_fanspeed_legacy(void* dispi, int index) pRegAddr_8x000 = (unsigned int*)(adp_info->mmio + fanbase + 0x000); pRegAddr_8x004 = (unsigned int*)(adp_info->mmio + fanbase + 0x004); pRegAddr_8x008 = (unsigned int*)(adp_info->mmio + fanbase + 0x008); - pRegAddr_8x00c = (unsigned int*)(adp_info->mmio + fanbase + 0x00c); pRegAddr_8x014 = (unsigned int*)(adp_info->mmio + fanbase + 0x014); pRegAddr_8x01c = (unsigned int*)(adp_info->mmio + fanbase + 0x01c); - pRegAddr_d00xc = (unsigned int*)(adp_info->mmio + pwmoffset + 0xd0000 + 0x0c); if((gf_read32(pRegAddr_8x004) & 0x2) != 0) { @@ -1747,8 +1865,6 @@ int gf_get_chip_fanspeed_legacy(void* dispi, int index) fanspeed = -1; } - pwm = gf_read32(pRegAddr_d00xc) & 0xfff; - ctrl_reg_8x014 = 0x7D00; gf_write32(pRegAddr_8x014, ctrl_reg_8x014); @@ -1917,3 +2033,66 @@ int gf_debugfs_displayinfo_dump(struct seq_file* file, struct drm_device* dev) return 0; } +void gf_acquire_display(disp_info_t *disp_info, unsigned int ref_type) +{ + gf_card_t *gf_card = disp_info->gf_card; + disp_state_info_t *pstate_info = disp_info->state_info; + unsigned long flags = 0; + bool request = false; + + flags = gf_spin_lock_irqsave(pstate_info->ref_lock); + + if (!pstate_info->ref_count) + { + request = true; + } + + pstate_info->ref_count |= (1 << ref_type); + + gf_spin_unlock_irqrestore(pstate_info->ref_lock, flags); + + if (request) + { + #if DRM_VERSION_CODE >= KERNEL_VERSION(6, 15, 0) + timer_delete_sync(&pstate_info->state_timer); + #else + del_timer_sync(&pstate_info->state_timer); + #endif + + if (atomic_read(&pstate_info->curr_state) != DISP_BUSY_STATE) + { + gf_core_interface->disp_state_update(gf_card->adapter, DISP_BUSY_STATE); + atomic_set(&pstate_info->curr_state, DISP_BUSY_STATE); + } + } + +} + +void gf_release_display(disp_info_t *disp_info, unsigned int ref_type) +{ + disp_state_info_t *pstate_info = disp_info->state_info; + unsigned long flags = 0; + bool notify = false; + + if (ref_type >= DISP_MAX_REF) + { + return; + } + + flags = gf_spin_lock_irqsave(pstate_info->ref_lock); + + if (pstate_info->ref_count == (1 << ref_type)) + { + notify = true; + } + + pstate_info->ref_count &= ~(1 << ref_type); + + gf_spin_unlock_irqrestore(pstate_info->ref_lock, flags); + + if (notify) + { + mod_timer(&pstate_info->state_timer, jiffies+HZ); + } +} + diff --git a/drivers/gpu/drm/arise/linux/gf_disp.h b/drivers/gpu/drm/arise/linux/gf_disp.h index e1d9247db22b0..b9c93e9991f89 100644 --- a/drivers/gpu/drm/arise/linux/gf_disp.h +++ b/drivers/gpu/drm/arise/linux/gf_disp.h @@ -24,6 +24,7 @@ #ifndef _GF_DISP_H #define _GF_DISP_H +#include "gf.h" #include "gf_kms.h" #include "gf_driver.h" #if DRM_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) @@ -203,6 +204,31 @@ typedef struct gf_i2c_op_t op; }gf_i2c_param_t; +typedef enum _DISP_REFERENCE +{ + DISP_FLIP_REF = 0, + DISP_CURSOR_REF, + DISP_ONSCREENDRAW_REF, + DISP_MAX_REF +}DISP_REFERENCE; + +typedef enum _DSIP_STATE +{ + DISP_INIT_STATE = 0x0, + DISP_LONGIDLE_STATE = 0x1, + DISP_SHORTIDLE_STATE = 0x2, + DISP_BUSY_STATE = 0x3, +}DISP_STATE; + +typedef struct +{ + void *disp_info; + atomic_t curr_state; + struct os_spinlock *ref_lock; + unsigned int ref_count; + struct timer_list state_timer; +} disp_state_info_t; + typedef struct { void *rom_image; @@ -242,6 +268,7 @@ typedef struct struct os_spinlock *hpd_lock; struct os_spinlock *hda_lock; struct os_spinlock *hdcp_lock; + struct os_mutex *gamma_lock; int irq_enabled; int poll_running; atomic_t atomic_irq_lock; @@ -289,6 +316,7 @@ typedef struct struct workqueue_struct *wq; #endif + disp_state_info_t *state_info; }disp_info_t; static __inline__ unsigned char read_reg_exc(unsigned char *mmio, int type, unsigned char index) @@ -406,4 +434,7 @@ void disp_create_plane_property(struct drm_device* dev, gf_plane_t* gf_plane); gf_connector_t* gf_get_connector_by_device_id(disp_info_t *disp_info, int device_id); +void gf_acquire_display(disp_info_t *disp_info, unsigned int ref_type); +void gf_release_display(disp_info_t *disp_info, unsigned int ref_type); + #endif diff --git a/drivers/gpu/drm/arise/linux/gf_driver.c b/drivers/gpu/drm/arise/linux/gf_driver.c index 55177e9b6aff6..be942800b4215 100644 --- a/drivers/gpu/drm/arise/linux/gf_driver.c +++ b/drivers/gpu/drm/arise/linux/gf_driver.c @@ -109,12 +109,12 @@ int gf_map_system_ram(struct vm_area_struct* vma, gf_map_argu_t *map) int start_page = _ALIGN_DOWN(map->offset, PAGE_SIZE) / PAGE_SIZE; int end_page = start_page + PAGE_ALIGN(map->size) / PAGE_SIZE; -#if LINUX_VERSION_CODE <= 0x02040e +#if DRM_VERSION_CODE <= 0x02040e vma->vm_flags |= VM_LOCKED; -#elif LINUX_VERSION_CODE < 0x030700 +#elif DRM_VERSION_CODE < 0x030700 vma->vm_flags |= VM_RESERVED; #else -#if LINUX_VERSION_CODE < KERNEL_VERSION(6,3,0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6,3,0) vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP; #else vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP); @@ -454,7 +454,6 @@ static ssize_t gf_gpuinfo_proc_read(struct file *filp, char *buf, size_t count, int ret = 0; size_t len = 0; - static int print_flag = 1; char *buffer = NULL, *memory_type = "DDR4", *pmp_version = NULL, *product_name = NULL, *type_dp = "\0"; char *output_type_vga_hdmi = "VGA, HDMI", *output_type_full = "VGA, HDMI, DP", *hdmi_resolution = "3840 x 2160", *vga_resolution = "1920 x 1080", *output_type = output_type_vga_hdmi; unsigned int mclk, coreclk, eclk, free_mem, mem_usage, usage_3d, usage_vcp, usage_vpp; @@ -465,7 +464,7 @@ static ssize_t gf_gpuinfo_proc_read(struct file *filp, char *buf, size_t count, unsigned char *fwname = NULL; int fw_version = 0; - if (!print_flag) + if (!offp || *offp) goto exit; buffer = gf_calloc(1024); @@ -605,6 +604,15 @@ static ssize_t gf_gpuinfo_proc_read(struct file *filp, char *buf, size_t count, type_dp = "/DP"; break; + case 0x3d0e: + hdmi_fps = 60; + subsystemid = 0x10D0; + technology = 28; + pixel_fillrate = 96 * eclk; + texture_fillrate = pixel_fillrate *2; + product_name = "Arise10D0"; + break; + default: hdmi_fps = 60; subsystemid = 0; @@ -666,7 +674,8 @@ static ssize_t gf_gpuinfo_proc_read(struct file *filp, char *buf, size_t count, if (ret) goto exit_err; - print_flag = 0; + *offp += len; + return len; exit_err: @@ -676,7 +685,6 @@ static ssize_t gf_gpuinfo_proc_read(struct file *filp, char *buf, size_t count, return -ENOMEM; exit: - print_flag = 1; return 0; } @@ -1019,6 +1027,7 @@ int gf_card_init(gf_card_t *gf, void *pdev) gf->allocation_trace_tags = 0; gf->video_irq_info_all = 0; gf->runtime_pm = gf_modparams.gf_runtime_pm; + gf->flags = 0; return ret; } diff --git a/drivers/gpu/drm/arise/linux/gf_driver.h b/drivers/gpu/drm/arise/linux/gf_driver.h index 5a8ba4cdcf8ae..80b17ff892b6d 100644 --- a/drivers/gpu/drm/arise/linux/gf_driver.h +++ b/drivers/gpu/drm/arise/linux/gf_driver.h @@ -34,6 +34,9 @@ #define __STR(x) #x #define STR(x) __STR(x) +#define GF_S4_RESUME 0x01 +#define GF_SHUT_DOWN 0x02 + typedef struct gf_file gf_file_t; typedef int (*gf_ioctl_t)(struct drm_device *dev, void *data,struct drm_file *filp); @@ -75,7 +78,6 @@ typedef struct struct os_pages_memory *trace_buffer; gf_vm_area_t *trace_buffer_vma; -#define GF_S4_RESUME 0x01 unsigned int flags; unsigned int fps_count; unsigned int rxa_blt_scn_cnt; @@ -83,6 +85,7 @@ typedef struct unsigned long allocation_trace_tags; // allocation trace tags, 0 to disable. unsigned int video_irq_info_all; int runtime_pm; + unsigned long long primary_addr[MAX_CORE_CRTCS]; }gf_card_t; struct gf_file diff --git a/drivers/gpu/drm/arise/linux/gf_encoder.c b/drivers/gpu/drm/arise/linux/gf_encoder.c index 57b92836b325f..d932cc7e66282 100644 --- a/drivers/gpu/drm/arise/linux/gf_encoder.c +++ b/drivers/gpu/drm/arise/linux/gf_encoder.c @@ -63,6 +63,7 @@ void gf_encoder_disable(struct drm_encoder *encoder) gf_encoder_t *gf_encoder = to_gf_encoder(encoder); gf_connector_t *gf_connector = gf_encoder_get_connector(gf_encoder); gf_capture_id_t cf_id = GF_CAPTURE_INVALID; + struct task_struct *cur_task = current; if (!gf_connector) { @@ -102,7 +103,14 @@ void gf_encoder_disable(struct drm_encoder *encoder) } #endif - gf_info("To turn off power of device: 0x%x.\n", gf_encoder->output_type); + if (cur_task) + { + gf_info("Task [%s] turn off power of device: 0x%x.\n", cur_task->comm, gf_encoder->output_type); + } + else + { + gf_info("To turn off power of device: 0x%x.\n", gf_encoder->output_type); + } gf_capture_handle_event(disp_info, cf_id, GF_CAPTURE_EVENT_SIGNAL_OFF); @@ -123,6 +131,7 @@ void gf_encoder_enable(struct drm_encoder *encoder) gf_encoder_t *gf_encoder = to_gf_encoder(encoder); gf_connector_t *gf_connector = gf_encoder_get_connector(gf_encoder); gf_capture_id_t cf_id = GF_CAPTURE_INVALID; + struct task_struct *cur_task = current; if (!gf_connector) { @@ -148,7 +157,14 @@ void gf_encoder_enable(struct drm_encoder *encoder) if(gf_encoder->enc_dpms != GF_DPMS_ON) { - gf_info("To turn on power of device: 0x%x.\n", gf_encoder->output_type); + if (cur_task) + { + gf_info("Task [%s] turn on power of device: 0x%x.\n", cur_task->comm, gf_encoder->output_type); + } + else + { + gf_info("To turn on power of device: 0x%x.\n", gf_encoder->output_type); + } gf_mutex_lock(gf_connector->conn_mutex); disp_cbios_set_dpms(disp_info, gf_encoder->output_type, GF_DPMS_ON); @@ -175,69 +191,105 @@ bool gf_encoder_mode_fixup_internal(disp_info_t* disp_info, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { - unsigned int dev_mode_size = 0, dev_real_num = 0, i = 0, matched = 0; - void * dev_mode_buf = NULL; + unsigned int dev_mode_size = 0, dev_real_num = 0, i = 0; + unsigned int adapter_mode_size = 0, adapter_mode_num = 0; + void *dev_mode_buf = NULL, *adapter_mode_buf = NULL; PCBiosModeInfoExt pcbios_mode = NULL, matched_mode = NULL; + PCBiosModeInfoExt ppreferred_mode = NULL, pmaxium_mode = NULL; + + if (!adjusted_mode) + { + return FALSE; + } dev_mode_size = disp_cbios_get_modes_size(disp_info, output_type); - if(dev_mode_size) + if (!dev_mode_size) + { + goto End; + } + + dev_mode_buf = gf_calloc(dev_mode_size); + if (!dev_mode_buf) + { + goto End; + } + + dev_real_num = disp_cbios_get_modes(disp_info, output_type, dev_mode_buf, dev_mode_size); + for (i = 0; i < dev_real_num; i++) { - dev_mode_buf = gf_calloc(dev_mode_size); - if(dev_mode_buf) + pcbios_mode = (PCBiosModeInfoExt)dev_mode_buf + i; + if ((pcbios_mode->XRes == mode->hdisplay) && + (pcbios_mode->YRes == mode->vdisplay) && + (pcbios_mode->RefreshRate/100 == drm_mode_vrefresh(mode)) && + ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? (pcbios_mode->InterlaceProgressiveCaps == 0x02) : (pcbios_mode->InterlaceProgressiveCaps == 0x01))) { - dev_real_num = disp_cbios_get_modes(disp_info, output_type, dev_mode_buf, dev_mode_size); - for(i = 0; i < dev_real_num; i++) - { - pcbios_mode = (PCBiosModeInfoExt)dev_mode_buf + i; - if((pcbios_mode->XRes == mode->hdisplay) && - (pcbios_mode->YRes == mode->vdisplay) && - (pcbios_mode->RefreshRate/100 == drm_mode_vrefresh(mode)) && - ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? (pcbios_mode->InterlaceProgressiveCaps == 0x02) : (pcbios_mode->InterlaceProgressiveCaps == 0x01))) - { - matched = 1; - break; - } - } + //sw mode == hw mode + goto End; } } - if(!matched && disp_info->scale_support) + if (!disp_info->scale_support) { - for(i = 0; i < dev_real_num; i++) + goto End; + } + + adapter_mode_size = disp_cbios_get_adapter_modes_size(disp_info); + if (!adapter_mode_size) + { + goto End; + } + + adapter_mode_buf = gf_calloc(adapter_mode_size); + if (!adapter_mode_buf) + { + goto End; + } + + ppreferred_mode = disp_cbios_get_preferred_mode((PCBiosModeInfoExt)dev_mode_buf, dev_real_num); + pmaxium_mode = disp_cbios_get_maxium_mode((PCBiosModeInfoExt)dev_mode_buf); + + adapter_mode_num = disp_cbios_get_adapter_modes(disp_info, adapter_mode_buf, adapter_mode_size); + for (i = 0; i < adapter_mode_num; i++) + { + pcbios_mode = (PCBiosModeInfoExt)adapter_mode_buf + i; + + if (pcbios_mode->XRes == mode->hdisplay && + pcbios_mode->YRes == mode->vdisplay && + pcbios_mode->RefreshRate/100 == drm_mode_vrefresh(mode)) { - pcbios_mode = (PCBiosModeInfoExt)dev_mode_buf + i; - if(pcbios_mode->XRes >= mode->hdisplay && pcbios_mode->YRes >= mode->vdisplay && - pcbios_mode->RefreshRate/100 >= drm_mode_vrefresh(mode)) + if (ppreferred_mode != NULL && + ppreferred_mode->XRes >= mode->hdisplay && + ppreferred_mode->YRes >= mode->vdisplay && + ppreferred_mode->RefreshRate/100 >= drm_mode_vrefresh(mode)) { - if(pcbios_mode->isPreferredMode) - { - matched_mode = pcbios_mode; - break; - } - else if(!matched_mode) - { - matched_mode = pcbios_mode; - } + //perferred as the hw mode + matched_mode = ppreferred_mode; + break; } - } - if(matched_mode) - { - if(adjusted_mode) + if (pmaxium_mode != NULL && + pmaxium_mode->XRes >= mode->hdisplay && + pmaxium_mode->YRes >= mode->vdisplay && + pmaxium_mode->RefreshRate/100 >= drm_mode_vrefresh(mode)) { - disp_cbios_cbmode_to_drmmode(disp_info, output_type, matched_mode, 0, adjusted_mode); + //maxium as the hw mode + matched_mode = pmaxium_mode; + break; } - matched = 1; } } - if (adjusted_mode && matched) + if (matched_mode) { + disp_cbios_cbmode_to_drmmode(disp_info, output_type, matched_mode, 0, adjusted_mode); + } + +End: #if DRM_VERSION_CODE < KERNEL_VERSION(5,9,0) - adjusted_mode->vrefresh = drm_mode_vrefresh(adjusted_mode); + adjusted_mode->vrefresh = drm_mode_vrefresh(adjusted_mode); #endif - disp_cbios_get_mode_timing(disp_info, output_type, adjusted_mode); - } + + disp_cbios_get_mode_timing(disp_info, output_type, adjusted_mode); if (dev_mode_buf) { @@ -245,7 +297,13 @@ bool gf_encoder_mode_fixup_internal(disp_info_t* disp_info, dev_mode_buf = NULL; } - return (matched)? TRUE : FALSE; + if (adapter_mode_buf) + { + gf_free(adapter_mode_buf); + adapter_mode_buf = NULL; + } + + return TRUE; } static bool gf_encoder_mode_fixup(struct drm_encoder *encoder, diff --git a/drivers/gpu/drm/arise/linux/gf_fence.c b/drivers/gpu/drm/arise/linux/gf_fence.c index 81c8b94b045b1..5c401cf2a8344 100644 --- a/drivers/gpu/drm/arise/linux/gf_fence.c +++ b/drivers/gpu/drm/arise/linux/gf_fence.c @@ -22,8 +22,10 @@ * */ #include "gf_fence.h" +#include "gf_driver.h" #include "gf_gem.h" #include "gf_gem_priv.h" +#include "gf_disp.h" #include "gf_trace.h" static const char *engine_name[MAX_ENGINE_COUNT] = { @@ -39,8 +41,6 @@ static const char *engine_name[MAX_ENGINE_COUNT] = { "ring9", }; -static struct gf_dma_fence_driver *fence_driver = NULL; - static bool gf_dma_fence_signaled(dma_fence_t *base) { struct gf_dma_fence *fence = to_gf_fence(base); @@ -89,12 +89,15 @@ static void gf_dma_fence_free(struct rcu_head *rcu) dma_fence_t *base = container_of(rcu, dma_fence_t, rcu); struct gf_dma_fence *fence = to_gf_fence(base); - if (fence_driver != fence->driver) - gf_info("detect someone trying to write fence:0x%llx\n", fence->driver); - - atomic_dec(&fence_driver->fence_alloc_count); - - kmem_cache_free(fence_driver->fence_slab, fence); + if (!fence->magic_number) + { + atomic_dec(&fence->driver->fence_alloc_count); + kmem_cache_free(fence->driver->fence_slab, fence); + } + else + { + gf_info("detect someone trying to write magic_number:0x%llx\n", fence->magic_number); + } } static void gf_dma_fence_release(dma_fence_t *base) @@ -143,6 +146,7 @@ static void *gf_dma_fence_create_cb(void *driver_, unsigned int engine_index, un fence->initialize_value = fence->value = initialize_value; fence->driver = driver; + fence->magic_number = 0; gf_get_nsecs(&fence->create_time); INIT_LIST_HEAD(&fence->link); dma_fence_init(&fence->base, &gf_dma_fence_ops, &context->lock, context->id, seq); @@ -391,6 +395,81 @@ static void gf_fence_dump(struct gf_dma_fence *fence) gf_info(" DmaFence %p baseid:%lld context:%lld value:%lld flags:0x%x\n", fence,fence->driver->base_context_id, fence->base.context, fence->value, fence->base.flags); } +void gf_check_touch_primary(void *_driver, void *_bo) +{ + struct drm_gf_gem_object *bo = (struct drm_gf_gem_object *)_bo; + struct gf_dma_fence_driver *driver = (struct gf_dma_fence_driver *)_driver; + gf_card_t *gf_card = driver->gf_card; + disp_info_t* disp_info = (disp_info_t *)gf_card->disp_info; + int i; + + for (i = 0; i < disp_info->num_crtc; i++) + { + if (bo && bo->info.gpu_virt_addr == gf_card->primary_addr[i]) + { + spin_lock(&driver->lock); + if (driver->primary_bo[i]) + { + gf_gem_object_put(driver->primary_bo[i]); + } + driver->primary_bo[i] = gf_gem_object_get(bo); + spin_unlock(&driver->lock); + //gf_info("try draw to bo %llx while it's used for flip in crtc %d\n", bo, i); + + gf_acquire_display(disp_info, DISP_ONSCREENDRAW_REF); + } + + } +} + +static void gf_touch_primary_done(struct gf_dma_fence_driver *driver) +{ + int i,j, fence_count = 0; + struct drm_gf_gem_object *bo = NULL; + dma_fence_t **fences = NULL; + int ret = 0; + gf_card_t *gf_card = driver->gf_card; + disp_info_t* disp_info = (disp_info_t *)gf_card->disp_info; + + for (i = 0; i < disp_info->num_crtc; i++) + { + bo = driver->primary_bo[i]; + if (bo && bo_resv(bo)) + { + int touch_primary_done = 1; + ret = reservation_get_fences(bo_resv(bo), 1, &fence_count, &fences); + gf_assert(ret == 0, ""); + + for (j = 0; j < fence_count; j++) + { + if (!gf_dma_fence_signaled(fences[j])) + { + touch_primary_done = 0; + } + dma_fence_put(fences[j]); + } + + if (touch_primary_done) + { + spin_lock(&driver->lock); + gf_gem_object_put(driver->primary_bo[i]); + driver->primary_bo[i] = NULL; + spin_unlock(&driver->lock); + //gf_info("draw to bo %llx in crtc %d has done\n", bo, i); + + gf_release_display(disp_info, DISP_ONSCREENDRAW_REF); + } + + if (fences) + { + kfree(fences); + fences = NULL; + fence_count = 0; + } + } + } +} + static long gf_dma_sync_object_wait_cb(void *driver, void *sync_obj_, unsigned long long timeout) { struct gf_dma_sync_object *sync_obj = sync_obj_; @@ -436,6 +515,10 @@ static gf_drm_callback_t gf_drm_callback = .gem = { .get_from_handle = gf_get_from_gem_handle, }, + + .kms = { + .check_touch_primary = gf_check_touch_primary, + }, }; static int gf_dma_fence_event_thread(void *data) @@ -451,6 +534,7 @@ static int gf_dma_fence_event_thread(void *data) do { ret = gf_thread_wait(driver->event, driver->timeout_msec); + gf_touch_primary_done(driver); try_again1: spin_lock(&driver->lock); @@ -565,11 +649,6 @@ int gf_dma_fence_driver_init(void *adapter, struct gf_dma_fence_driver *driver) INIT_LIST_HEAD(&driver->fence_list); driver->os_thread = gf_create_thread(gf_dma_fence_event_thread, driver, "dma_fenced"); - /** - * TODO: remove this - */ - fence_driver = driver; - return 0; } diff --git a/drivers/gpu/drm/arise/linux/gf_fence.h b/drivers/gpu/drm/arise/linux/gf_fence.h index 464907aed2b94..6c572327c327f 100644 --- a/drivers/gpu/drm/arise/linux/gf_fence.h +++ b/drivers/gpu/drm/arise/linux/gf_fence.h @@ -207,6 +207,7 @@ struct gf_dma_fence_driver; struct gf_dma_fence { + unsigned long long magic_number; struct gf_dma_fence_driver *driver; dma_fence_t base; unsigned long long initialize_value; @@ -241,6 +242,8 @@ struct gf_dma_fence_driver struct gf_dma_fence_context *context; struct kmem_cache *fence_slab; atomic_t fence_alloc_count; + gf_card_t *gf_card; + void* primary_bo[MAX_CORE_CRTCS]; }; #define gf_engine_by_fence(driver, fence) \ diff --git a/drivers/gpu/drm/arise/linux/gf_gem.c b/drivers/gpu/drm/arise/linux/gf_gem.c index 9b5eae89d8094..72ab6c5010efc 100644 --- a/drivers/gpu/drm/arise/linux/gf_gem.c +++ b/drivers/gpu/drm/arise/linux/gf_gem.c @@ -31,7 +31,11 @@ #include "os_interface.h" #if DRM_VERSION_CODE >= KERNEL_VERSION(5, 16, 0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 13, 0) MODULE_IMPORT_NS(DMA_BUF); +#else +MODULE_IMPORT_NS("DMA_BUF"); +#endif #endif extern struct os_pages_memory* gf_allocate_pages_memory_struct(int page_cnt, struct sg_table *st); diff --git a/drivers/gpu/drm/arise/linux/gf_gem_priv.h b/drivers/gpu/drm/arise/linux/gf_gem_priv.h index f3572ac41478b..e179785e8336c 100644 --- a/drivers/gpu/drm/arise/linux/gf_gem_priv.h +++ b/drivers/gpu/drm/arise/linux/gf_gem_priv.h @@ -51,6 +51,12 @@ typedef struct { #define to_gf_bo(gem) container_of(gem, struct drm_gf_gem_object, base) #define dmabuf_to_gf_bo(dmabuf) to_gf_bo((struct drm_gem_object*)((dmabuf)->priv)) +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) +#define bo_resv(bo) ((bo)->resv) +#else +#define bo_resv(bo) ((bo)->base.resv) +#endif + static inline unsigned int gf_gem_get_core_handle(gf_file_t *file, unsigned int handle) { struct drm_gem_object *gem; diff --git a/drivers/gpu/drm/arise/linux/gf_ioctl.c b/drivers/gpu/drm/arise/linux/gf_ioctl.c index 688dd22670968..ec51db18355d2 100644 --- a/drivers/gpu/drm/arise/linux/gf_ioctl.c +++ b/drivers/gpu/drm/arise/linux/gf_ioctl.c @@ -21,7 +21,6 @@ * IN THE SOFTWARE. * */ -#include "gf_def.h" #include "gf_ioctl.h" #include "os_interface.h" #include "kernel_interface.h" diff --git a/drivers/gpu/drm/arise/linux/gf_irq.c b/drivers/gpu/drm/arise/linux/gf_irq.c index 434208e7ba0d0..1a57fa5418605 100644 --- a/drivers/gpu/drm/arise/linux/gf_irq.c +++ b/drivers/gpu/drm/arise/linux/gf_irq.c @@ -406,6 +406,7 @@ void gf_disable_vblank(struct drm_device *dev, pipe_t pipe) } gf_spin_unlock_irqrestore(disp_info->intr_lock, flags); + } trace_gfx_vblank_onoff(gf_card->index << 16 | pipe, 0); @@ -1657,6 +1658,14 @@ void gf_video_interrupt_handle(disp_info_t* disp_info, unsigned int video_int_m ktime_t ctime = ktime_get(); if (output_all || video_irq_info_count[i] < DEFAULT_PRINT_COUNT) { + if (!output_all) + { + /* Ignore default be error info print. */ + if (5 == i || 7 == i) + { + continue; + } + } gf_info("*******************%s!*******************\n", video_irq_name[i]); if (i < 4) { diff --git a/drivers/gpu/drm/arise/linux/gf_kms.h b/drivers/gpu/drm/arise/linux/gf_kms.h index 56406d5d4681f..8baf4aac9b23e 100644 --- a/drivers/gpu/drm/arise/linux/gf_kms.h +++ b/drivers/gpu/drm/arise/linux/gf_kms.h @@ -48,7 +48,11 @@ #endif #if DRM_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 13, 0) #include +#else +#include +#endif #endif #if DRM_VERSION_CODE >= KERNEL_VERSION(5, 5, 0) diff --git a/drivers/gpu/drm/arise/linux/gf_params.c b/drivers/gpu/drm/arise/linux/gf_params.c index 54bc90997a68e..fcc52e326b77c 100644 --- a/drivers/gpu/drm/arise/linux/gf_params.c +++ b/drivers/gpu/drm/arise/linux/gf_params.c @@ -31,7 +31,7 @@ struct gf_params gf_modparams __read_mostly = { #else .gf_fb = 1, #endif - .gf_pwm_mode = 0x1, + .gf_pwm_mode = 0x101, .gf_dfs_mode = 0, .gf_worker_thread_enable = 1, .gf_recovery_enable = 1, diff --git a/drivers/gpu/drm/arise/linux/gf_pcie.c b/drivers/gpu/drm/arise/linux/gf_pcie.c index 0e9d1bcf89b99..db7cd788f5401 100644 --- a/drivers/gpu/drm/arise/linux/gf_pcie.c +++ b/drivers/gpu/drm/arise/linux/gf_pcie.c @@ -47,13 +47,32 @@ #include #if DRM_VERSION_CODE >= KERNEL_VERSION(6, 2, 0) -#if DRM_VERSION_CODE < KERNEL_VERSION(6,11,0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 11, 0) #include #else +#if DRM_VERSION_CODE >= KERNEL_VERSION(6, 13, 0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 14, 0) +#include +#else +#include +#endif +#endif #include #endif #endif +#if DRM_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 13, 0) +#include +#else +#include +#endif +#endif + +#if defined(__loongarch__) && defined(KYLIN) && DRM_VERSION_CODE == KERNEL_VERSION(6, 6, 0) +#include +#endif + #define DRIVER_DESC "Glenfly DRM Pro" #define ROM_IMAGE_HEADER 0xaa55 @@ -91,6 +110,7 @@ static struct pci_device_id pciidlist[] = {0x6766, 0x3D06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&gf_e3k_info}, //arise10c0t {0x6766, 0x3D07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&gf_e3k_info}, {0x6766, 0x3D08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&gf_e3k_info}, + {0x6766, 0x3D0E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (kernel_ulong_t)&gf_e3k_info}, //arise10D0 {0, 0, 0} }; @@ -411,7 +431,22 @@ static int gf_drm_load_kms(struct drm_device *dev, unsigned long flags) gf->pdev = pdev; #if DRM_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 13, 0) + +#if defined(__loongarch__) && defined(KYLIN) && DRM_VERSION_CODE == KERNEL_VERSION(6, 6, 0) + //NOTE: add patch here to resolve firmware fb remove failure for old firmware on loongarch64 platform. + // gop fb address issue has been fixed from firmware 03000014 version. + // now only patch for KylinV11 which use kernel verion 6.6.0 + if (vga_default_device() == pdev) + { + sysfb_disable(NULL); + } +#endif + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, (const struct drm_driver *)&gf_drm_driver.base); +#else + ret = aperture_remove_conflicting_pci_devices(pdev, gf_drm_driver.base.name); +#endif #elif DRM_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "arisedrmfb"); #else @@ -451,6 +486,7 @@ static int gf_drm_load_kms(struct drm_device *dev, unsigned long flags) } gf->fence_drv = gf_calloc(sizeof(struct gf_dma_fence_driver)); + gf->fence_drv->gf_card = gf; gf_dma_fence_driver_init(gf->adapter, gf->fence_drv); @@ -699,7 +735,7 @@ static struct file_operations gf_drm_fops = { .read = drm_read, .poll = drm_poll, .llseek = noop_llseek, -#if DRM_VERSION_CODE >= KERNEL_VERSION(6, 11, 0) +#if DRM_VERSION_CODE >= KERNEL_VERSION(6, 12, 0) .fop_flags = FOP_UNSIGNED_OFFSET, #endif }; @@ -734,7 +770,9 @@ static struct drm_gf_driver gf_drm_driver = { #endif .postclose = gf_drm_postclose, + #if DRM_VERSION_CODE < KERNEL_VERSION(6,12,0) .lastclose = gf_drm_last_close, + #endif .ioctls = gf_ioctls, .num_ioctls = ioctl_nr_total_num, #if DRM_VERSION_CODE < KERNEL_VERSION(4,14,0) && DRM_VERSION_CODE >= KERNEL_VERSION(3,18,0) @@ -756,6 +794,10 @@ static struct drm_gf_driver gf_drm_driver = { .gem_vm_ops = &gf_gem_vm_ops, #endif + #if DRM_VERSION_CODE >= KERNEL_VERSION(6, 13, 0) + DRM_FBDEV_TTM_DRIVER_OPS, + #endif + #if DRM_VERSION_CODE < KERNEL_VERSION(5, 11, 0) .gem_prime_vmap = gf_gem_prime_vmap, .gem_prime_vunmap = gf_gem_prime_vunmap, @@ -794,7 +836,9 @@ static struct drm_gf_driver gf_drm_driver = { #endif .name = STR(DRIVER_NAME), .desc = DRIVER_DESC, + #if DRM_VERSION_CODE < KERNEL_VERSION(6, 14, 0) .date = DRIVER_DATE, + #endif .major = DRIVER_MAJOR, .minor = DRIVER_MINOR, .patchlevel = DRIVER_PATCHLEVEL, @@ -845,8 +889,10 @@ static int gf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *ent) #if DRM_VERSION_CODE < KERNEL_VERSION(6, 11, 0) drm_fbdev_generic_setup(dev, 32); -#else +#elif DRM_VERSION_CODE < KERNEL_VERSION(6, 13, 0) drm_fbdev_ttm_setup(dev, 32); +#else + drm_client_setup(dev, NULL); #endif #if DRM_VERSION_CODE < KERNEL_VERSION(5, 2, 0) @@ -1083,6 +1129,7 @@ static void gf_shutdown(struct pci_dev *pdev) gf_info("pci device(vendor:0x%X, device:0x%X) shutting down.\n", pdev->vendor, pdev->device); + gf->flags |= GF_SHUT_DOWN; gf_core_interface->wait_chip_idle(gf->adapter); #if DRM_VERSION_CODE >= KERNEL_VERSION(4, 8, 0) diff --git a/drivers/gpu/drm/arise/linux/gf_plane.c b/drivers/gpu/drm/arise/linux/gf_plane.c index aeaeb49d6bd07..bbf9fb0147f4a 100644 --- a/drivers/gpu/drm/arise/linux/gf_plane.c +++ b/drivers/gpu/drm/arise/linux/gf_plane.c @@ -22,6 +22,7 @@ * */ #include "gf_plane.h" +#include "gf_disp.h" #include "gf_drmfb.h" #include "gf_fence.h" #include "gf_modifies.h" @@ -50,6 +51,8 @@ int gf_atomic_helper_update_plane(struct drm_plane *plane, { struct drm_plane_state* plane_state = plane->state; const struct drm_plane_helper_funcs *funcs; + gf_card_t *gf_card = (gf_card_t *)plane->dev->dev_private; + disp_info_t *disp_info = (disp_info_t *)gf_card->disp_info; gf_assert(!!crtc == !!fb, GF_FUNC_NAME(__func__)); @@ -62,6 +65,8 @@ int gf_atomic_helper_update_plane(struct drm_plane *plane, #endif } + gf_acquire_display(disp_info, DISP_CURSOR_REF); + plane_state->crtc = crtc; if(crtc->state) { @@ -97,6 +102,8 @@ int gf_atomic_helper_update_plane(struct drm_plane *plane, plane->old_fb = plane->fb; + gf_release_display(disp_info, DISP_CURSOR_REF); + return 0; } @@ -651,8 +658,9 @@ bool gf_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, case DRM_FORMAT_MOD_GF_TILED_COMPRESS: case DRM_FORMAT_MOD_GF_LOCAL: case DRM_FORMAT_MOD_GF_PCIE: + case DRM_FORMAT_MOD_GF_RB_ALT: case DRM_FORMAT_MOD_GF_INVALID: - /* TODO: should do something? */ + /* TODO: should do something after sync? */ ret = true; goto check_done; default: diff --git a/drivers/gpu/drm/arise/linux/gf_splice.c b/drivers/gpu/drm/arise/linux/gf_splice.c index 24a547173946a..cffae2e177558 100644 --- a/drivers/gpu/drm/arise/linux/gf_splice.c +++ b/drivers/gpu/drm/arise/linux/gf_splice.c @@ -585,13 +585,16 @@ static int gf_splice_update_plane(struct drm_plane *plane, struct drm_plane_state* plane_state = plane->state; const struct drm_plane_helper_funcs *funcs; + gf_card_t *gf_card = (gf_card_t *)plane->dev->dev_private; + disp_info_t *disp_info = (disp_info_t *)gf_card->disp_info; if (to_gf_plane(plane)->is_cursor == 0) { - //TODO: iter the plane return drm_atomic_helper_update_plane(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h, ctx); } + gf_acquire_display(disp_info, DISP_CURSOR_REF); + plane_state->crtc = crtc; if(crtc->state) { @@ -626,8 +629,9 @@ static int gf_splice_update_plane(struct drm_plane *plane, plane->old_fb = plane->fb; - return 0; + gf_release_display(disp_info, DISP_CURSOR_REF); + return 0; } static int gf_splice_disable_plane(struct drm_plane *plane, struct drm_modeset_acquire_ctx *ctx) @@ -1154,9 +1158,7 @@ static int gf_splice_crtc_page_flip(struct drm_crtc *crtc, static struct drm_crtc_state* gf_splice_crtc_duplicate_state(struct drm_crtc *crtc) { - gf_crtc_state_t* crtc_state, *cur_crtc_state; - - cur_crtc_state = to_gf_crtc_state(crtc->state); + gf_crtc_state_t* crtc_state; crtc_state = gf_calloc(sizeof(gf_crtc_state_t)); if (!crtc_state) @@ -1654,7 +1656,18 @@ static void gf_splice_crtc_dpms_onoff_helper(struct drm_crtc *crtc, int dpms_on) continue; } - disp_cbios_turn_onoff_screen(disp_info, gf_source_crtc->pipe, status); + if(!status) + { + //turn off + disp_cbios_turn_onoff_screen(disp_info, gf_source_crtc->pipe, 0); + disp_cbios_turn_onoff_iga(disp_info, gf_source_crtc->pipe, 0); + } + else if(status) + { + //turn on + disp_cbios_turn_onoff_iga(disp_info, gf_source_crtc->pipe, 1); + disp_cbios_turn_onoff_screen(disp_info, gf_source_crtc->pipe, 1); + } } gf_crtc->crtc_dpms = status; diff --git a/drivers/gpu/drm/arise/linux/gf_sysfs.c b/drivers/gpu/drm/arise/linux/gf_sysfs.c index a6c3ce7c4e5c4..6331b3a82d56e 100644 --- a/drivers/gpu/drm/arise/linux/gf_sysfs.c +++ b/drivers/gpu/drm/arise/linux/gf_sysfs.c @@ -72,20 +72,22 @@ static ssize_t gf_enable_usage_store(struct device *dev,struct device_attribute struct pci_dev* pdev = container_of(dev,struct pci_dev,dev); struct drm_device* drm_dev = pci_get_drvdata(pdev); gf_card_t* gf_card = drm_dev->dev_private; - + unsigned int power_state; unsigned long value = 0; + + ret = gf_core_interface->get_power_state(gf_card->adapter, &power_state); + if (ret == 0) + return -EPERM; + ret = kstrtoul(buf, 0, &value); - if(ret < 0) - { + if (ret < 0) return ret; - } - value = (value==0)? 0:1; - gf_core_interface->ctl_flags_set(gf_card->adapter,1,(1UL<<16),(value<<16)); //First Int Bit16 hwq_event_enable - if(value) - { - gf_core_interface->ctl_flags_set(gf_card->adapter,1,(1UL<<9),(value<<9)); //First Int Bit11, perf_event_enable - } + value = (value == 0) ? 0 : 1; + gf_core_interface->ctl_flags_set(gf_card->adapter, 1, (1UL << 16), (value << 16)); //First Int Bit16 hwq_event_enable + if (value) + gf_core_interface->ctl_flags_set(gf_card->adapter, 1, (1UL << 9), (value << 9)); //First Int Bit11, perf_event_enable + return len; } @@ -95,20 +97,22 @@ static ssize_t gf_enable_perf_store(struct device *dev,struct device_attribute * struct pci_dev* pdev = container_of(dev,struct pci_dev,dev); struct drm_device* drm_dev = pci_get_drvdata(pdev); gf_card_t* gf_card = drm_dev->dev_private; - + unsigned int power_state; unsigned long value = 0; + + ret = gf_core_interface->get_power_state(gf_card->adapter, &power_state); + if (ret == 0) + return -EPERM; + ret = kstrtoul(buf, 0, &value); - if(ret < 0) - { + if (ret < 0) return ret; - } - value = (value==0)? 0:1; - gf_core_interface->ctl_flags_set(gf_card->adapter,1,(1UL<<9),(value<<9)); //First Int Bit11 perf_event_enable - if(value==0) - { - gf_core_interface->ctl_flags_set(gf_card->adapter,1,(1UL<<16),(value<<16)); //First Int Bit16 hwq_event_enable - } + value = (value == 0) ? 0 : 1; + gf_core_interface->ctl_flags_set(gf_card->adapter, 1, (1UL << 9), (value << 9)); //First Int Bit11 perf_event_enable + if (value == 0) + gf_core_interface->ctl_flags_set(gf_card->adapter, 1, (1UL << 16), (value << 16)); //First Int Bit16 hwq_event_enable + return len; } @@ -623,6 +627,42 @@ static ssize_t gf_task_timeout_store(struct device *dev, struct device_attribute return len; } +static ssize_t gf_power_state_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct pci_dev* pdev = container_of(dev,struct pci_dev,dev); + struct drm_device* drm_dev = pci_get_drvdata(pdev); + gf_card_t* gf_card = drm_dev->dev_private; + unsigned int level = 0; + int ret; + + ret = gf_core_interface->get_power_state(gf_card->adapter, &level); + if (ret) + return -EPERM; + + return sprintf(buf, "E%u\n", level); +} + +static ssize_t gf_power_state_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) +{ + struct pci_dev* pdev = container_of(dev,struct pci_dev,dev); + struct drm_device* drm_dev = pci_get_drvdata(pdev); + gf_card_t* gf_card = drm_dev->dev_private; + unsigned int level = 0; + int ret; + + ret = sscanf(buf, "%u", &level); + if (ret <= 0) + return -EINVAL; + + ret = gf_core_interface->set_power_state(gf_card->adapter, level, 300, TRUE, TRUE, TRUE); + if (ret) + return -EPERM; + + gf_debug("trying to fix power state.\n"); + + return len; +} + static ssize_t gf_firmware_version_show(struct device *dev, struct device_attribute *attr, char *buf) { struct pci_dev* pdev = container_of(dev,struct pci_dev,dev); @@ -662,6 +702,7 @@ GF_DEVICE_ATTR_RW(misc_ctl_flag); GF_DEVICE_ATTR_RO(segment_info); GF_DEVICE_ATTR_RW(task_timeout); GF_DEVICE_ATTR_RO(firmware_version); +GF_DEVICE_ATTR_RW(power_state); static struct attribute *gf_info_attributes[] = { &dev_attr_string.attr, @@ -692,6 +733,7 @@ static struct attribute *gf_info_attributes[] = { &dev_attr_segment_info.attr, &dev_attr_task_timeout.attr, &dev_attr_firmware_version.attr, + &dev_attr_power_state.attr, NULL }; @@ -791,9 +833,15 @@ static const struct vm_operations_struct gf_sysfs_trace_vmops = { extern unsigned char gf_validate_page_cache(struct os_pages_memory *memory, int start_page, int end_page, unsigned char request_cache_type); +#if DRM_VERSION_CODE < KERNEL_VERSION(6, 13, 0) static int gf_sysfs_trace_mmap(struct file *filp, struct kobject *kobj, struct bin_attribute *attr, struct vm_area_struct *vma) +#else +static int gf_sysfs_trace_mmap(struct file *filp, struct kobject *kobj, + const struct bin_attribute *attr, + struct vm_area_struct *vma) +#endif { struct pci_dev* pdev = to_pci_dev(container_of(kobj,struct device,kobj)); struct drm_device* drm_dev = pci_get_drvdata(pdev); diff --git a/drivers/gpu/drm/arise/linux/os_interface.c b/drivers/gpu/drm/arise/linux/os_interface.c index 0b0625317ecbe..7320d40db3cc5 100644 --- a/drivers/gpu/drm/arise/linux/os_interface.c +++ b/drivers/gpu/drm/arise/linux/os_interface.c @@ -489,6 +489,35 @@ void GF_API_CALL gf_cb_printk(const char* msg) } } +void GF_API_CALL gf_cb_vdbgprint(int enable, unsigned int print_level, const char* prefix, const char* msg, ...) +{ + char buffer[256]; + va_list args; + unsigned int prefix_len = 0; + + UNUSED(print_level); + + if(!enable) + { + return; + } + + if(prefix) + { + prefix_len = gf_strlen((char*)prefix); + gf_strncpy(buffer, prefix, prefix_len); + } + + va_start(args, msg); + + vsnprintf(buffer+prefix_len, 256-prefix_len, msg, args); + + va_end(args); + + printk("%s", buffer); +} + + void GF_API_CALL gf_printk(unsigned int msglevel, const char* fmt, ...) { char buffer[256]; @@ -1139,6 +1168,7 @@ void gf_get_current_pname(char *pname, int size) gf_strncpy(pname, buf, size); } +#if defined(__mips64__) || defined(__loongarch__) void gf_dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction) { unsigned long long len; @@ -1147,15 +1177,15 @@ void gf_dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_da #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) dma_cache_sync(dev, vaddr, size, direction); #elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 19, 0) -#if defined(__mips64__) || defined(__loongarch__) for (len = 0; len < size; len += PAGE_SIZE) { flush_data_cache_page(addr); addr += PAGE_SIZE; } #endif -#endif + } +#endif static void gf_flush_page_cache(struct device *dev, struct page *pages, unsigned int flush_size) { @@ -1181,8 +1211,10 @@ static void gf_flush_page_cache(struct device *dev, struct page *pages, unsigned #if __ARM_ARCH >= 8 flush_icache_range((unsigned long)ptr, (unsigned long)(ptr+PAGE_SIZE)); #else +#if !defined(__riscv) dmac_flush_range(ptr, ptr + PAGE_SIZE); outer_flush_range(page_to_phys(pages), page_to_phys(pages) + PAGE_SIZE); +#endif #endif kunmap(pages); pages++; @@ -1752,8 +1784,10 @@ void gf_flush_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memor #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)(ptr + page_start_offset), (unsigned long)(ptr + page_end_offset)); #else +#if !defined(__riscv) dmac_flush_range(ptr + page_start_offset, ptr + page_end_offset); outer_flush_range(page_to_phys(pages) + page_start_offset, page_to_phys(pages) + page_end_offset); +#endif #endif kunmap(pages); } @@ -1766,8 +1800,10 @@ void gf_flush_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memor #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)(ptr + page_start_offset), (unsigned long)(ptr + PAGE_SIZE)); #else +#if !defined(__riscv) dmac_flush_range(ptr + page_start_offset, ptr + PAGE_SIZE); outer_flush_range(page_to_phys(pages) + page_start_offset, page_to_phys(pages) + PAGE_SIZE); +#endif #endif kunmap(pages); @@ -1778,8 +1814,10 @@ void gf_flush_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memor #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)ptr, (unsigned long)(ptr + page_end_offset)); #else +#if !defined(__riscv) dmac_flush_range(ptr, ptr + PAGE_SIZE); outer_flush_range(page_to_phys(pages), page_to_phys(pages) + page_end_offset); +#endif #endif kunmap(pages); } @@ -1793,8 +1831,10 @@ void gf_flush_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memor #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)ptr, (unsigned long)(ptr + PAGE_SIZE)); #else +#if !defined(__riscv) dmac_flush_range(ptr, ptr + PAGE_SIZE); outer_flush_range(page_to_phys(pages), page_to_phys(pages) + PAGE_SIZE); +#endif #endif kunmap(pages); } @@ -1838,8 +1878,10 @@ void gf_inv_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memory, #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)(ptr + page_start_offset), (unsigned long)(ptr + page_end_offset)); #else +#if !defined(__riscv) dmac_flush_range(ptr + page_start_offset, ptr + page_end_offset); outer_inv_range(page_to_phys(pages) + page_start_offset, page_to_phys(pages) + page_end_offset); +#endif #endif kunmap(pages); } @@ -1852,8 +1894,10 @@ void gf_inv_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memory, #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)(ptr + page_start_offset), (unsigned long)(ptr + PAGE_SIZE)); #else +#if !defined(__riscv) dmac_flush_range(ptr + page_start_offset, ptr + PAGE_SIZE); outer_inv_range(page_to_phys(pages) + page_start_offset, page_to_phys(pages) + PAGE_SIZE); +#endif #endif kunmap(pages); @@ -1864,8 +1908,10 @@ void gf_inv_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memory, #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)ptr, (unsigned long)(ptr + PAGE_SIZE)); #else +#if !defined(__riscv) dmac_flush_range(ptr, ptr + PAGE_SIZE); outer_inv_range(page_to_phys(pages), page_to_phys(pages) + page_end_offset); +#endif #endif kunmap(pages); } @@ -1879,8 +1925,10 @@ void gf_inv_cache(void *pdev, gf_vm_area_t *vma, struct os_pages_memory* memory, #elif __ARM_ARCH >= 8 flush_icache_range((unsigned long)ptr, (unsigned long)(ptr + PAGE_SIZE)); #else +#if !defined(__riscv) dmac_flush_range(ptr, ptr + PAGE_SIZE); outer_inv_range(page_to_phys(pages), page_to_phys(pages) + PAGE_SIZE); +#endif #endif kunmap(pages); } @@ -2050,35 +2098,15 @@ int gf_query_platform_caps(void *pdev, platform_caps_t *caps) caps->dcache_type = GF_CPU_CACHE_UNKNOWN; #endif -#if defined(CONFIG_IOMMU_SUPPORT) - caps->iommu_support = iommu_present(&platform_bus_type) || -#ifdef CONFIG_ARM_AMBA - iommu_present(&amba_bustype) || -#endif - iommu_present(&pci_bus_type); -#if defined(CONFIG_ARM_GIC_PHYTIUM_2500) - caps->iommu_support = FALSE; -#endif -#else - caps->iommu_support = FALSE; -#endif + caps->iommu_support = TRUE; caps->page_size = PAGE_SIZE; caps->page_shift = PAGE_SHIFT; - /*for (mem_res = iomem_resource.child; mem_res; mem_res = mem_res->sibling) - { - if (mem_res->name && (!gf_strcmp(mem_res->name, "System RAM")) && (mem_res->end > max_physical_addr)) - max_physical_addr = mem_res->end; - } - - - if (BITS_PER_LONG == 64 && !caps->iommu_support && max_physical_addr >= (1ULL << 36)) - { - caps->system_need_dma32 = TRUE; - }*/ - - caps->system_need_dma32 = caps->iommu_support ? FALSE : dma_get_required_mask(device) > DMA_BIT_MASK(40); + caps->system_need_dma32 = dma_get_required_mask(device) > DMA_BIT_MASK(40); +#if defined(__loongarch__) + caps->system_need_dma32 = FALSE; +#endif #if defined(__i386__) || defined(__x86_64__) #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) @@ -2338,7 +2366,7 @@ int gf_disp_wait_idle(void *disp_info) #define gf_wmb_asm() wmb() #define gf_flush_wc_asm() mb() #define gf_dsb_asm() -#else +#elif defined(__aarch64__) #if __ARM_ARCH >= 7 #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") @@ -2349,6 +2377,12 @@ int gf_disp_wait_idle(void *disp_info) #define gf_flush_wc_asm() dsb(sy) #define gf_dsb_asm() dsb(sy) #endif +#elif defined(__riscv) +#define gf_mb_asm() +#define gf_rmb_asm() +#define gf_wmb_asm() +#define gf_flush_wc_asm() +#define gf_dsb_asm() #endif void gf_mb(void) diff --git a/drivers/gpu/drm/arise/shared/gf_def.h b/drivers/gpu/drm/arise/shared/gf_def.h index 13ce9d6f4a44e..8efbe11e54052 100644 --- a/drivers/gpu/drm/arise/shared/gf_def.h +++ b/drivers/gpu/drm/arise/shared/gf_def.h @@ -486,4 +486,4 @@ typedef struct gf_process_allocation_t alloc_info[KERNAL_NORMAT_ARRAY_MAX]; unsigned int alloc_num; } gf_process_base_t; -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/arise/shared/gf_types.h b/drivers/gpu/drm/arise/shared/gf_types.h index d89ca886ef9a9..57f9c8259c629 100644 --- a/drivers/gpu/drm/arise/shared/gf_types.h +++ b/drivers/gpu/drm/arise/shared/gf_types.h @@ -120,6 +120,7 @@ typedef enum GF_FORMAT_S8_UINT = 35, GF_FORMAT_B8G8R8A8_SRGB = 36, + GF_FORMAT_AYUV_VIDEO = 37, }gf_format; typedef struct diff --git a/drivers/gpu/drm/arise/shared/os_interface.h b/drivers/gpu/drm/arise/shared/os_interface.h index 5caf0c29c49a4..7ce397de3f5b9 100644 --- a/drivers/gpu/drm/arise/shared/os_interface.h +++ b/drivers/gpu/drm/arise/shared/os_interface.h @@ -121,6 +121,8 @@ extern int GF_API_CALL gf_sscanf(char *buf, char *fmt, ...); extern void GF_API_CALL gf_printk(unsigned int msglevel, const char* fmt, ...); extern void GF_API_CALL gf_cb_printk(const char* msg); +extern void GF_API_CALL gf_cb_vdbgprint(int enable, unsigned int print_level, const char* prefix, const char* msg, ...); + #ifdef _DEBUG_ #define GF_MSG_LEVEL GF_DRV_DEBUG