feat!: Gate pipeline deserialization through a module allowlist #11432

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft

bogdankostic wants to merge 5 commits into v3 from yaml_deserialization

Draft

feat!: Gate pipeline deserialization through a module allowlist #11432

honor fnmatch patterns on module prefixes in the deserialization allo…

Vercel / Vercel Preview Comments succeeded May 30, 2026 in 0s

✅ No unresolved feedback

💬 0 unresolved, 0 resolved.

View more details on Vercel