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[AArch64] fuse constant addition after sbb (llvm#185117)
Resolves: llvm#171676 Related: llvm#184541 (x86_64 PR) The issue points out that `Fold ADD(ADC(Y,0,W),X) -> ADC(X,Y,W)` is optimized and that SBB can be optimized similarly: `Fold ADD(SBB(Y,0,W),C) -> SBB(Y,-C,W)`. With the changes from this branch, a new clang will compile the example code: ``` #include <stdint.h> uint64_t f(uint64_t a, uint64_t b) { uint64_t x; x += __builtin_add_overflow(a, b, &x); return x + 10; } uint64_t g(uint64_t a, uint64_t b) { uint64_t x; x -= __builtin_sub_overflow(a, b, &x); return x + 10; } ``` To this, so the subc case matches the add case. ``` f: mov w8, llvm#10 adds x9, x0, x1 adc x0, x9, x8 ret g: mov x8, #-10 subs x9, x0, x1 sbc x0, x9, x8 ret ```
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Lines changed: 172 additions & 1 deletion

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23365,6 +23365,31 @@ static SDValue performAddTruncShiftCombine(SDNode *N, SelectionDAG &DAG) {
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return DAG.getNode(ISD::ADD, DL, VT, Trunc, Shift);
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}
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// Fold ADD(SBC(Y, 0, W), C) -> SBC(Y, -C, W)
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// SBC(Y, 0, W) = Y - 0 - ~carry = Y + carry - 1
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// Adding C: Y + carry - 1 + C = Y - (-C) - ~carry = SBC(Y, -C, W)
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static SDValue performAddWithSBCCombine(SDNode *N, SelectionDAG &DAG) {
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if (N->getOpcode() != ISD::ADD)
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return SDValue();
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EVT VT = N->getValueType(0);
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if (VT != MVT::i32 && VT != MVT::i64)
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return SDValue();
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SDValue SBC = N->getOperand(0);
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SDValue C = N->getOperand(1);
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// ADD is commutative; operands may be on either side.
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if (SBC.getOpcode() != AArch64ISD::SBC)
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std::swap(SBC, C);
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if (SBC.getOpcode() != AArch64ISD::SBC || !SBC.hasOneUse())
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return SDValue();
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if (!isNullConstant(SBC.getOperand(1)))
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return SDValue();
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// AArch64 SBC (non-flag-setting) has only one output; no flags guard needed.
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SDLoc DL(N);
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return DAG.getNode(AArch64ISD::SBC, DL, VT, SBC.getOperand(0),
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DAG.getNegative(C, DL, VT), SBC.getOperand(2));
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}
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static SDValue performAddSubCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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// Try to change sum of two reductions.
@@ -23390,7 +23415,8 @@ static SDValue performAddSubCombine(SDNode *N,
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return Val;
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if (SDValue Val = performAddTruncShiftCombine(N, DCI.DAG))
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return Val;
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23418+
if (SDValue Val = performAddWithSBCCombine(N, DCI.DAG))
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return Val;
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if (SDValue Val = performExtBinopLoadFold(N, DCI.DAG))
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return Val;
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‎llvm/test/CodeGen/AArch64/sbc-add-constant.ll‎

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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;
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; Verify that ADD(SBB(Y,0,flags),C) folds to SBB(Y,-C,flags).
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; SBB(Y,0) = Y - CF; adding C gives Y - CF + C = Y - (-C) - CF = SBB(Y,-C).
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; Fold should fire, adding with constant
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define i64 @g_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: g_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #-10 // =0xfffffffffffffff6
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; CHECK-NEXT: subs x9, x0, x1
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; CHECK-NEXT: sbc x0, x9, x8
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; CHECK-NEXT: ret
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%ov = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %ov, 0
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%bit = extractvalue { i64, i1 } %ov, 1
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%ext = sext i1 %bit to i64
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%r = add i64 %val, %ext
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%r2 = add i64 %r, 10
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ret i64 %r2
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}
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; Fold should fire, adding with constant
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define i32 @g_i32(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: g_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
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; CHECK-NEXT: subs w9, w0, w1
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; CHECK-NEXT: sbc w0, w9, w8
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; CHECK-NEXT: ret
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%ov = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %ov, 0
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%bit = extractvalue { i32, i1 } %ov, 1
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%ext = sext i1 %bit to i32
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%r = add i32 %val, %ext
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%r2 = add i32 %r, 10
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ret i32 %r2
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}
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; Fold should fire for non-constant addend too
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define i64 @g_nonconstant(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: g_nonconstant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg x8, x2
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; CHECK-NEXT: subs x9, x0, x1
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; CHECK-NEXT: sbc x0, x9, x8
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; CHECK-NEXT: ret
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%ov = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %ov, 0
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%bit = extractvalue { i64, i1 } %ov, 1
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%ext = sext i1 %bit to i64
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%r = add i64 %val, %ext
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%r2 = add i64 %r, %c
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ret i64 %r2
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}
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; Fold should fire for non-constant addend too
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define i32 @g_nonconstant_i32(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: g_nonconstant_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w2
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; CHECK-NEXT: subs w9, w0, w1
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; CHECK-NEXT: sbc w0, w9, w8
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; CHECK-NEXT: ret
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%ov = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %ov, 0
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%bit = extractvalue { i32, i1 } %ov, 1
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%ext = sext i1 %bit to i32
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%r = add i32 %val, %ext
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%r2 = add i32 %r, %c
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ret i32 %r2
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}
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; Fold should fire for non-constant addend in commuted form too
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define i64 @g_nonconstant_commuted(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: g_nonconstant_commuted:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg x8, x2
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; CHECK-NEXT: subs x9, x0, x1
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; CHECK-NEXT: sbc x0, x9, x8
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; CHECK-NEXT: ret
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%ov = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %ov, 0
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%bit = extractvalue { i64, i1 } %ov, 1
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%ext = sext i1 %bit to i64
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%r = add i64 %val, %ext
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%r2 = add i64 %c, %r
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ret i64 %r2
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}
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; Fold should fire for non-constant addend in commuted form too
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define i32 @g_nonconstant_commuted_i32(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: g_nonconstant_commuted_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w8, w2
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; CHECK-NEXT: subs w9, w0, w1
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; CHECK-NEXT: sbc w0, w9, w8
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; CHECK-NEXT: ret
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%ov = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
101+
%val = extractvalue { i32, i1 } %ov, 0
102+
%bit = extractvalue { i32, i1 } %ov, 1
103+
%ext = sext i1 %bit to i32
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%r = add i32 %val, %ext
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%r2 = add i32 %c, %r
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ret i32 %r2
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}
108+
109+
; Multiple uses of SBC result should not generate the fold
110+
define i64 @g_multi_use(i64 %a, i64 %b, ptr %out) nounwind {
111+
; CHECK-LABEL: g_multi_use:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: sbc x8, x8, xzr
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; CHECK-NEXT: add x0, x8, #10
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; CHECK-NEXT: str x8, [x2]
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; CHECK-NEXT: ret
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%ov = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %ov, 0
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%bit = extractvalue { i64, i1 } %ov, 1
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%ext = sext i1 %bit to i64
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%sbc = add i64 %val, %ext
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store i64 %sbc, ptr %out
124+
%r = add i64 %sbc, 10
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ret i64 %r
126+
}
127+
128+
; Multiple uses of SBC result should not generate the fold
129+
define i32 @g_multi_use_i32(i32 %a, i32 %b, ptr %out) nounwind {
130+
; CHECK-LABEL: g_multi_use_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: sbc w8, w8, wzr
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; CHECK-NEXT: add w0, w8, #10
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%ov = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %ov, 0
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%bit = extractvalue { i32, i1 } %ov, 1
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%ext = sext i1 %bit to i32
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%sbc = add i32 %val, %ext
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store i32 %sbc, ptr %out
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%r = add i32 %sbc, 10
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ret i32 %r
145+
}

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