[AArch64] Add vector expansion support for ISD::FPOW when using ArmPL (llvm#183526)

david-arm · web-flow · commit 9e95cff5155a · 2026-02-27T09:43:05.000Z
This patch is split off from PR llvm#183319 and teaches the backend how to lower the FPOW DAG node to the vector math library function when using ArmPL. This is similar to what we already do for llvm.sincos/FSINCOS today.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -1318,6 +1318,15 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
     // scalarizing.
     break;
   }
+  case ISD::FPOW: {
+    RTLIB::Libcall LC = RTLIB::getPOW(Node->getValueType(0));
+    if (tryExpandVecMathCall(Node, LC, Results))
+      return;
+
+    // TODO: Try to see if there's a narrower call available to use before
+    // scalarizing.
+    break;
+  }
   case ISD::FMODF: {
     EVT VT = Node->getValueType(0);
     RTLIB::Libcall LC = RTLIB::getMODF(VT);
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -539,6 +539,24 @@ RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) {
 }
 
 RTLIB::Libcall RTLIB::getPOW(EVT RetVT) {
+  // TODO: Tablegen should generate this function
+  if (RetVT.isVector()) {
+    if (!RetVT.isSimple())
+      return RTLIB::UNKNOWN_LIBCALL;
+    switch (RetVT.getSimpleVT().SimpleTy) {
+    case MVT::v4f32:
+      return RTLIB::POW_V4F32;
+    case MVT::v2f64:
+      return RTLIB::POW_V2F64;
+    case MVT::nxv4f32:
+      return RTLIB::POW_NXV4F32;
+    case MVT::nxv2f64:
+      return RTLIB::POW_NXV2F64;
+    default:
+      return RTLIB::UNKNOWN_LIBCALL;
+    }
+  }
+
   return getFPLibCall(RetVT, POW_F32, POW_F64, POW_F80, POW_F128, POW_PPCF128);
 }
 
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -65,12 +65,15 @@ RuntimeLibcallsInfo::RuntimeLibcallsInfo(const Triple &TT,
           RTLIB::impl_armpl_svsincos_f64_x, RTLIB::impl_armpl_svsincos_f32_x,
           RTLIB::impl_armpl_vsincospiq_f32, RTLIB::impl_armpl_vsincospiq_f64,
           RTLIB::impl_armpl_svsincospi_f32_x,
-          RTLIB::impl_armpl_svsincospi_f64_x})
+          RTLIB::impl_armpl_svsincospi_f64_x, RTLIB::impl_armpl_svpow_f32_x,
+          RTLIB::impl_armpl_svpow_f64_x, RTLIB::impl_armpl_vpowq_f32,
+          RTLIB::impl_armpl_vpowq_f64})
       setAvailable(Impl);
 
     for (RTLIB::LibcallImpl Impl :
          {RTLIB::impl_armpl_vfmodq_f32, RTLIB::impl_armpl_vfmodq_f64,
-          RTLIB::impl_armpl_vsincosq_f64, RTLIB::impl_armpl_vsincosq_f32})
+          RTLIB::impl_armpl_vsincosq_f64, RTLIB::impl_armpl_vsincosq_f32,
+          RTLIB::impl_armpl_vpowq_f32, RTLIB::impl_armpl_vpowq_f64})
       setLibcallImplCallingConv(Impl, CallingConv::AArch64_VectorCall);
     break;
   default:
@@ -288,16 +291,24 @@ RuntimeLibcallsInfo::getFunctionTy(LLVMContext &Ctx, const Triple &TT,
   case RTLIB::impl_armpl_vfmodq_f32:
   case RTLIB::impl_armpl_vfmodq_f64:
   case RTLIB::impl_armpl_svfmod_f32_x:
-  case RTLIB::impl_armpl_svfmod_f64_x: {
+  case RTLIB::impl_armpl_svfmod_f64_x:
+  case RTLIB::impl_armpl_vpowq_f32:
+  case RTLIB::impl_armpl_vpowq_f64:
+  case RTLIB::impl_armpl_svpow_f32_x:
+  case RTLIB::impl_armpl_svpow_f64_x: {
     bool IsF32 = LibcallImpl == RTLIB::impl__ZGVnN4vv_fmodf ||
                  LibcallImpl == RTLIB::impl__ZGVsMxvv_fmodf ||
                  LibcallImpl == RTLIB::impl_armpl_svfmod_f32_x ||
-                 LibcallImpl == RTLIB::impl_armpl_vfmodq_f32;
+                 LibcallImpl == RTLIB::impl_armpl_vfmodq_f32 ||
+                 LibcallImpl == RTLIB::impl_armpl_vpowq_f32 ||
+                 LibcallImpl == RTLIB::impl_armpl_svpow_f32_x;
 
     bool IsScalable = LibcallImpl == RTLIB::impl__ZGVsMxvv_fmod ||
                       LibcallImpl == RTLIB::impl__ZGVsMxvv_fmodf ||
                       LibcallImpl == RTLIB::impl_armpl_svfmod_f32_x ||
-                      LibcallImpl == RTLIB::impl_armpl_svfmod_f64_x;
+                      LibcallImpl == RTLIB::impl_armpl_svfmod_f64_x ||
+                      LibcallImpl == RTLIB::impl_armpl_svpow_f32_x ||
+                      LibcallImpl == RTLIB::impl_armpl_svpow_f64_x;
 
     AttrBuilder FuncAttrBuilder(Ctx);
 
@@ -448,6 +459,8 @@ bool RuntimeLibcallsInfo::hasVectorMaskArgument(RTLIB::LibcallImpl Impl) {
   case RTLIB::impl_armpl_svsincospi_f64_x:
   case RTLIB::impl__ZGVsMxvv_fmod:
   case RTLIB::impl__ZGVsMxvv_fmodf:
+  case RTLIB::impl_armpl_svpow_f32_x:
+  case RTLIB::impl_armpl_svpow_f64_x:
     return true;
   default:
     return false;
diff --git a/llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll b/llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -start-before=codegenprepare -mtriple=aarch64-gnu-linux -mattr=+neon,+sve \
+; RUN:   -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL
+
+define <4 x float> @test_pow_v4f32(<4 x float> %x, <4 x float> %y) nounwind {
+; ARMPL-LABEL: test_pow_v4f32:
+; ARMPL:       // %bb.0:
+; ARMPL-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; ARMPL-NEXT:    bl armpl_vpowq_f32
+; ARMPL-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; ARMPL-NEXT:    ret
+  %result = call <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> %y)
+  ret <4 x float> %result
+}
+
+define <2 x double> @test_pow_v2f64(<2 x double> %x, <2 x double> %y) nounwind {
+; ARMPL-LABEL: test_pow_v2f64:
+; ARMPL:       // %bb.0:
+; ARMPL-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; ARMPL-NEXT:    bl armpl_vpowq_f64
+; ARMPL-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; ARMPL-NEXT:    ret
+  %result = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> %y)
+  ret <2 x double> %result
+}
+
+define <vscale x 4 x float> @test_pow_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y) nounwind {
+; ARMPL-LABEL: test_pow_nxv4f32:
+; ARMPL:       // %bb.0:
+; ARMPL-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; ARMPL-NEXT:    ptrue p0.s
+; ARMPL-NEXT:    bl armpl_svpow_f32_x
+; ARMPL-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; ARMPL-NEXT:    ret
+  %result = call <vscale x 4 x float> @llvm.pow.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y)
+  ret <vscale x 4 x float> %result
+}
+
+define <vscale x 2 x double> @test_pow_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y) nounwind {
+; ARMPL-LABEL: test_pow_nxv2f64:
+; ARMPL:       // %bb.0:
+; ARMPL-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; ARMPL-NEXT:    ptrue p0.d
+; ARMPL-NEXT:    bl armpl_svpow_f64_x
+; ARMPL-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; ARMPL-NEXT:    ret
+  %result = call <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y)
+  ret <vscale x 2 x double> %result
+}
+
+define <4 x float> @test_pow_v4f32_025(<4 x float> %x) nounwind {
+; ARMPL-LABEL: test_pow_v4f32_025:
+; ARMPL:       // %bb.0:
+; ARMPL-NEXT:    fsqrt v0.4s, v0.4s
+; ARMPL-NEXT:    fsqrt v0.4s, v0.4s
+; ARMPL-NEXT:    ret
+  %result = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> splat (float 2.5e-01))
+  ret <4 x float> %result
+}
+
+define <vscale x 2 x double> @test_pow_nxv2f64_075(<vscale x 2 x double> %x) nounwind {
+; ARMPL-LABEL: test_pow_nxv2f64_075:
+; ARMPL:       // %bb.0:
+; ARMPL-NEXT:    ptrue p0.d
+; ARMPL-NEXT:    fsqrt z0.d, p0/m, z0.d
+; ARMPL-NEXT:    movprfx z1, z0
+; ARMPL-NEXT:    fsqrt z1.d, p0/m, z0.d
+; ARMPL-NEXT:    fmul z0.d, z0.d, z1.d
+; ARMPL-NEXT:    ret
+  %result = call fast <vscale x 2 x double> @llvm.pow.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> splat (double 7.5e-01))
+  ret <vscale x 2 x double> %result
+}
diff --git a/llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll b/llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
@@ -9,6 +9,10 @@
 
 ; CHECK: declare <vscale x 2 x double> @armpl_svmodf_f64_x(<vscale x 2 x double>, ptr noalias nonnull writeonly align 16, <vscale x 2 x i1>) [[ATTRS_PTR_ARG]]
 
+; CHECK: declare <vscale x 4 x float> @armpl_svpow_f32_x(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>) [[ATTRS]]
+
+; CHECK: declare <vscale x 2 x double> @armpl_svpow_f64_x(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>) [[ATTRS]]
+
 ; CHECK: declare void @armpl_svsincos_f32_x(<vscale x 4 x float>, ptr noalias nonnull writeonly align 16, ptr noalias nonnull writeonly align 16, <vscale x 4 x i1>) [[ATTRS_PTR_ARG]]
 
 ; CHECK: declare void @armpl_svsincos_f64_x(<vscale x 2 x double>, ptr noalias nonnull writeonly align 16, ptr noalias nonnull writeonly align 16, <vscale x 2 x i1>) [[ATTRS_PTR_ARG]]
@@ -25,6 +29,10 @@
 
 ; CHECK: declare <2 x double> @armpl_vmodfq_f64(<2 x double>, ptr noalias nonnull writeonly align 16) [[ATTRS_PTR_ARG]]
 
+; CHECK: declare aarch64_vector_pcs <4 x float> @armpl_vpowq_f32(<4 x float>, <4 x float>) [[ATTRS]]
+
+; CHECK: declare aarch64_vector_pcs <2 x double> @armpl_vpowq_f64(<2 x double>, <2 x double>) [[ATTRS]]
+
 ; CHECK: declare void @armpl_vsincospiq_f32(<4 x float>, ptr noalias nonnull writeonly align 16, ptr noalias nonnull writeonly align 16) [[ATTRS_PTR_ARG]]
 
 ; CHECK: declare void @armpl_vsincospiq_f64(<2 x double>, ptr noalias nonnull writeonly align 16, ptr noalias nonnull writeonly align 16) [[ATTRS_PTR_ARG]]
