kicad9: snap placement, power bus wires, T-junction stagger, power symbol orientation#297
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…mbol orientation Adds connectivity-aware part placement for KiCad 9 schematic generation: - Snap 2-pin parts (R, C, LED) onto their connected IC pins with correct rotation, chaining multiple parts (IC ← R ← LED) with occupied-pin tracking - Generate power bus wires between co-linear power pins with max-gap filtering - Snap decoupling caps to IC power pins, offset from IC body - Stagger T-junction wire patterns for fanout nets with shared junction points - Orient power symbols (VCC up, GND down) based on pin direction - Suppress redundant net labels on snapped pin clusters - Compute label angle from transformed pin direction to avoid overlap - Add NCNet no_connect flag support Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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What this does
When SKiDL's fallback placement kicks in (routing fails, schematic still needs to be readable), 2-pin passive parts used to float randomly around the page with net labels as the only clue they belonged to a particular IC. This PR makes the fallback output look like a human drew it.
Snap placement
Resistors, caps, LEDs, and switches now snap directly onto the IC pin they connect to, extending outward in the pin's direction. Three passes handle increasingly complex cases:
Decoupling caps get special treatment: they snap to power pins but offset away from the IC body so they don't obscure signal pins.
T-junction stagger
When an IC has a repeating pattern (3+ pins each driving the same number of parts, like 16 mux channels each with a pot), the parts are arranged in a stepped stagger extending outward from the IC. Each pin's group sits further from the body than the last, with junction wires connecting back. The step size adapts to the physical size of the parts being staggered (a row of switches needs more room than a row of resistors).
IC group redistribution
Before stagger fans are placed, ICs that will have large fans are shifted apart vertically so the fans don't overlap each other. Parts already snapped to the IC (from pass 1) move with it, so connectivity is preserved. The stagger fans are then placed at the final IC positions.
Power symbol orientation
GND bars and supply arrows now rotate to point away from their component pin. The previous code always placed them at angle 0, which meant ground symbols often sat on top of their IC instead of hanging below it. The fix accounts for the Y-axis flip between SKiDL's internal coordinate system (Y-up) and KiCad's schematic coordinates (Y-down).
Power bus wires
When multiple pins on the same power net are co-linear (e.g. a row of VCC pins along one side of an IC), a single bus wire connects them instead of each getting an independent power symbol.
Label cleanup
Redundant net labels on snapped pin clusters are suppressed (the physical wire connection makes them unnecessary). Label angles are computed from the transformed pin direction so they don't overlap their parent symbol.
Tested on
A 150+ part Daisy Seed carrier board design: CD74HC4067E mux with 16 pots, 4x SN74HC165N shift registers with 28 switches, 6x DM13A LED drivers with 85 LEDs, H11L1 optocoupler MIDI I/O, SSD1306 OLED, LD33V regulator. All through-hole DIP.