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Sathish Kumar Kamishettigarizeddii
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Revert "lopper:assists:baremetallinker_xlnx: Fix default DDR selection for Microblaze RISC-V to prefer BRAM"
This reverts commit 59b00b5. Signed-off-by: Sathish Kumar Kamishettigari <sathishkumar.kamishettigari@amd.com>
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lopper/assists/baremetallinker_xlnx.py

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Original file line numberDiff line numberDiff line change
@@ -491,13 +491,6 @@ def get_ddr_address(sdt,tgt_node,mem_ranges,match_cpunode,cpu_ip_name,memtest_co
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if has_ddr and not memtest_config and not "microblaze" in cpu_ip_name:
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default_ddr = min(has_ddr, key=lambda k: has_ddr[k])
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# For Microblaze RISC-V, use the BRAM memory if available
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if cpu_ip_name == "microblaze_riscv" and valid_mem_ips and not memtest_config:
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has_bram = [key for key in sorted(mem_ranges.items(), key=lambda e: e[1][1], reverse=traverse) if "_bram" in key and
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any(key.rsplit('_', 1)[0] in mem_ip for mem_ip in valid_mem_ips)]
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if has_bram:
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default_ddr = has_bram[0]
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mb_reset_addr = None
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if "microblaze" in cpu_ip_name:
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if match_cpunode.propval('xlnx,base-vectors') != ['']:

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