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lopper:assists:baremetallinker_xlnx: Fix default DDR selection for Mi…#758

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zeddii merged 1 commit into
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sathishkumar-amd:lmb_mbv
May 7, 2026
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lopper:assists:baremetallinker_xlnx: Fix default DDR selection for Mi…#758
zeddii merged 1 commit into
devicetree-org:masterfrom
sathishkumar-amd:lmb_mbv

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…croblaze RISC-V to prefer BRAM

Fix the default memory selection for Microblaze RISC-V processors to prefer the largest available BRAM over DDR when BRAM is present in the CPU's valid memory IP list.

…croblaze RISC-V to prefer BRAM

Fix the default memory selection for Microblaze RISC-V processors to prefer the largest
available BRAM over DDR when BRAM is present in the CPU's valid memory IP list.

Signed-off-by: Sathish Kumar Kamishettigari <sathishkumar.kamishettigari@amd.com>
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Hi @kedareswararao,

Please review this

@zeddii zeddii merged commit 59b00b5 into devicetree-org:master May 7, 2026
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3 participants