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zynqmp: wolfBoot ZynqMP FSBL with signed FIT Linux boot and EL3 security (eFuse/PUF/AES-CSU)
1 parent 4308b36 commit 0fec91f

28 files changed

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‎.github/workflows/test-build-aarch64.yml‎

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make-args:
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required: false
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type: string
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psu-init-stub:
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# Generate a build-only stub for the board psu_init_gpl.c (ZynqMP FSBL).
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required: false
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type: boolean
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default: false
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jobs:
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run: |
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make -C tools/keytools && make -C tools/bin-assemble
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- name: Generate ZynqMP psu_init build-only stub
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if: ${{ inputs.psu-init-stub }}
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run: |
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cat > hal/board/zynqmp/psu_init_gpl.c <<'STUB'
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/* CI build-only stub for the board psu_init_gpl.c (XSA-generated, not
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* tracked in-tree). Satisfies the hal/zynqmp_psu_shim.c externs so the
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* FSBL links; performs NO real PS init -- never run on hardware. */
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unsigned long psu_mio_init_data(void) { return 1UL; }
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unsigned long psu_peripherals_pre_init_data(void) { return 1UL; }
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unsigned long psu_pll_init_data(void) { return 1UL; }
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unsigned long psu_clock_init_data(void) { return 1UL; }
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unsigned long psu_ddr_init_data(void) { return 1UL; }
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unsigned long psu_ddr_phybringup_data(void) { return 1UL; }
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unsigned long psu_peripherals_init_data(void) { return 1UL; }
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unsigned long psu_resetin_init_data(void) { return 1UL; }
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unsigned long psu_serdes_init_data(void) { return 1UL; }
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unsigned long psu_resetout_init_data(void) { return 1UL; }
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int serdes_fixcal_code(void) { return 0; }
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unsigned long psu_peripherals_powerdwn_data(void) { return 1UL; }
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unsigned long psu_afi_config(void) { return 1UL; }
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unsigned long psu_ddr_qos_init_data(void) { return 1UL; }
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STUB
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- name: Build wolfboot
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run: |
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make ${{inputs.make-args}}

‎.github/workflows/test-configs.yml‎

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arch: aarch64
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config-file: ./config/examples/zynqmp_sdcard.config
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zynqmp_fsbl_test:
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uses: ./.github/workflows/test-build-aarch64.yml
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with:
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arch: aarch64
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config-file: ./config/examples/zynqmp_fsbl.config
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make-args: ZYNQMP_FSBL=1 ZYNQMP_PSU_INIT_DIR=hal/board/zynqmp
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psu-init-stub: true
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zynqmp_fsbl_sec_test:
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uses: ./.github/workflows/test-build-aarch64.yml
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with:
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arch: aarch64
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config-file: ./config/examples/zynqmp_fsbl.config
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make-args: ZYNQMP_FSBL=1 ZYNQMP_PSU_INIT_DIR=hal/board/zynqmp ZYNQMP_SEC=1 ZYNQMP_PUF_SELFTEST=1 ZYNQMP_AES_SELFTEST=1
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psu-init-stub: true
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zynqmp_fsbl_sd_test:
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uses: ./.github/workflows/test-build-aarch64.yml
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with:
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arch: aarch64
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config-file: ./config/examples/zynqmp_fsbl_sd.config
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make-args: ZYNQMP_FSBL=1 ZYNQMP_PSU_INIT_DIR=hal/board/zynqmp DISK_SDCARD=1
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psu-init-stub: true
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zynq7000_test:
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uses: ./.github/workflows/test-build.yml
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with:

‎arch.mk‎

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CFLAGS+=-DWOLFBOOT_ZYNQMP_CSU
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endif
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ifeq ($(ZYNQMP_FSBL),1)
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# wolfBoot fully replaces the Xilinx FSBL: the BootROM authenticates and
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# loads wolfBoot into OCM at EL3, and wolfBoot runs psu_init() to bring up
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# the PLLs/DDR/MIO/clocks before loading the downstream images. wolfBoot
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# therefore links and runs entirely from OCM (DDR is not up at entry).
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#
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# The board-specific psu_init_gpl.c / psu_init_gpl.h (generated from the
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# XSA, Xilinx copyright) are supplied at build time from
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# ZYNQMP_PSU_INIT_DIR and are NOT part of the wolfBoot tree. The
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# hal/zynqmp/ shim headers (xil_io.h, sleep.h) let that unmodified file
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# compile. Set EL3_SECURE=1 in the target .config.
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ZYNQMP_PSU_INIT_DIR?=hal/board/zynqmp
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CFLAGS+=-DWOLFBOOT_ZYNQMP_FSBL
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CFLAGS+=-Ihal/zynqmp -I$(ZYNQMP_PSU_INIT_DIR)
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LSCRIPT_IN=hal/zynqmp_ocm.ld
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OBJS+=hal/zynqmp_psu_shim.o
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OBJS+=hal/zynqmp_atf.o
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OBJS+=$(ZYNQMP_PSU_INIT_DIR)/psu_init_gpl.o
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# Load the PMU configuration object (EEMI permission table) into PMU
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# firmware so the APU can control the SoC nodes. Like psu_init_gpl.c the
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# pm_cfg_obj.c is design-specific and supplied from ZYNQMP_PSU_INIT_DIR.
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ifeq ($(ZYNQMP_PM_CFG),1)
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CFLAGS+=-DWOLFBOOT_ZYNQMP_PM_CFG
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OBJS+=$(ZYNQMP_PSU_INIT_DIR)/pm_cfg_obj.o
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endif
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# Run the PS-GTR serdes init (USB3/SATA/PCIe/DP PHY lanes). Required if the
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# kernel drives a PS-GTR peripheral (e.g. USB3 dwc3, whose probe hangs on
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# an unclocked PHY). Skipped by default since QSPI/SD/RGMII boot needs no
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# serdes; the shim runs the full calibrated sequence when enabled.
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ifeq ($(ZYNQMP_PSU_INIT_SERDES),1)
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CFLAGS+=-DZYNQMP_PSU_INIT_SERDES
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endif
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# FSBL security features (eFuse read, PUF, AES-CSU). At EL3 these access
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# the CSU/eFuse controllers directly (pmu_mmio is direct MMIO in FSBL
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# mode). Read-only eFuse dump today; PUF/AES land incrementally.
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ifeq ($(ZYNQMP_SEC),1)
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CFLAGS+=-DWOLFBOOT_ZYNQMP_FSBL_SEC
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endif
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# PUF register+regenerate self-test at boot (bring-up only; registers the
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# PUF every boot). Opt-in, needs ZYNQMP_SEC=1.
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ifeq ($(ZYNQMP_PUF_SELFTEST),1)
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CFLAGS+=-DWOLFBOOT_ZYNQMP_PUF_SELFTEST
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endif
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# AES-CSU known-answer self-test at boot (KUP key; eFuse-safe). Opt-in.
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ifeq ($(ZYNQMP_AES_SELFTEST),1)
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CFLAGS+=-DWOLFBOOT_ZYNQMP_AES_SELFTEST
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endif
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endif
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endif
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ifeq ($(TARGET),versal)

‎config/examples/zynqmp_fsbl.config‎

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# wolfBoot configuration for AMD ZynqMP ZCU102 - FSBL REPLACEMENT (QSPI boot)
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# Zynq UltraScale+ MPSoC ZU9EG - Quad-core ARM Cortex-A53
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#
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# wolfBoot replaces the Xilinx First Stage Boot Loader (FSBL). The BootROM
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# (optionally with eFuse PPK RSA secure boot) authenticates and loads wolfBoot
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# directly into OCM at 0xFFFC0000 and enters it at EL3. wolfBoot then:
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# 1. runs the board psu_init() (PLLs, DDR, MIO mux, clocks)
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# 2. loads + verifies the downstream images with its OWN signing keys
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# 3. (Milestone 1) hands off to real ARM Trusted Firmware (BL31) which keeps
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# EL3/PSCI and drops to Linux.
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# PMUFW is still loaded by the BootROM via the [pmufw_image] BIF tag.
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#
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# Boot flow: BootROM -> wolfBoot (OCM/EL3) -> psu_init -> verify+load
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# BL31 + kernel + DTB -> BL31 -> Linux
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#
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# The board-specific psu_init_gpl.c / psu_init_gpl.h (generated from the XSA,
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# Xilinx copyright) must be supplied at build time. By default they are read
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# from hal/board/zynqmp/ (override with ZYNQMP_PSU_INIT_DIR=...). They are not
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# part of the wolfBoot tree. Build with:
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# make ZYNQMP_FSBL=1 ZYNQMP_PSU_INIT_DIR=/path/to/board
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# Package with tools/scripts/zcu102/zynqmp_wolfboot_fsbl.bif
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ARCH?=AARCH64
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TARGET?=zynq
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# Enable the FSBL-replacement build: link/run from OCM, run psu_init at boot,
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# pull in the board psu_init_gpl.o + the hal/zynqmp shim.
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ZYNQMP_FSBL?=1
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ZYNQMP_PSU_INIT_DIR?=hal/board/zynqmp
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# Load the PMU configuration object (EEMI permission table) into PMU firmware
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# so the APU can control SoC nodes; needs hal/board/zynqmp/pm_cfg_obj.c.
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ZYNQMP_PM_CFG?=1
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# Run the PS-GTR serdes init so USB3/SATA/PCIe/DP PHY lanes are clocked.
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# Needed for the kernel's USB (dwc3) probe not to hang. Set 0 to skip (QSPI/SD
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# boot does not need serdes).
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ZYNQMP_PSU_INIT_SERDES?=1
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# FSBL security features (eFuse read/PUF/AES-CSU) via direct EL3 CSU/eFuse
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# access. Read-only eFuse dump today. Set 0 to exclude.
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ZYNQMP_SEC?=1
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# BootROM enters the [bootloader] partition at EL3. Run wolfBoot at EL3.
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CFLAGS_EXTRA+=-DEL3_SECURE=1
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# DDR-training delay correction. The BootROM leaves the IOU_SCNTRS system
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# counter running at the ~1.6GHz pre-divider rate during psu_init (the /15
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# TIMESTAMP_REF_CTRL divisor does not re-latch the already-running counter),
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# while usleep() computes its tick budget at the nominal 100MHz timestamp
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# clock. Without correction every psu_ddr_phybringup settle delay is ~16x too
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# short and DDR PHY training comes up marginal. Hardware-measured: a 16x scale
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# restores correct training. See hal/zynqmp_psu_shim.c.
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CFLAGS_EXTRA+=-DZYNQMP_USLEEP_SCALE=16
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WOLFBOOT_VERSION?=0
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# RSA 4096-bit with SHA3-384 (downstream image signing)
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SIGN?=RSA4096
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HASH?=SHA3
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IMAGE_HEADER_SIZE?=1024
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# Software ARMv8+Crypto assembly for SHA3 (no CSU/PMU SMC available at EL3
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# until BL31 is resident).
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NO_ARM_ASM?=0
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HW_SHA3?=0
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DEBUG?=0
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DEBUG_SYMBOLS=1
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DEBUG_UART=1
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# CFLAGS_EXTRA+=-DDEBUG_ZYNQ=1 # per-chunk QSPI/DDR debug spew; enable only for bring-up
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=0
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DUALBANK_SWAP?=0
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PKA?=0
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WOLFTPM?=0
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# Downstream images are read from QSPI (not XIP; wolfBoot executes from OCM).
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EXT_FLASH?=1
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SPI_FLASH?=0
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NO_XIP=1
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USE_GCC=1
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ELF?=1
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# Native gzip decompression for FIT subimages
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GZIP?=1
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# Flash Sector Size
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WOLFBOOT_SECTOR_SIZE=0x20000
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# Application Partition Size
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WOLFBOOT_PARTITION_SIZE=0x2A00000
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# wolfBoot self-location (OCM). Must match ORIGIN in hal/zynqmp_ocm.ld.
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WOLFBOOT_ORIGIN=0xFFFC0000
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# Location in QSPI for Primary Boot Partition (OS payload: FIT kernel+DTB)
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x800000
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# Load Partition to RAM Address (DDR, after psu_init)
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WOLFBOOT_LOAD_ADDRESS?=0x10000000
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# Location in QSPI for Secondary (update) Partition
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x3A00000
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# Location to store wolfBoot state
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x63E0000
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# DTS (Device Tree)
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x11800000
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WOLFBOOT_DTS_BOOT_ADDRESS?=0x7B0000
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WOLFBOOT_DTS_UPDATE_ADDRESS?=0x39B0000
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CROSS_COMPILE=aarch64-none-elf-
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# Speed up reads from flash by using larger blocks
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CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096

‎config/examples/zynqmp_fsbl_sd.config‎

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# wolfBoot configuration for AMD ZynqMP ZCU102 - FSBL REPLACEMENT (SD boot)
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# Zynq UltraScale+ MPSoC ZU9EG - Quad-core ARM Cortex-A53
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#
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# Same FSBL-replacement role as config/examples/zynqmp_fsbl.config, but the
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# BootROM loads wolfBoot from BOOT.BIN on the SD card FAT partition, and
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# wolfBoot reads the downstream images from MBR partitions on the same card.
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#
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# Boot flow: BootROM -> wolfBoot (OCM/EL3) -> psu_init -> verify+load
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# BL31 + kernel + DTB (from SD) -> BL31 -> Linux
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#
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# Supply the board psu_init_gpl.c/.h at build time (see zynqmp_fsbl.config).
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# Build: make ZYNQMP_FSBL=1 ZYNQMP_PSU_INIT_DIR=/path/to/board
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# Package: tools/scripts/zcu102/zynqmp_wolfboot_fsbl.bif
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ARCH?=AARCH64
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TARGET?=zynq
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ZYNQMP_FSBL?=1
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ZYNQMP_PSU_INIT_DIR?=hal/board/zynqmp
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# BootROM enters the [bootloader] partition at EL3.
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CFLAGS_EXTRA+=-DEL3_SECURE=1
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WOLFBOOT_VERSION?=0
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SIGN?=RSA4096
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HASH?=SHA3
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IMAGE_HEADER_SIZE?=1024
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NO_ARM_ASM?=0
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HW_SHA3?=0
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DEBUG?=0
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DEBUG_SYMBOLS=1
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DEBUG_UART=1
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CFLAGS_EXTRA+=-DDEBUG_ZYNQ=1
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# SD card support - use SDHCI driver (SD1 external slot on ZCU102)
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DISK_SDCARD?=1
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DISK_EMMC?=0
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CFLAGS_EXTRA+=-DSDHCI_FORCE_CARD_DETECT
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# No QSPI in the SD configuration
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EXT_FLASH?=0
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NO_XIP=1
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ELF?=1
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GZIP?=1
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VTOR?=1
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CORTEX_M0?=0
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NO_ASM?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=0
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DUALBANK_SWAP?=0
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PKA?=0
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WOLFTPM?=0
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USE_GCC=1
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CROSS_COMPILE=aarch64-none-elf-
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# MBR partition layout (same as zynqmp_sdcard.config):
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# part[0]=boot (FAT32, BOOT.BIN), part[1]=OFP_A, part[2]=OFP_B, part[3]=rootfs
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WOLFBOOT_NO_PARTITIONS=1
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CFLAGS_EXTRA+=-DBOOT_PART_A=1
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CFLAGS_EXTRA+=-DBOOT_PART_B=2
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CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000
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CFLAGS_EXTRA+=-DLINUX_BOOTARGS_ROOT=\"/dev/mmcblk0p4\"
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# wolfBoot self-location (OCM). Must match ORIGIN in hal/zynqmp_ocm.ld.
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WOLFBOOT_ORIGIN=0xFFFC0000
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# Bound the RAM load of the (not-yet-authenticated) disk image. Required with
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# WOLFBOOT_NO_PARTITIONS=1 (update_disk.c). 64MB comfortably fits the signed
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# FIT (kernel+atf+fdt) at WOLFBOOT_LOAD_ADDRESS. NOTE: the SD FSBL boot path is
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# not yet HW-validated (QSPI is); this config is build-tested only.
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WOLFBOOT_RAMBOOT_MAX_SIZE=0x4000000
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# Load Partition to RAM Address (DDR, after psu_init)
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WOLFBOOT_LOAD_ADDRESS?=0x10000000
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# DTS (Device Tree) load address
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WOLFBOOT_LOAD_DTS_ADDRESS?=0x1000
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# Required for test-app (even with WOLFBOOT_NO_PARTITIONS=1)
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WOLFBOOT_PARTITION_BOOT_ADDRESS=0x80200000
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WOLFBOOT_PARTITION_SIZE=0x4000000
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WOLFBOOT_SECTOR_SIZE=0x1000

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