Commit c71f0e9
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Temporal Logic: fix s_until_with lowering for BDD
Lower sva_s_until_with to strong release in SVA_to_LTL and teach
LTL_to_CTL to handle strong_R so the BDD engine can check these
properties. Promote the regression added in #1998 from KNOWNBUG to
CORE.1 parent 7b05b8d commit c71f0e9
4 files changed
Lines changed: 18 additions & 4 deletions
File tree
- regression/ebmc/SVA-LTL
- src/temporal-logic
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