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Temporal Logic: fix s_until_with lowering for BDD
Lower sva_s_until_with to strong release in SVA_to_LTL and teach LTL_to_CTL to handle strong_R so the BDD engine can check these properties. Promote the regression added in #1998 from KNOWNBUG to CORE.
1 parent 7b05b8d commit c71f0e9

4 files changed

Lines changed: 18 additions & 4 deletions

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CHANGELOG

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@@ -1,5 +1,6 @@
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# EBMC 6.1
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* Fix for lowering of s_until_with to LTL
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* Verilog: $root.
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* Verilog: procedural assignments to hierarchical identifiers
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* SystemVerilog: ports for sequence and property declarations

regression/ebmc/SVA-LTL/s_until_with1.desc

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@@ -1,4 +1,4 @@
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KNOWNBUG
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CORE
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s_until_with1.sv
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--bdd
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^\[main\.p0\] always \(0 s_until_with 1\): REFUTED$

src/temporal-logic/sva_to_ltl.cpp

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@@ -228,11 +228,11 @@ exprt SVA_to_LTL(exprt expr)
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}
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else if(expr.id() == ID_sva_s_until_with)
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{
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// This is release with swapped operands
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// This is strong release with swapped operands.
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auto &until_with = to_sva_s_until_with_expr(expr);
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auto rec_lhs = SVA_to_LTL(until_with.lhs());
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auto rec_rhs = SVA_to_LTL(until_with.rhs());
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return R_exprt{rec_rhs, rec_lhs}; // swapped
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return strong_R_exprt{rec_rhs, rec_lhs}; // swapped
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}
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else if(!has_temporal_operator(expr))
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{

src/temporal-logic/temporal_logic.cpp

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@@ -70,7 +70,8 @@ bool is_CTL(const exprt &expr)
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bool is_LTL_operator(const exprt &expr)
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{
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auto id = expr.id();
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return id == ID_G || id == ID_F || id == ID_X || id == ID_U || id == ID_R;
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return id == ID_G || id == ID_F || id == ID_X || id == ID_U || id == ID_R ||
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id == ID_strong_R;
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}
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bool is_LTL_past_operator(const exprt &expr)
@@ -217,6 +218,18 @@ std::optional<exprt> LTL_to_CTL(exprt expr)
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else
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return {};
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}
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else if(expr.id() == ID_strong_R)
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{
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auto &strong_R = to_strong_R_expr(expr);
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auto rec_lhs = LTL_to_CTL(strong_R.lhs());
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auto rec_rhs = LTL_to_CTL(strong_R.rhs());
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if(rec_lhs.has_value() && rec_rhs.has_value())
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{
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return and_exprt{AF_exprt{*rec_lhs}, AR_exprt{*rec_lhs, *rec_rhs}};
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}
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else
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return {};
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}
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else
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return {};
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}

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