Merge pull request #1518 from diffblue/port_expression1

KNOWNBUG test for SystemVerilog port expressions

Author: tautschnig

regression/verilog/modules/port_expression1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+port_expression1.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+This does not parse.

regression/verilog/modules/port_expression1.sv

@@ -0,0 +1,17 @@
+// Port expressions. The type of the port is derived
+// from the type of the expression.
+// Not supported by Icarus 12, VCS 2023.03, Xcelium 23.09.
+// Works with Questa 2024.3, Riviera Pro 2023.04.
+module M(input .some_input(data[7:0]));
+
+  reg [31:0] data;
+
+  initial #1 assert (data[7:0] == 123);
+
+endmodule
+
+module main;
+
+  M my_instance(.some_input(123));
+
+endmodule