netlist conversion: track equivalent nodes#1604
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tautschnig
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Jan 26, 2026
| ================================================*/ | ||
| void ic3_enginet::add_verilog_conv_constrs() | ||
| { | ||
| PRECONDITION(netlist.equivalences.empty()); |
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Why is this an important invariant to maintain for this function?
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But then, at present, #1605 does not change any existing code, it just adds new code (and, hence, isn't actually being used).
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Now using a different approach -- the equivalences are now recorded in addition to the constraints
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This augments the list of constraints on netlist nodes (netlist nodes that have to evaluate to true) by a list of node equivalences. This avoids the need for expensive re-discovery of such equivalences by methods such as SAT sweeping.
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This replaces the list of constraints on netlist nodes (netlist nodes that have to evaluate to true) by a list of node equivalences. This is more compact when node equivalences have to be generated, as the AIG nodes for lhs<->rhs do not have to be generated.