Verilog: introduce $unit scope to parser

[kroening]

This adds the $unit scope to the parser scope stack.

The parser to explicitly put modules and packages into the top (definitions) scope, not the current scope, which is now the $unit scope.

[tautschnig]

Why does this not affect any test? Are all our tests too simple?

[kroening]

The problem here is that the name resolution done by most (but not all) tools is contextual. E.g., most tools accept

int some_identifier;

module some_identifier;
  initial assert(some_identifier == 0);
endmodule

[kroening]

I.e., the right thing to do is likely to switch to a recursive descent parser, and then do lookups in different name spaces depending on syntax.

[tautschnig]

Does the Verilog standard not specify what the lookup rules are? Or perhaps it does and tools just ignore what the standard says?

[kroening]

The clarity of the standard leaves room for improvement. See comments on test in #1818. ChatGPT says it's not valid. Claude says it's valid.