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## References
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Javier de San Pedro, Thomas Bourgeat, Jordi Cortadella
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[Specification mining for asynchronous controllers](http://www.cs.upc.edu/~jspedro/articles/async2016.pdf)
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[Specification mining for asynchronous controllers](https://doi.org/10.1109/ASYNC.2016.10)
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Asynchronous Circuits and Systems (ASYNC), 2016 22nd IEEE International Symposium on 107-114
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DOI: 10.1109/ASYNC.2016.10
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Infers formal specifications (state graphs / STGs) from observed I/O traces of asynchronous controllers, so an implementation can be reverse-engineered into a model and re-synthesized or verified. Applies data-mining to signal-transition behavior to reconstruct the underlying concurrency.
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Cortadella, Jordi, et al.
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["RTL Synthesis: From Logic Synthesis to Automatic Pipelining."](http://upcommons.upc.edu/bitstream/handle/2117/82027/RTLsynthesis.pdf)
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Proceedings of the IEEE 103.11 (2015): 2061-2075.
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DOI: 10.1109/JPROC.2015.2456189
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Survey tracing the evolution from classical logic synthesis toward automatic pipelining and microarchitectural transformation, with elasticity/latency-insensitivity as the substrate that makes pipelining a correctness-preserving transform rather than a manual redesign.
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1317
Chatterjee, Satrajit, Michael Kishinevsky, and Umit Y. Ogras.
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["xMAS: Quick formal modeling of communication fabrics to enable verification."](https://www.researchgate.net/profile/Satrajit_Chatterjee/publication/224150874_xMAS_Quick_Formal_Modeling_of_Communication_Fabrics_to_Enable_Verification/links/560f30b508aec422d112f3ea.pdf)
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["xMAS: Quick formal modeling of communication fabrics to enable verification."](https://doi.org/10.1109/MDT.2012.2205998)
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Design & Test of Computers, IEEE 29.3 (2012): 80-88.
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DOI: 10.1109/MDT.2012.2205998
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Introduces eXecutable Micro-Architectural Specification: a small primitive set (queues, functions, forks, joins, switches, merges) for building formal, executable models of on-chip communication fabrics, enabling early liveness/deadlock verification and property derivation before RTL exists.
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Cortadella, Jordi, et al.
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[Logic synthesis for asynchronous controllers and interfaces](http://www.springer.com/productFlyer_978-3-540-43152-7.pdf?SGWID=0-0-1297-2158934-0).
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Vol. 8. Springer Science & Business Media, 2012.
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Textbook on synthesizing asynchronous control from Signal Transition Graphs: state encoding, logic decomposition, and hazard-free implementation. Theoretical foundation behind the Petrify toolflow.
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2130
Cortadella, Jordi, Marc Galceran-Oms, and Mike Kishinevsky.
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["Elastic systems."](http://www.cs.upc.edu/~jordicf/gavina/BIB/files/memocode2010.pdf)
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Formal Methods and Models for Codesign (MEMOCODE), 2010 8th IEEE/ACM International Conference on. IEEE, 2010.
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Generalizes synchronous elastic circuits into a theory of elastic systems where the timing of data is decoupled from functional correctness via valid/stall handshaking. Establishes the algebra and behavior-preserving transformations (retiming, recycling, bubble insertion).
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Galceran-Oms, Marc, et al.
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["Automatic microarchitectural pipelining."](http://www.date-conference.org/proceedings/PAPERS/2010/DATE10/PDFFILES/IP3_08.PDF)
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["Automatic microarchitectural pipelining."](https://doi.org/10.1109/DATE.2010.5456910)
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Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 2010.
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DOI: 10.1109/DATE.2010.5456910
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Uses elasticity to automatically insert pipeline stages into a design without changing its function, exploiting latency-insensitivity to add/remove buffering (recycling) and rebalance combinational paths.
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Carmona, Josep, et al.
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["Elastic circuits."](http://www.eecs.ucf.edu/~mingjie/ECM6308/papers/Elastic%20circuits.pdf)
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["Elastic circuits."](https://doi.org/10.1109/TCAD.2009.2030436)
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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 28.10 (2009): 1437-1455.
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DOI: 10.1109/TCAD.2009.2030436
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Canonical journal paper defining synchronous elastic circuits (latency-insensitive at clock granularity): the SELF valid/stop handshake, elastic buffers, join/fork controllers, and equivalence to ordinary synchronous circuits. Core reference for the whole topic.
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Casu, Mario R., and Luca Macchiarulo.
3451
["Adaptive latency-insensitive protocols."](http://porto.polito.it/1642487/1/dtc07_paper.pdf)
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IEEE Design & Test of Computers 5 (2007): 442-452.
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Improves classic latency-insensitive design by adapting to the actual channel latencies at runtime, reducing the throughput penalty of conservatively inserted relay stations.
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Cortadella, Jordi, and Mike Kishinevsky.
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["Synchronous elastic circuits with early evaluation and token counterflow."](https://www.cs.upc.edu/~jordicf/gavina/BIB/files/dac07_early.pdf)
3958
Proceedings of the 44th annual Design Automation Conference. ACM, 2007.
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Adds early evaluation (produce a result before all inputs arrive, e.g. a mux with a known select) and backward-flowing anti-tokens to cancel unneeded computation, breaking the throughput limits of purely eager elastic protocols.
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Cortadella, Jordi, Mike Kishinevsky, and Bill Grundmann.
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["Synthesis of synchronous elastic architectures."](https://www.cs.upc.edu/~jordicf/gavina/BIB/files/dac06_self.pdf)
4364
Proceedings of the 43rd annual Design Automation Conference. ACM, 2006.
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Seminal paper introducing SELF: automatically converting an ordinary synchronous circuit into an elastic one with elastic buffers and controllers, enabling variable-latency units and modular composition.
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Ampalam, Manoj, and Montek Singh.
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["Counterflow pipelining: Architectural support for preemption in asynchronous systems using anti-tokens."](http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.259.293&rep=rep1&type=pdf)
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["Counterflow pipelining: Architectural support for preemption in asynchronous systems using anti-tokens."](https://doi.org/10.1109/ICCAD.2006.320024)
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Computer-Aided Design, 2006. ICCAD'06. IEEE/ACM International Conference on. IEEE, 2006.
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DOI: 10.1109/ICCAD.2006.320024
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Asynchronous-domain use of anti-tokens flowing backward through a pipeline to preempt and cancel in-flight computation; a direct precursor to the anti-token mechanism later adopted in elastic circuits.
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Brej, C. F., and J. D. Garside.
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["Early output logic using anti-tokens."](http://brej.org/papers/iwls_paper.pdf)
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International Workshop on Logic Synthesis. 2003.
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Introduces anti-tokens in asynchronous early-output logic: negative tokens that annihilate real tokens to discard unneeded results. Origin of the anti-token concept reused throughout later elastic work.
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Spars, Jens, and Steve Furber.
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[Principles Asynchronous Circuit Design](http://twanclik.free.fr/electricity/electronic/pdfdone12/Principles%20of%20Asynchronous%20Circuit%20Design%20-%20A%20Systems%20Perspective.pdf).
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Kluwer Academic Publishers, 2002.
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Standard textbook covering handshake protocols, delay models, pipeline styles (bundled-data, dual-rail) and controllers. Background reading for handshake-based elasticity.
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Carloni, Luca P., Kenneth L. McMillan, and Alberto L. Sangiovanni-Vincentelli.
5888
["Theory of latency-insensitive design."](http://webcluster.cs.columbia.edu/~luca/research/lipTransactions.pdf)
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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 20.9 (2001): 1059-1076.
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Founding theory of latency-insensitive design: patient processes and relay stations make a system tolerant to arbitrary channel latencies while guaranteeing functional equivalence regardless of wire delay. Root of the entire elastic line.
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Varshavsky, Victor, Vyacheslav Marakhovsky, and Tam-Anh Chu.
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"Logical timing (global synchronization of asynchronous arrays)."
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Parallel Algorithms/Architecture Synthesis, 1995. Proceedings., First Aizu International Symposium on. IEEE, 1995.
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DOI: 10.1109/AISPAS.1995.401346
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Early work on globally synchronizing arrays of asynchronous elements through logical (data-driven) timing instead of a global clock.
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Sutherland, Ivan E.
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["Micropipelines."](http://f-cpu.seul.org/new/micropipelines.pdf)
68102
Communications of the ACM 32.6 (1989): 720-738.
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Turing-award lecture introducing micropipelines: elastic FIFO pipelines built from transition-signaling (event) control and capture-pass latches. Direct ancestor of handshake and elastic pipelining.
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### Dynamically-Scheduled HLS / Dataflow
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Josipovic, Lana, Radhika Ghosal, and Paolo Ienne.
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["Dynamically Scheduled High-level Synthesis."](https://doi.org/10.1145/3174243.3174264)
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Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). ACM, 2018.
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DOI: 10.1145/3174243.3174264
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First to generate elastic/dataflow circuits directly from C: instead of statically scheduled HLS, emits handshaked dataflow units that schedule at runtime, extracting parallelism from irregular control and memory. Origin of the Dynamatic toolflow.
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Josipovic, Lana, Andrea Guerrieri, and Paolo Ienne.
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["From C/C++ Code to High-Performance Dataflow Circuits."](https://doi.org/10.1109/TCAD.2021.3105574)
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 41.7 (2022): 2142-2155.
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DOI: 10.1109/TCAD.2021.3105574
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Comprehensive journal treatment of the Dynamatic flow: full compiler from LLVM IR to elastic dataflow netlists with memory interfaces, plus the buffering and sharing optimizations. Definitive reference for modern elastic HLS.
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Josipovic, Lana.
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["High-Level Synthesis of Dynamically Scheduled Circuits."](https://doi.org/10.5075/epfl-thesis-7211)
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PhD thesis, EPFL, 2021.
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DOI: 10.5075/epfl-thesis-7211
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Dissertation gathering the dataflow-circuit HLS methodology, buffering theory, and optimizations in one place.
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Josipovic, Lana, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, and Jordi Cortadella.
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["Buffer Placement and Sizing for High-Performance Dataflow Circuits."](https://doi.org/10.1145/3373087.3375314)
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Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). ACM, 2020.
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Extended version: ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15.1 (2022): 1-32. DOI: 10.1145/3477053
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MILP formulation that places and sizes elastic buffers to meet a throughput target while breaking combinational cycles for timing closure. Directly extends elastic retiming/recycling theory to generated dataflow circuits.
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Josipovic, Lana, Andrea Guerrieri, and Paolo Ienne.
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["Speculative Dataflow Circuits."](https://doi.org/10.1145/3289602.3293914)
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Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). ACM, 2019.
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DOI: 10.1145/3289602.3293914
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Adds speculation to elastic circuits: units issue speculatively and squash on misspeculation via a token/anti-token discard mechanism, raising throughput on control-dependent code.
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Josipovic, Lana, et al.
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["Resource Sharing in Dataflow Circuits."](https://doi.org/10.1109/FCCM53951.2022.9786084)
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2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2022.
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Extended version: ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2023. DOI: 10.1145/3597614
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Shares expensive functional units among operations in a dataflow circuit without introducing deadlock, using arbitration that respects the elastic handshake and the circuit's throughput constraints.
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Xu, Jiahui, Emmet Murphy, Jordi Cortadella, and Lana Josipovic.
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["Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking."](https://doi.org/10.1145/3543622.3573196)
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Proceedings of the 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). ACM, 2023.
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DOI: 10.1145/3543622.3573196
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Uses formal model checking to find where runtime dynamism is unnecessary and replace it with cheaper static scheduling, cutting handshake and buffering overhead without losing correctness.
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Elakhras, Ayatallah, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, and Paolo Ienne.
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["Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits."](https://doi.org/10.1145/3543622.3573050)
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Proceedings of the 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). ACM, 2023.
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DOI: 10.1145/3543622.3573050
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Efficient load-store-queue allocation that preserves memory ordering in dataflow circuits with less area and latency than prior LSQ schemes.
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Elakhras, Ayatallah, Andrea Guerrieri, Lana Josipovic, and Paolo Ienne.
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["Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits."](https://doi.org/10.1145/3626202.3637556)
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Proceedings of the 2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). ACM, 2024.
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DOI: 10.1145/3626202.3637556
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Enables more out-of-order execution in dataflow circuits, letting independent tokens overtake stalled ones to raise throughput on data-dependent workloads.
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Elakhras, Ayatallah, et al.
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["Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits."](https://doi.org/10.1145/3779212.3790166)
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Proceedings of the 2026 International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM, 2026.
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DOI: 10.1145/3779212.3790166
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Formally verified framework for out-of-order execution in dataflow circuits, proving the correctness of the token reordering that earlier throughput work introduced.
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### Asynchronous
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Yakovlev, A. V., et al.
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["Modelling, analysis and synthesis of asynchronous control circuits using Petri nets."](https://www.researchgate.net/profile/Alex_Yakovlev/publication/220686772_Modelling_analysis_and_synthesis_of_asynchronous_control_circuits_using_Petri_nets/links/541030420cf2f2b29a3f1e73.pdf)
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["Modelling, analysis and synthesis of asynchronous control circuits using Petri nets."](https://doi.org/10.1016/S0167-9260(96)00010-7)
74182
Integration, the VLSI journal 21.3 (1996): 143-170.
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DOI: 10.1016/S0167-9260(96)00010-7
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Survey of Petri-net / STG based methods for specifying, analyzing, and synthesizing asynchronous control circuits; groundwork for the concurrency models used in elastic control.
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Cortadella, Jordi and Kishinevsky, Michael and Kondratyev, Alex and Lavagno, Luciano and Yakovlev, Alex;
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Logic synthesis for asynchronous controllers and interfaces;2012
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Logic synthesis for asynchronous controllers and interfaces; 2012
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Book-length treatment (same as the Springer entry above) of asynchronous controller synthesis from STGs; the reference implementation is the Petrify tool.
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### Transformations
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81194
Galceran-Oms, Marc, et al.
82195
["Microarchitectural transformations using elasticity."](http://www.cs.upc.edu/~jordicf/gavina/BIB/files/JECTS2011_MicroarchTransform.pdf)
83196
ACM Journal on Emerging Technologies in Computing Systems (JETC) 7.4 (2011): 18.
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Shows how elasticity enables correctness-preserving microarchitectural transforms — retiming, recycling, bypasses, variable-latency units — automating transformations that are normally done by hand.
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Bufistov, Dmitry E., et al.
86201
["Retiming and recycling for elastic systems with early evaluation."](http://www.cs.upc.edu/~jordicf/Research/gavina/BIB/files/rr_early_dac09.pdf)
87202
Proceedings of the 46th Annual Design Automation Conference. ACM, 2009.
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Jointly optimizes retiming (moving registers) and recycling (adding empty buffers) to maximize elastic-system throughput, extended to handle early evaluation.
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89206
Carloni, Luca P., and Alberto L. Sangiovanni-Vincentelli.
90207
["Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits."](http://www1.cs.columbia.edu/~luca/research/rscSBCCI03.pdf)
91208
SBCCI. Vol. 3. 2003.
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Shows recycling (inserting empty/bubble stations) complements retiming, and combining both optimizes the throughput of latency-insensitive/synchronous circuits.
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93212
### Performance
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95214
Júlvez, Jorge, Jordi Cortadella, and Michael Kishinevsky.
96215
["On the performance evaluation of multi-guarded marked graphs with single-server semantics."](http://webdiis.unizar.es/~julvez/pub/09deds.pdf)
97216
Discrete Event Dynamic Systems 20.3 (2010): 377-407.
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Analytical throughput evaluation of marked graphs with guards and single-server semantics — the modeling machinery used to compute steady-state throughput of elastic systems.
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99220
Ramamoorthy, C. V., and Gary S. Ho.
100221
["Performance evaluation of asynchronous concurrent systems using Petri nets."](http://www.computer.org/csdl/trans/ts/1980/05/01702760.pdf)
101222
Software Engineering, IEEE Transactions on 5 (1980): 440-449.
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Classic method for computing cycle time / throughput of concurrent systems modeled as timed Petri nets via critical-cycle (maximum mean cycle) analysis.
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103226
Commoner, Frederic, et al.
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["Marked directed graphs."](http://www.sciencedirect.com/science/article/pii/S0022000071800132/pdf?md5=7fb2ad96e4f09b235e15a6b503dbd380&pid=1-s2.0-S0022000071800132-main.pdf)
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["Marked directed graphs."](https://doi.org/10.1016/S0022-0000(71)80013-2)
105228
Journal of Computer and System Sciences 5.5 (1971): 511-523.
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DOI: 10.1016/S0022-0000(71)80013-2
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Foundational theory of marked graphs (a Petri-net subclass): liveness, safeness, and token conservation around cycles. Mathematical basis for elastic throughput analysis.
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## DataFlow
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109235
Lee, Edward Ashford, and David G. Messerschmitt.
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["Static scheduling of synchronous data flow programs for digital signal processing."](http://www.eecs.ucf.edu/~mingjie/ECM6308/papers/%20Static%20Scheduling%20of%20Synchronous%20Data%20Flow%20Programs%20for%20Digital%20Signal%20Processing.pdf)
236+
["Static scheduling of synchronous data flow programs for digital signal processing."](https://doi.org/10.1109/TC.1987.5009446)
111237
Computers, IEEE Transactions on 100.1 (1987): 24-35.
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DOI: 10.1109/TC.1987.5009446
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Defines Synchronous Data Flow: actors with fixed token production/consumption rates, schedulable at compile time via balance equations and periodic schedules. Foundational dataflow model of computation.
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113242
Johnston, Wesley M., J. R. Hanna, and Richard J. Millar.
114-
["Advances in dataflow programming languages."](http://www.cs.ucf.edu/~dcm/Teaching/COT4810-Spring2011/Literature/DataFlowProgrammingLanguages.pdf)
243+
["Advances in dataflow programming languages."](https://doi.org/10.1145/1013208.1013209)
115244
ACM Computing Surveys (CSUR) 36.1 (2004): 1-34.
116245

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Survey of the history and concepts of dataflow programming languages, from tagged-token machines to modern dataflow languages.
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117248
Benini, Luca, et al.
118249
["Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs."](http://si2.epfl.ch/~demichel/publications/archive/1998/CADICSvol17iss3Mar98pg220.pdf)
119250
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 17.3 (1998).
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Variable-latency functional units that detect and signal completion early on common-case inputs — a performance technique naturally wrapped by elastic/handshake control.
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121254
## DAG
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123256
Yu, Cunxi, et al.
124257
["DAG-Aware Logic Synthesis of Datapaths."](http://www.ecs.umass.edu/ece/labs/vlsicad/papers/dac-2016-cunxi-ibm-muxmove.pdf)
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Datapath logic synthesis that exploits DAG structure (mux movement, sub-expression sharing) to optimize area and delay.
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126261
Mohanty, Saraju P., and N. Ranganathan.
127-
["Energy efficient scheduling for datapath synthesis."](http://www.smohanty.org/Publications_Conferences/2003/MohantyVLSID2003Energy.pdf)
262+
["Energy efficient scheduling for datapath synthesis."](https://doi.org/10.1109/ICVD.2003.1183175)
128263
VLSI Design, 2003. Proceedings. 16th International Conference on. IEEE, 2003.
264+
DOI: 10.1109/ICVD.2003.1183175
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High-level-synthesis scheduling that minimizes energy in the resulting datapath under resource and timing constraints.
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## Projects
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@@ -136,3 +274,5 @@ https://github.com/bvgastel/xmas
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https://github.com/Rotsor/phd
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https://bitbucket.org/alanmi/abc
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https://github.com/EPFL-LAP/dynamatic

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