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RISC-V64 arch. port support RVV Extension;
1 parent 0c92f48 commit 2f1fc52

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6 files changed

+369
-4
lines changed

6 files changed

+369
-4
lines changed

‎ports/risc-v64/gnu/inc/tx_port.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,15 +105,23 @@ typedef unsigned short USHORT;
105105
thread creation is less than this value, the thread create call will return an error. */
106106

107107
#ifndef TX_MINIMUM_STACK
108-
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
108+
#if defined(__riscv_vector)
109+
#define TX_MINIMUM_STACK (1024 + 16448) /* Minimum stack size for this port */
110+
#else
111+
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
112+
#endif
109113
#endif
110114

111115

112116
/* Define the system timer thread's default stack size and priority. These are only applicable
113117
if TX_TIMER_PROCESS_IN_ISR is not defined. */
114118

115119
#ifndef TX_TIMER_THREAD_STACK_SIZE
116-
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
120+
#if defined(__riscv_vector)
121+
#define TX_TIMER_THREAD_STACK_SIZE (1024 + 16448) /* Default timer thread stack size */
122+
#else
123+
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
124+
#endif
117125
#endif
118126

119127
#ifndef TX_TIMER_THREAD_PRIORITY

‎ports/risc-v64/gnu/src/tx_thread_context_restore.S‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,34 @@ _tx_thread_context_restore:
138138
csrw fcsr, t0
139139
#endif
140140

141+
#if defined(__riscv_vector)
142+
/* Recover vector registers v0-v31 */
143+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
144+
addi t1, sp, 64*8
145+
#else
146+
addi t1, sp, 31*8
147+
#endif
148+
addi t2, t1, 4*8
149+
vsetvli t3, zero, e8, m8, ta, ma
150+
vle8.v v0, (t2) // Recover v0 ~ v7
151+
add t2, t2, t3
152+
vle8.v v8, (t2) // Recover v8 ~ v15
153+
add t2, t2, t3
154+
vle8.v v16, (t2) // Recover v16 ~ v23
155+
add t2, t2, t3
156+
vle8.v v24, (t2) // Recover v24 ~ v31
157+
add t2, t2, t3
158+
159+
/* Recover vector CSRs */
160+
ld t2, 0*8(t1)
161+
ld t3, 1*8(t1)
162+
ld t4, 2*8(t1)
163+
vsetvl zero, t4, t3
164+
csrw vstart, t2
165+
ld t4, 3*8(t1)
166+
csrw vcsr, t4
167+
#endif
168+
141169
/* Recover standard registers. */
142170

143171
/* Restore registers,
@@ -168,6 +196,10 @@ _tx_thread_context_restore:
168196
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
169197
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
170198
or t1, t1, t0
199+
#endif
200+
#if defined(__riscv_vector)
201+
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
202+
or t1, t1, t0
171203
#endif
172204
csrw mstatus, t1 // Update mstatus safely
173205

@@ -194,6 +226,21 @@ _tx_thread_context_restore:
194226
#else
195227
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
196228
#endif
229+
230+
#if defined(__riscv_vector)
231+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
232+
addi t0, sp, -65*8
233+
#else
234+
addi t0, sp, -32*8
235+
#endif
236+
csrr t1, vlenb // Get vector register byte length
237+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
238+
addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr
239+
add sp, sp, t1 // Recover vector stack frame
240+
241+
ld t1, 18*8(t0) // Recover t1
242+
ld t0, 19*8(t0) // Recover t0
243+
#endif
197244
mret // Return to point of interrupt
198245

199246
/* } */
@@ -273,6 +320,34 @@ _tx_thread_no_preempt_restore:
273320
csrw fcsr, t0 // Restore fcsr
274321
#endif
275322

323+
#if defined(__riscv_vector)
324+
/* Recover vector registers v0-v31 */
325+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
326+
addi t1, sp, 64*8
327+
#else
328+
addi t1, sp, 31*8
329+
#endif
330+
addi t2, t1, 4*8
331+
vsetvli t3, zero, e8, m8, ta, ma
332+
vle8.v v0, (t2) // Recover v0 ~ v7
333+
add t2, t2, t3
334+
vle8.v v8, (t2) // Recover v8 ~ v15
335+
add t2, t2, t3
336+
vle8.v v16, (t2) // Recover v16 ~ v23
337+
add t2, t2, t3
338+
vle8.v v24, (t2) // Recover v24 ~ v31
339+
add t2, t2, t3
340+
341+
/* Recover vector CSRs */
342+
ld t2, 0*8(t1)
343+
ld t3, 1*8(t1)
344+
ld t4, 2*8(t1)
345+
vsetvl zero, t4, t3
346+
csrw vstart, t2
347+
ld t4, 3*8(t1)
348+
csrw vcsr, t4
349+
#endif
350+
276351
/* Recover the saved context and return to the point of interrupt. */
277352

278353
/* Recover standard registers. */
@@ -294,6 +369,10 @@ _tx_thread_no_preempt_restore:
294369
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
295370
li t0, 0x2000 // Set FS bits for FP state
296371
or t1, t1, t0
372+
#endif
373+
#if defined(__riscv_vector)
374+
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
375+
or t1, t1, t0
297376
#endif
298377
csrw mstatus, t1 // Update mstatus safely
299378

@@ -320,6 +399,21 @@ _tx_thread_no_preempt_restore:
320399
#else
321400
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
322401
#endif
402+
403+
#if defined(__riscv_vector)
404+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
405+
addi t0, sp, -65*8
406+
#else
407+
addi t0, sp, -32*8
408+
#endif
409+
csrr t1, vlenb // Get vector register byte length
410+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
411+
addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr
412+
add sp, sp, t1 // Recover vector stack frame
413+
414+
ld t1, 18*8(t0) // Recover t1
415+
ld t0, 19*8(t0) // Recover t0
416+
#endif
323417
mret // Return to point of interrupt
324418

325419
/* }
@@ -362,6 +456,36 @@ _tx_thread_preempt_restore:
362456
fsd f27, 58*8(t0) // Store fs11
363457
#endif
364458

459+
#if defined(__riscv_vector)
460+
/* Store vector registers and CSRs */
461+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
462+
addi t1, t0, 64*8
463+
#else
464+
addi t1, t0, 31*8
465+
#endif
466+
/* Store vector CSRs */
467+
csrr t2, vstart // Store vstart
468+
sd t2, 0*8(t1)
469+
csrr t2, vtype // Store vtype
470+
sd t2, 1*8(t1)
471+
csrr t2, vl // Store vl
472+
sd t2, 2*8(t1)
473+
csrr t2, vcsr // Store vcsr
474+
sd t2, 3*8(t1)
475+
476+
/* Store vector registers v0-v31 */
477+
addi t2, t1, 4*8
478+
vsetvli t3, zero, e8, m8, ta, ma
479+
vse8.v v0, 0(t2) // Store v0 ~ v7
480+
add t2, t2, t3
481+
vse8.v v8, 0(t2) // Store v8 ~ v15
482+
add t2, t2, t3
483+
vse8.v v16, 0(t2) // Store v16 ~ v23
484+
add t2, t2, t3
485+
vse8.v v24, 0(t2) // Store v24 ~ v31
486+
add t2, t2, t3
487+
#endif
488+
365489
/* Store standard preserved registers. */
366490

367491
sd x9, 11*8(t0) // Store s1

‎ports/risc-v64/gnu/src/tx_thread_context_save.S‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,36 @@ _tx_thread_context_save:
151151
sd t0, 63*8(sp) // Store fcsr
152152
#endif
153153

154+
#if defined(__riscv_vector)
155+
/* Store vector registers and CSRs */
156+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
157+
addi t1, sp, 64*8
158+
#else
159+
addi t1, sp, 31*8
160+
#endif
161+
/* Store vector CSRs */
162+
csrr t2, vstart // Store vstart
163+
sd t2, 0*8(t1)
164+
csrr t2, vtype // Store vtype
165+
sd t2, 1*8(t1)
166+
csrr t2, vl // Store vl
167+
sd t2, 2*8(t1)
168+
csrr t2, vcsr // Store vcsr
169+
sd t2, 3*8(t1)
170+
171+
/* Store vector registers v0-v31 */
172+
addi t2, t1, 4*8
173+
vsetvli t3, zero, e8, m8, ta, ma
174+
vse8.v v0, 0(t2) // Store v0 ~ v7
175+
add t2, t2, t3
176+
vse8.v v8, 0(t2) // Store v8 ~ v15
177+
add t2, t2, t3
178+
vse8.v v16, 0(t2) // Store v16 ~ v23
179+
add t2, t2, t3
180+
vse8.v v24, 0(t2) // Store v24 ~ v31
181+
add t2, t2, t3
182+
#endif
183+
154184
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
155185
call _tx_execution_isr_enter // Call the ISR execution enter function
156186
#endif
@@ -241,6 +271,36 @@ _tx_thread_not_nested_save:
241271
sd t0, 63*8(sp) // Store fcsr
242272
#endif
243273

274+
#if defined(__riscv_vector)
275+
/* Store vector registers and CSRs */
276+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
277+
addi t1, sp, 64*8
278+
#else
279+
addi t1, sp, 31*8
280+
#endif
281+
/* Store vector CSRs */
282+
csrr t2, vstart // Store vstart
283+
sd t2, 0*8(t1)
284+
csrr t2, vtype // Store vtype
285+
sd t2, 1*8(t1)
286+
csrr t2, vl // Store vl
287+
sd t2, 2*8(t1)
288+
csrr t2, vcsr // Store vcsr
289+
sd t2, 3*8(t1)
290+
291+
/* Store vector registers v0-v31 */
292+
addi t2, t1, 4*8
293+
vsetvli t3, zero, e8, m8, ta, ma
294+
vse8.v v0, 0(t2) // Store v0 ~ v7
295+
add t2, t2, t3
296+
vse8.v v8, 0(t2) // Store v8 ~ v15
297+
add t2, t2, t3
298+
vse8.v v16, 0(t2) // Store v16 ~ v23
299+
add t2, t2, t3
300+
vse8.v v24, 0(t2) // Store v24 ~ v31
301+
add t2, t2, t3
302+
#endif
303+
244304
/* Save the current stack pointer in the thread's control block. */
245305
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */
246306

@@ -280,4 +340,19 @@ _tx_thread_idle_system_save:
280340
#else
281341
addi sp, sp, 32*8 // Recover the reserved stack space
282342
#endif
343+
344+
#if defined(__riscv_vector)
345+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
346+
addi t0, sp, -65*8
347+
#else
348+
addi t0, sp, -32*8
349+
#endif
350+
csrr t1, vlenb // Get vector register byte length
351+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
352+
addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr
353+
add sp, sp, t1 // Recover vector stack frame
354+
355+
ld t1, 18*8(t0) // Recover t1
356+
ld t0, 19*8(t0) // Recover t0
357+
#endif
283358
ret // Return to calling ISR

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