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Merge pull request #502 from quintauris-tech/riscv32-clang-port
Added a RV32 Clang port
2 parents b3e8a9a + 49439bf commit 385d39f

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‎cmake/riscv32-clang-unknown-elf.cmake‎

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# Toolchain settings
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set(CMAKE_C_COMPILER clang-18)
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set(CMAKE_CXX_COMPILER clang++-18)
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#set(AS llvm-as)
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#set(AR llvm-ar)
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#set(OBJCOPY llvm-objcopy)
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#set(OBJDUMP llvm-objdump-18)
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#set(SIZE llvm-size)
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set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
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set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
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set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
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set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
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# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts
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set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
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set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags")
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set(CMAKE_CXX_FLAGS "${CXXFLAGS}" CACHE INTERNAL "cxx compiler flags")
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set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags")
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set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags")
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SET(CMAKE_C_FLAGS_DEBUG "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -g" CACHE INTERNAL "c debug compiler flags")
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SET(CMAKE_CXX_FLAGS_DEBUG "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -g" CACHE INTERNAL "cxx debug compiler flags")
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SET(CMAKE_ASM_FLAGS_DEBUG "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -g" CACHE INTERNAL "asm debug compiler flags")
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SET(CMAKE_C_FLAGS_RELEASE "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -O3" CACHE INTERNAL "c release compiler flags")
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SET(CMAKE_CXX_FLAGS_RELEASE "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -O3" CACHE INTERNAL "cxx release compiler flags")
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SET(CMAKE_ASM_FLAGS_RELEASE "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32" CACHE INTERNAL "asm release compiler flags")

‎cmake/riscv32_clang.cmake‎

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# Name of the target
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set(CMAKE_SYSTEM_NAME Generic)
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set(CMAKE_SYSTEM_PROCESSOR risc-v32)
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IF(DEFINED $ENV{GCC_INSTALL_PREFIX})
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SET(GCC_INSTALL_PREFIX "$ENV{GCC_INSTALL_PREFIX}" CACHE INTERNAL "" FORCE)
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ELSE()
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SET(GCC_INSTALL_PREFIX "/opt/riscv_rv32ima" CACHE INTERNAL "" FORCE)
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ENDIF()
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set(THREADX_ARCH "risc-v32")
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set(THREADX_TOOLCHAIN "clang")
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set(ARCH_FLAGS "--sysroot=${GCC_INSTALL_PREFIX}/riscv32-unknown-elf --target=riscv32 -g -march=rv32ima_zicsr -mabi=ilp32")
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set(CFLAGS "${ARCH_FLAGS}")
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set(ASFLAGS "${ARCH_FLAGS}")
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set(LDFLAGS "--no-dynamic-linker -m elf32lriscv -static -nostdlib")
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include(${CMAKE_CURRENT_LIST_DIR}/riscv32-clang-unknown-elf.cmake)

‎ports/risc-v32/clang/CMakeLists.txt‎

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target_sources(${PROJECT_NAME}
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PRIVATE
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# {{BEGIN_TARGET_SOURCES}}
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${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
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# {{END_TARGET_SOURCES}}
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)
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target_include_directories(${PROJECT_NAME}
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PUBLIC
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${CMAKE_CURRENT_LIST_DIR}/inc
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)

‎ports/risc-v32/clang/example_build/qemu_virt/board.c‎

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/***************************************************************************
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* Copyright (c) 2026 Quintauris
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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#include "plic.h"
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#include "hwtimer.h"
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#include "uart.h"
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#include <stdint.h>
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#include <stddef.h>
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void *memset(void *des, int c,size_t n)
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{
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if((des == NULL) || n <=0)
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return (void*)des;
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char* t = (char*)des;
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int i;
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for(i=0;i<n;i++)
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t[i]=c;
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return t;
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}
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int board_init(void)
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{
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int ret;
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ret = plic_init();
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if(ret)
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return ret;
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ret = uart_init();
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if(ret)
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return ret;
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ret = hwtimer_init();
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if(ret)
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return ret;
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return 0;
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}

‎ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh‎

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#!/bin/bash
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pushd ../../../../../
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#cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake .
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cmake -Bbuild -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake .
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cmake --build ./build/
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popd

‎ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh‎

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#!/bin/bash
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DIRNAME=$(dirname "$0")
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BASEDIR=$DIRNAME/../../../../..
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mkdir -p build
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CC=clang-18
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LD=ld.lld-18
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$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.s
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -D__ASSEMBLER__ -o build/tx_initialize_low_level.obj -c tx_initialize_low_level.S
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/board.obj -c board.c
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/hwtimer.obj -c hwtimer.c
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/plic.obj -c plic.c
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/trap.obj -c trap.c
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/uart.obj -c uart.c
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$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/demo_threadx.obj -c demo_threadx.c
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$LD -Tlink.lds --no-dynamic-linker -m elf32lriscv -static -nostdlib -o build/demo_threadx.elf --Map=build/demo_threadx.map build/entry.obj build/tx_initialize_low_level.obj build/board.obj build/hwtimer.obj build/plic.obj build/trap.obj build/uart.obj build/demo_threadx.obj $BASEDIR/build/libthreadx.a

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