Fixes to the RISC-V32 architecture port layer for Clang.

Author: francisco-merino-quintauris

ports/risc-v32/clang/README.md

@@ -228,6 +228,8 @@ UINT    status;
         /* Send message to queue 0.  */
         status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
 
+        tx_thread_sleep(2);
+
         /* Check completion status.  */
         if (status != TX_SUCCESS) {
             puts("[Thread 1] ERROR: Failed to send message!");
@@ -257,6 +259,8 @@ UINT    status;
         /* Retrieve a message from the queue.  */
         status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
 
+        tx_thread_sleep(2);
+
         /* Check completion status and make sure the message is what we
            expected.  */
         if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)){

ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c

@@ -67,12 +67,12 @@
     .extern  _tx_thread_context_restore
     trap_entry:
 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
-	addi sp, sp, -65*REGBYTES         // Allocate space for all registers - with floating point enabled
+	addi sp, sp, -65*4                // Allocate space for all registers - with floating point enabled
 #else
-	addi sp, sp, -32*REGBYTES         // Allocate space for all registers - without floating point enabled
+	addi sp, sp, -32*4                // Allocate space for all registers - without floating point enabled
 #endif
 
-	STORE   x1, 28*REGBYTES(sp)       // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
+	sw      x1, 28*4(sp)              // Store RA, 28*4(because call will override ra [ra is a calle register in riscv])
 
     	call    _tx_thread_context_save
 

ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S

@@ -53,25 +53,7 @@
 #ifndef TX_PORT_H
 #define TX_PORT_H
 
-#ifdef __ASSEMBLER__
-
-
-#if __riscv_xlen == 64
-# define SLL32    sllw
-# define STORE    sd
-# define LOAD     ld
-# define LWU      lwu
-# define LOG_REGBYTES 3
-#else
-# define SLL32    sll
-# define STORE    sw
-# define LOAD     lw
-# define LWU      lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#else   /*not __ASSEMBLER__ */
+#ifndef __ASSEMBLER__
 
 /* Include for memset.  */
 #include <string.h>

ports/risc-v32/clang/inc/tx_port.h

@@ -7,10 +7,13 @@
 
 Prerequisites
 - Install a RISC-V32 bare-metal Clang toolchain
-- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix
-- Common source: https://github.com/riscv-collab/riscv-gnu-toolchain
+- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix.
+  Common source: https://github.com/riscv-collab/riscv-gnu-toolchain
 
-Verify the Clang toolchaing:
+The GNU toolchain is needed because the Clang toolchain does not include some
+standard headers and libraries, i.e. "string.h".
+
+Verify the Clang toolchain:
   clang --version
 
 Verify the GCC toolchain:
@@ -21,6 +24,9 @@ CMake-based build (recommended)
 
 From the ThreadX top-level directory:
 
+  Set environment variable "GCC_INSTALL_PREFIX" with the location of the 
+  GNU toolchain, i.e., export GCC_INSTALL_PREFIX=/opt/riscv_rv32ima
+
   cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake .
   cmake --build ./build/