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Add RISC-V32 QEMU-virt example
This commit introduces the complete example build environment for the RISC-V32/GNU port targeting the QEMU virt machine. It includes basic BSP components, startup code, drivers, linker script, and a minimal ThreadX demo application. Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
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‎ports/risc-v32/gnu/example_build/qemu_virt/board.c‎

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/***************************************************************************
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* Copyright (c) 2025 10xEngineers
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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#include "plic.h"
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#include "hwtimer.h"
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#include "uart.h"
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#include <stdint.h>
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#include <stddef.h>
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void *memset(const void *des, int c,size_t n)
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{
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if((des == NULL) || n <=0)
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return (void*)des;
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char* t = (char*)des;
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int i;
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for(i=0;i<n;i++)
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t[i]=c;
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return t;
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}
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int board_init(void)
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{
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int ret;
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ret = plic_init();
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if(ret)
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return ret;
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ret = uart_init();
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if(ret)
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return ret;
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ret = hwtimer_init();
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if(ret)
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return ret;
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return 0;
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}

‎ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh‎

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#!/bin/bash
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pushd ../../../../../
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cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_gnu.cmake .
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cmake --build ./build/
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popd

‎ports/risc-v32/gnu/example_build/qemu_virt/csr.h‎

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/***************************************************************************
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* Copyright (c) 2025 10xEngineers
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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#ifndef RISCV_CSR_H
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#define RISCV_CSR_H
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// Machine Status Register, mstatus
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#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
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#define MSTATUS_MPP_M (3L << 11)
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#define MSTATUS_MPP_S (1L << 11)
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#define MSTATUS_MPP_U (0L << 11)
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#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
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#define MSTATUS_MPIE (1L << 7)
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#define MSTATUS_FS (1L << 13)
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// Machine-mode Interrupt Enable
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#define MIE_MTIE (1L << 7)
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#define MIE_MSIE (1L << 3)
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#define MIE_MEIE (1L << 11)
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#define MIE_STIE (1L << 5) // supervisor timer
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#define MIE_SSIE (1L << 1)
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#define MIE_SEIE (1L << 9)
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// Supervisor Status Register, sstatus
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#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
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#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
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#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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#define SSTATUS_SPIE (1L << 5)
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#define SSTATUS_UPIE (1L << 4)
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// Supervisor Interrupt Enable
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#define SIE_SEIE (1L << 9) // external
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#define SIE_STIE (1L << 5) // timer
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#define SIE_SSIE (1L << 1) // software
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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static inline uint32_t riscv_get_core()
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{
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uint32_t x;
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asm volatile("csrr %0, mhartid" : "=r" (x) );
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return x;
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}
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static inline uint32_t riscv_get_mstatus()
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{
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uint32_t x;
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asm volatile("csrr %0, mstatus" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_mstatus(uint32_t x)
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{
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asm volatile("csrw mstatus, %0" : : "r" (x));
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}
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static inline void riscv_writ_mepc(uint32_t x)
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{
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asm volatile("csrw mepc, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_sstatus()
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{
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uint32_t x;
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asm volatile("csrr %0, sstatus" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_sstatus(uint32_t x)
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{
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asm volatile("csrw sstatus, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_sip()
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{
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uint32_t x;
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asm volatile("csrr %0, sip" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_sip(uint32_t x)
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{
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asm volatile("csrw sip, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_sie()
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{
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uint32_t x;
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asm volatile("csrr %0, sie" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_sie(uint32_t x)
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{
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asm volatile("csrw sie, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_mie()
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{
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uint32_t x;
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asm volatile("csrr %0, mie" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_mie(uint32_t x)
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{
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asm volatile("csrw mie, %0" : : "r" (x));
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}
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static inline void riscv_writ_sepc(uint32_t x)
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{
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asm volatile("csrw sepc, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_sepc()
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{
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uint32_t x;
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asm volatile("csrr %0, sepc" : "=r" (x) );
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return x;
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}
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static inline uint32_t riscv_get_medeleg()
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{
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uint32_t x;
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asm volatile("csrr %0, medeleg" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_medeleg(uint32_t x)
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{
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asm volatile("csrw medeleg, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_mideleg()
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{
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uint32_t x;
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asm volatile("csrr %0, mideleg" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_mideleg(uint32_t x)
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{
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asm volatile("csrw mideleg, %0" : : "r" (x));
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}
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static inline void riscv_writ_stvec(uint32_t x)
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{
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asm volatile("csrw stvec, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_stvec()
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{
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uint32_t x;
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asm volatile("csrr %0, stvec" : "=r" (x) );
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return x;
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}
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static inline uint32_t riscv_get_stimecmp()
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{
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uint32_t x;
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asm volatile("csrr %0, 0x14d" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_stimecmp(uint32_t x)
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{
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asm volatile("csrw 0x14d, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_menvcfg()
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{
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uint32_t x;
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asm volatile("csrr %0, 0x30a" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_menvcfg(uint32_t x)
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{
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asm volatile("csrw 0x30a, %0" : : "r" (x));
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}
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static inline void riscv_writ_pmpcfg0(uint32_t x)
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{
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asm volatile("csrw pmpcfg0, %0" : : "r" (x));
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}
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static inline void riscv_writ_pmpaddr0(uint32_t x)
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{
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asm volatile("csrw pmpaddr0, %0" : : "r" (x));
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}
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static inline void riscv_writ_satp(uint32_t x)
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{
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asm volatile("csrw satp, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_satp()
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{
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uint32_t x;
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asm volatile("csrr %0, satp" : "=r" (x) );
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return x;
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}
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static inline uint32_t riscv_get_scause()
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{
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uint32_t x;
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asm volatile("csrr %0, scause" : "=r" (x) );
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return x;
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}
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static inline uint32_t riscv_get_stval()
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{
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uint32_t x;
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asm volatile("csrr %0, stval" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_mcounteren(uint32_t x)
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{
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asm volatile("csrw mcounteren, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_mcounteren()
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{
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uint32_t x;
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asm volatile("csrr %0, mcounteren" : "=r" (x) );
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return x;
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}
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static inline uint32_t riscv_get_time()
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{
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uint32_t x;
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asm volatile("csrr %0, time" : "=r" (x) );
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return x;
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}
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static inline void riscv_sintr_on()
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{
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uint32_t sstatus = riscv_get_sstatus();
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sstatus |= SSTATUS_SIE;
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riscv_writ_sstatus(sstatus);
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}
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static inline void riscv_sintr_off()
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{
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uint32_t sstatus = riscv_get_sstatus();
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sstatus &= (~SSTATUS_SIE);
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riscv_writ_sstatus(sstatus);
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}
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static inline int riscv_sintr_get()
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{
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uint32_t x = riscv_get_sstatus();
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return (x & SSTATUS_SIE) != 0;
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}
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static inline void riscv_sintr_restore(int x)
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{
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if(x)
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riscv_sintr_on();
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else
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riscv_sintr_off();
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}
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static inline void riscv_mintr_on()
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{
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uint32_t mstatus = riscv_get_mstatus();
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mstatus |= MSTATUS_MIE;
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riscv_writ_mstatus(mstatus);
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}
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static inline void riscv_mintr_off()
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{
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uint32_t mstatus = riscv_get_mstatus();
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mstatus &= (~MSTATUS_MIE);
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riscv_writ_mstatus(mstatus);
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}
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static inline int riscv_mintr_get()
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{
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uint32_t x = riscv_get_mstatus();
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return (x & MSTATUS_MIE) != 0;
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}
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static inline void riscv_mintr_restore(int x)
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{
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if(x)
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riscv_mintr_on();
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else
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riscv_mintr_off();
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}
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static inline uint32_t riscv_get_sp()
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{
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uint32_t x;
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asm volatile("mv %0, sp" : "=r" (x) );
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return x;
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}
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// read and write tp, the thread pointer, which xv6 uses to hold
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// this core's hartid (core number), the index into cpus[].
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static inline uint32_t riscv_get_tp()
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{
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uint32_t x;
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asm volatile("mv %0, tp" : "=r" (x) );
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return x;
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}
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static inline void riscv_writ_tp(uint32_t x)
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{
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asm volatile("mv tp, %0" : : "r" (x));
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}
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static inline uint32_t riscv_get_ra()
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{
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uint32_t x;
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asm volatile("mv %0, ra" : "=r" (x) );
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return x;
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}
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// flush the TLB.
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static inline void sfence_vma()
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{
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// the zero, zero means flush all TLB entries.
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asm volatile("sfence.vma zero, zero");
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}
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#endif // __ASSEMBLER__
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#endif

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