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Merge pull request #508 from goodnorning/feature/rv64_rvv_support
Added rv64 rvv support
2 parents 57e317a + dfafc96 commit a0dc185

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11 files changed

+393
-4
lines changed

11 files changed

+393
-4
lines changed

‎ports/risc-v64/gnu/example_build/qemu_virt/csr.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
2323
#define MSTATUS_MPIE (1L << 7)
2424
#define MSTATUS_FS (1L << 13)
25+
#define MSTATUS_VS (1L << 9)
2526

2627
// Machine-mode Interrupt Enable
2728
#define MIE_MTIE (1L << 7)

‎ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,13 @@
44

55
#include "tx_api.h"
66
#include "uart.h"
7+
#if defined(__riscv_vector)
8+
#define DEMO_STACK_SIZE (1024 + 16448) /* 16448 for RVV Extension */
9+
#define DEMO_BYTE_POOL_SIZE (9180 + 148032) /* 148032 for RVV Extension */
10+
#else
711
#define DEMO_STACK_SIZE 1024
812
#define DEMO_BYTE_POOL_SIZE 9180
13+
#endif
914
#define DEMO_BLOCK_POOL_SIZE 100
1015
#define DEMO_QUEUE_SIZE 100
1116

‎ports/risc-v64/gnu/example_build/qemu_virt/entry.s‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,11 @@ _start:
4141
li x30, 0
4242
li x31, 0
4343
la t0, _sysstack_start
44+
#ifdef __riscv_vector
45+
li t1, 0x5000
46+
#else
4447
li t1, 0x1000
48+
#endif
4549
add sp, t0, t1
4650
la t0, _bss_start
4751
la t1, _bss_end

‎ports/risc-v64/gnu/example_build/qemu_virt/link.lds‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,9 @@ SECTIONS
4242
. = ALIGN(4096);
4343
_sysstack_start = .;
4444
. += 0x1000;
45+
#ifdef __riscv_vector
46+
. += 0x4000;
47+
#endif
4548
_sysstack_end = .;
4649
}
4750

‎ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,13 @@
6666
#else
6767
addi sp, sp, -256 // Allocate space for all registers - without floating point enabled (32*8)
6868
#endif
69+
#if defined(__riscv_vector)
70+
/* Allocate space for vector registers */
71+
csrr t4, vlenb
72+
slli t4, t4, 5
73+
addi t4, t4, 4*8
74+
sub sp, sp, t4
75+
#endif
6976

7077
sd x1, 224(sp) // Store RA (28*8 = 224, because call will override ra [ra is a callee register in riscv])
7178

@@ -149,6 +156,10 @@ _tx_initialize_low_level:
149156
li t0, MSTATUS_FS
150157
csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv
151158
fscsr x0
159+
#endif
160+
#ifdef __riscv_vector
161+
li t0, MSTATUS_VS
162+
csrrs zero, mstatus, t0 // set MSTATUS_VS bit to open vector isa in riscv
152163
#endif
153164
addi sp, sp, -8
154165
sd ra, 0(sp)

‎ports/risc-v64/gnu/inc/tx_port.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -100,15 +100,23 @@ typedef unsigned short USHORT;
100100
thread creation is less than this value, the thread create call will return an error. */
101101

102102
#ifndef TX_MINIMUM_STACK
103-
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
103+
#if defined(__riscv_vector)
104+
#define TX_MINIMUM_STACK (1024 + 16448) /* Minimum stack size for this port */
105+
#else
106+
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
107+
#endif
104108
#endif
105109

106110

107111
/* Define the system timer thread's default stack size and priority. These are only applicable
108112
if TX_TIMER_PROCESS_IN_ISR is not defined. */
109113

110114
#ifndef TX_TIMER_THREAD_STACK_SIZE
111-
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
115+
#if defined(__riscv_vector)
116+
#define TX_TIMER_THREAD_STACK_SIZE (1024 + 16448) /* Default timer thread stack size */
117+
#else
118+
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
119+
#endif
112120
#endif
113121

114122
#ifndef TX_TIMER_THREAD_PRIORITY

‎ports/risc-v64/gnu/src/tx_thread_context_restore.S‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,34 @@ _tx_thread_context_restore:
133133
csrw fcsr, t0
134134
#endif
135135

136+
#if defined(__riscv_vector)
137+
/* Recover vector registers v0-v31 */
138+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
139+
addi t1, sp, 64*8
140+
#else
141+
addi t1, sp, 31*8
142+
#endif
143+
addi t2, t1, 4*8
144+
vsetvli t3, zero, e8, m8, ta, ma
145+
vle8.v v0, (t2) // Recover v0 ~ v7
146+
add t2, t2, t3
147+
vle8.v v8, (t2) // Recover v8 ~ v15
148+
add t2, t2, t3
149+
vle8.v v16, (t2) // Recover v16 ~ v23
150+
add t2, t2, t3
151+
vle8.v v24, (t2) // Recover v24 ~ v31
152+
add t2, t2, t3
153+
154+
/* Recover vector CSRs */
155+
ld t2, 0*8(t1)
156+
ld t3, 1*8(t1)
157+
ld t4, 2*8(t1)
158+
vsetvl zero, t4, t3
159+
csrw vstart, t2
160+
ld t4, 3*8(t1)
161+
csrw vcsr, t4
162+
#endif
163+
136164
/* Recover standard registers. */
137165

138166
/* Restore registers,
@@ -163,6 +191,10 @@ _tx_thread_context_restore:
163191
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
164192
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
165193
or t1, t1, t0
194+
#endif
195+
#if defined(__riscv_vector)
196+
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
197+
or t1, t1, t0
166198
#endif
167199
csrw mstatus, t1 // Update mstatus safely
168200

@@ -189,6 +221,21 @@ _tx_thread_context_restore:
189221
#else
190222
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
191223
#endif
224+
225+
#if defined(__riscv_vector)
226+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
227+
addi t0, sp, -65*8
228+
#else
229+
addi t0, sp, -32*8
230+
#endif
231+
csrr t1, vlenb // Get vector register byte length
232+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
233+
addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr
234+
add sp, sp, t1 // Recover vector stack frame
235+
236+
ld t1, 18*8(t0) // Recover t1
237+
ld t0, 19*8(t0) // Recover t0
238+
#endif
192239
mret // Return to point of interrupt
193240

194241
/* } */
@@ -268,6 +315,34 @@ _tx_thread_no_preempt_restore:
268315
csrw fcsr, t0 // Restore fcsr
269316
#endif
270317

318+
#if defined(__riscv_vector)
319+
/* Recover vector registers v0-v31 */
320+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
321+
addi t1, sp, 64*8
322+
#else
323+
addi t1, sp, 31*8
324+
#endif
325+
addi t2, t1, 4*8
326+
vsetvli t3, zero, e8, m8, ta, ma
327+
vle8.v v0, (t2) // Recover v0 ~ v7
328+
add t2, t2, t3
329+
vle8.v v8, (t2) // Recover v8 ~ v15
330+
add t2, t2, t3
331+
vle8.v v16, (t2) // Recover v16 ~ v23
332+
add t2, t2, t3
333+
vle8.v v24, (t2) // Recover v24 ~ v31
334+
add t2, t2, t3
335+
336+
/* Recover vector CSRs */
337+
ld t2, 0*8(t1)
338+
ld t3, 1*8(t1)
339+
ld t4, 2*8(t1)
340+
vsetvl zero, t4, t3
341+
csrw vstart, t2
342+
ld t4, 3*8(t1)
343+
csrw vcsr, t4
344+
#endif
345+
271346
/* Recover the saved context and return to the point of interrupt. */
272347

273348
/* Recover standard registers. */
@@ -289,6 +364,10 @@ _tx_thread_no_preempt_restore:
289364
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
290365
li t0, 0x2000 // Set FS bits for FP state
291366
or t1, t1, t0
367+
#endif
368+
#if defined(__riscv_vector)
369+
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
370+
or t1, t1, t0
292371
#endif
293372
csrw mstatus, t1 // Update mstatus safely
294373

@@ -315,6 +394,21 @@ _tx_thread_no_preempt_restore:
315394
#else
316395
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
317396
#endif
397+
398+
#if defined(__riscv_vector)
399+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
400+
addi t0, sp, -65*8
401+
#else
402+
addi t0, sp, -32*8
403+
#endif
404+
csrr t1, vlenb // Get vector register byte length
405+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
406+
addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr
407+
add sp, sp, t1 // Recover vector stack frame
408+
409+
ld t1, 18*8(t0) // Recover t1
410+
ld t0, 19*8(t0) // Recover t0
411+
#endif
318412
mret // Return to point of interrupt
319413

320414
/* }
@@ -357,6 +451,36 @@ _tx_thread_preempt_restore:
357451
fsd f27, 58*8(t0) // Store fs11
358452
#endif
359453

454+
#if defined(__riscv_vector)
455+
/* Store vector registers and CSRs */
456+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
457+
addi t1, t0, 64*8
458+
#else
459+
addi t1, t0, 31*8
460+
#endif
461+
/* Store vector CSRs */
462+
csrr t2, vstart // Store vstart
463+
sd t2, 0*8(t1)
464+
csrr t2, vtype // Store vtype
465+
sd t2, 1*8(t1)
466+
csrr t2, vl // Store vl
467+
sd t2, 2*8(t1)
468+
csrr t2, vcsr // Store vcsr
469+
sd t2, 3*8(t1)
470+
471+
/* Store vector registers v0-v31 */
472+
addi t2, t1, 4*8
473+
vsetvli t3, zero, e8, m8, ta, ma
474+
vse8.v v0, 0(t2) // Store v0 ~ v7
475+
add t2, t2, t3
476+
vse8.v v8, 0(t2) // Store v8 ~ v15
477+
add t2, t2, t3
478+
vse8.v v16, 0(t2) // Store v16 ~ v23
479+
add t2, t2, t3
480+
vse8.v v24, 0(t2) // Store v24 ~ v31
481+
add t2, t2, t3
482+
#endif
483+
360484
/* Store standard preserved registers. */
361485

362486
sd x9, 11*8(t0) // Store s1

‎ports/risc-v64/gnu/src/tx_thread_context_save.S‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,36 @@ _tx_thread_context_save:
146146
sd t0, 63*8(sp) // Store fcsr
147147
#endif
148148

149+
#if defined(__riscv_vector)
150+
/* Store vector registers and CSRs */
151+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
152+
addi t1, sp, 64*8
153+
#else
154+
addi t1, sp, 31*8
155+
#endif
156+
/* Store vector CSRs */
157+
csrr t2, vstart // Store vstart
158+
sd t2, 0*8(t1)
159+
csrr t2, vtype // Store vtype
160+
sd t2, 1*8(t1)
161+
csrr t2, vl // Store vl
162+
sd t2, 2*8(t1)
163+
csrr t2, vcsr // Store vcsr
164+
sd t2, 3*8(t1)
165+
166+
/* Store vector registers v0-v31 */
167+
addi t2, t1, 4*8
168+
vsetvli t3, zero, e8, m8, ta, ma
169+
vse8.v v0, 0(t2) // Store v0 ~ v7
170+
add t2, t2, t3
171+
vse8.v v8, 0(t2) // Store v8 ~ v15
172+
add t2, t2, t3
173+
vse8.v v16, 0(t2) // Store v16 ~ v23
174+
add t2, t2, t3
175+
vse8.v v24, 0(t2) // Store v24 ~ v31
176+
add t2, t2, t3
177+
#endif
178+
149179
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
150180
call _tx_execution_isr_enter // Call the ISR execution enter function
151181
#endif
@@ -236,6 +266,36 @@ _tx_thread_not_nested_save:
236266
sd t0, 63*8(sp) // Store fcsr
237267
#endif
238268

269+
#if defined(__riscv_vector)
270+
/* Store vector registers and CSRs */
271+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
272+
addi t1, sp, 64*8
273+
#else
274+
addi t1, sp, 31*8
275+
#endif
276+
/* Store vector CSRs */
277+
csrr t2, vstart // Store vstart
278+
sd t2, 0*8(t1)
279+
csrr t2, vtype // Store vtype
280+
sd t2, 1*8(t1)
281+
csrr t2, vl // Store vl
282+
sd t2, 2*8(t1)
283+
csrr t2, vcsr // Store vcsr
284+
sd t2, 3*8(t1)
285+
286+
/* Store vector registers v0-v31 */
287+
addi t2, t1, 4*8
288+
vsetvli t3, zero, e8, m8, ta, ma
289+
vse8.v v0, 0(t2) // Store v0 ~ v7
290+
add t2, t2, t3
291+
vse8.v v8, 0(t2) // Store v8 ~ v15
292+
add t2, t2, t3
293+
vse8.v v16, 0(t2) // Store v16 ~ v23
294+
add t2, t2, t3
295+
vse8.v v24, 0(t2) // Store v24 ~ v31
296+
add t2, t2, t3
297+
#endif
298+
239299
/* Save the current stack pointer in the thread's control block. */
240300
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */
241301

@@ -275,4 +335,19 @@ _tx_thread_idle_system_save:
275335
#else
276336
addi sp, sp, 32*8 // Recover the reserved stack space
277337
#endif
338+
339+
#if defined(__riscv_vector)
340+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
341+
addi t0, sp, -65*8
342+
#else
343+
addi t0, sp, -32*8
344+
#endif
345+
csrr t1, vlenb // Get vector register byte length
346+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
347+
addi t1, t1, 4*8 // Add vector CSR space: vstart, vtype, vl, vcsr
348+
add sp, sp, t1 // Recover vector stack frame
349+
350+
ld t1, 18*8(t0) // Recover t1
351+
ld t0, 19*8(t0) // Recover t0
352+
#endif
278353
ret // Return to calling ISR

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