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</header><main data-topic="rtos-kernel" id="main-content"><header class="article-hero"><nav aria-label="Breadcrumb" class="article-hero__crumbs"><a href="index.html">Home</a> · <a href="news.html">News</a> · <a href="news.html#topic-rtos-kernel">RTOS & Kernel</a></nav><span class="kicker kicker--purple"><a class="kicker" href="news.html#topic-rtos-kernel">RTOS & Kernel</a></span><h1 class="article-hero__title">EoS RTOS roadmap 2026: tickless idle, RT-IPC, formal verification</h1><p class="article-hero__dek">Three large RTOS bets for 2026: a tickless scheduler with sub-microsecond wake latency, RT-IPC primitives sharing memory across security domains, and a formally verified context-switch path.</p><div class="byline"><span class="byline__avatar">EE</span><span>EoS Editorial</span><span class="byline__sep">·</span><time datetime="2026-04-27">2026-04-27</time><span class="byline__sep">·</span><span>10 min read</span></div><div aria-label="Decorative cover for RTOS & Kernel" class="article-hero__media" role="img"><img alt="Code on a screen — EoS RTOS roadmap 2026" decoding="async" height="520" loading="lazy" src="img/photos/kernel-roadmap.svg" width="1200"/></div></header><div class="layout-article"><article class="layout-article__main prose"><h2>Three big bets</h2><p>The EoS RTOS roadmap for 2026 is shorter and more ambitious than past years. Three engineering bets, each large enough to slip on its own:</p><h2>1. Tickless idle</h2><p>The current 100 Hz tick is fine for most workloads but leaks measurable power on always-on edge devices. The new <code>--tickless</code> kernel mode eliminates the tick entirely; wakeups are driven by timer-queue events. Target wake latency: under 800 ns on Cortex-M7. The hard part is preserving deterministic priority inversion behavior for the existing real-time guarantees.</p><h2>2. RT-IPC across security domains</h2><p>Today, sharing memory between a normal-world task and a secure-world task means a copy. RT-IPC adds a primitive for zero-copy region sharing, with hardware MPU programming and a handshake protocol for ownership transfer. We expect this to land first as an optional EoS-S feature, then graduate to the base RTOS.</p><h2>3. Formal verification of the context switch</h2><p>The kernel's context-switch path is 240 lines of assembly per architecture, and it's been hand-audited dozens of times. We're partnering with two academic groups to produce a machine-checkable proof that the switch preserves register state, satisfies the AAPCS calling convention, and never exposes prior-task secrets. Target: Cortex-M and RV32 complete by Q4.</p><h2>What's not on the list</h2><p>SMP scheduling on more than 4 cores. We continue to believe the right answer for high-core-count systems is a different kernel; EoS targets up-to-quad-core deterministic workloads.</p><div aria-label="Topic" class="article-tags"><span class="byline" style="margin:0">Filed under:</span><a class="topic-chip" href="news.html#topic-rtos-kernel">RTOS & Kernel</a></div><section class="article-readnext"><h2>Read next</h2><div class="article-readnext__grid"><a class="article-card" data-topic="apps-platforms" href="article-eos-platform-launch.html"><div class="article-card__media"><img alt="Embedded systems engineering — platform" height="340" loading="lazy" src="img/photos/alt-platform.svg" width="600"/></div><div class="article-card__body"><span class="kicker">Apps & Platforms</span><h3 class="article-card__title">eos-platform 1.0 lands: one toolchain, every EoS profile</h3><p class="article-card__dek">After eighteen months of incremental releases, the eos-platform meta-distribution reaches 1.0 with stable APIs, a unified package manifest, and reproducible builds across all 14 EoS components.</p><p class="article-card__byline">EoS Editorial · 2026-05-12 · 7 min read</p></div></a><a class="article-card" data-topic="embedded-ai" href="article-eai-llm-bench.html"><div class="article-card__media"><img alt="AI / LLM data visualisation" height="340" loading="lazy" src="img/photos/alt-llm.svg" width="600"/></div><div class="article-card__body"><span class="kicker kicker--purple">Embedded AI</span><h3 class="article-card__title">EAI 0.9 ships INT4 LLM runtime — 11 tok/s on a Cortex-M85</h3><p class="article-card__dek">EAI's new quantized inference path squeezes a 1.3B-parameter model into 312 MB of flash and runs at interactive speed on a 480 MHz microcontroller. We dig into the kernel scheduler that made it possible.</p><p class="article-card__byline">EoS Editorial · 2026-05-10 · 9 min read</p></div></a><a class="article-card" data-topic="neural-interface" href="article-eni-1024-channel-pipeline.html"><div class="article-card__media"><img alt="Neural network synapses" height="340" loading="lazy" src="img/photos/alt-neural.svg" width="600"/></div><div class="article-card__body"><span class="kicker kicker--teal">Neural Interface</span><h3 class="article-card__title">ENI's 1,024-channel pipeline: deterministic spike sorting in 800 µs</h3><p class="article-card__dek">How the Embedded Neural Interface stack moves a thousand-electrode array through filtering, sorting, and decoding inside a single RTOS frame — and why the hardest part wasn't the math.</p><p class="article-card__byline">EoS Editorial · 2026-05-08 · 8 min read</p></div></a></div></section></article><aside aria-label="Sidebar" class="layout-article__sidebar"><section class="widget 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