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Resolve Issue #32: Define peripherals/PPB as absolute symbols in linker scripts (#37)
AI updated the `stm32f405rg-sections.ld`, `stm32f407ve-sections.ld`, and `stm32h753zi-sections.ld` linker scripts to define peripherals and PPB registers as absolute symbol assignments and kept `.bkpsram` / `.bkup_sram` standalone. Human approved the implementation plan, reviewed the changes, and verified the builds.
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Lines changed: 281 additions & 600 deletions

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‎modules/stm32/linkerscripts/stm32f405rg-sections.ld‎

Lines changed: 81 additions & 170 deletions
Original file line numberDiff line numberDiff line change
@@ -1,65 +1,34 @@
11

22
/* Arm Private Bus 1 */
3-
.apb1 (NOLOAD) : {
4-
. = ORIGIN(APB1) + 0x0000;
5-
_stm32_tim2 = . ;
6-
. = ORIGIN(APB1) + 0x0400;
7-
_stm32_tim3 = . ;
8-
. = ORIGIN(APB1) + 0x0800;
9-
_stm32_tim4 = . ;
10-
. = ORIGIN(APB1) + 0x0C00;
11-
_stm32_tim5 = . ;
12-
. = ORIGIN(APB1) + 0x1000;
13-
_stm32_tim6 = . ;
14-
. = ORIGIN(APB1) + 0x1400;
15-
_stm32_tim7 = . ;
16-
. = ORIGIN(APB1) + 0x1800;
17-
_stm32_tim12 = . ;
18-
. = ORIGIN(APB1) + 0x1C00;
19-
_stm32_tim13 = . ;
20-
. = ORIGIN(APB1) + 0x2000;
21-
_stm32_tim14 = . ;
22-
. = ORIGIN(APB1) + 0x2800;
23-
_stm32_rtc_bkp = . ;
24-
. = ORIGIN(APB1) + 0x2C00;
25-
_stm32_wwdg = . ;
26-
. = ORIGIN(APB1) + 0x3000;
27-
_stm32_iwdg = . ;
28-
. = ORIGIN(APB1) + 0x3400;
29-
_stm32_i2s2_ext = . ;
30-
. = ORIGIN(APB1) + 0x3800;
31-
_stm32_spi2_i2s2 = . ;
32-
. = ORIGIN(APB1) + 0x3C00;
33-
_stm32_spi3_i2s3 = . ;
34-
. = ORIGIN(APB1) + 0x4000;
35-
_stm32_i2s3_ext = . ;
36-
. = ORIGIN(APB1) + 0x4400;
37-
_stm32_usart2 = . ;
38-
. = ORIGIN(APB1) + 0x4800;
39-
_stm32_usart3 = . ;
40-
. = ORIGIN(APB1) + 0x4C00;
41-
_stm32_uart4 = . ;
42-
. = ORIGIN(APB1) + 0x5000;
43-
_stm32_uart5 = . ;
44-
. = ORIGIN(APB1) + 0x5400;
45-
_stm32_i2c1 = . ;
46-
. = ORIGIN(APB1) + 0x5800;
47-
_stm32_i2c2 = . ;
48-
. = ORIGIN(APB1) + 0x5C00;
49-
_stm32_i2c3 = . ;
50-
. = ORIGIN(APB1) + 0x6400;
51-
_stm32_can1 = . ;
52-
. = ORIGIN(APB1) + 0x6800;
53-
_stm32_can2 = . ;
54-
. = ORIGIN(APB1) + 0x7000;
55-
_stm32_pwr = . ;
56-
. = ORIGIN(APB1) + 0x7400;
57-
_stm32_dac = . ;
58-
. = ORIGIN(APB1) + 0x7800;
59-
_stm32_uart7 = . ;
60-
. = ORIGIN(APB1) + 0x7C00;
61-
_stm32_uart8 = . ;
62-
} > APB1
3+
_stm32_tim2 = ORIGIN(APB1) + 0x0000;
4+
_stm32_tim3 = ORIGIN(APB1) + 0x0400;
5+
_stm32_tim4 = ORIGIN(APB1) + 0x0800;
6+
_stm32_tim5 = ORIGIN(APB1) + 0x0C00;
7+
_stm32_tim6 = ORIGIN(APB1) + 0x1000;
8+
_stm32_tim7 = ORIGIN(APB1) + 0x1400;
9+
_stm32_tim12 = ORIGIN(APB1) + 0x1800;
10+
_stm32_tim13 = ORIGIN(APB1) + 0x1C00;
11+
_stm32_tim14 = ORIGIN(APB1) + 0x2000;
12+
_stm32_rtc_bkp = ORIGIN(APB1) + 0x2800;
13+
_stm32_wwdg = ORIGIN(APB1) + 0x2C00;
14+
_stm32_iwdg = ORIGIN(APB1) + 0x3000;
15+
_stm32_i2s2_ext = ORIGIN(APB1) + 0x3400;
16+
_stm32_spi2_i2s2 = ORIGIN(APB1) + 0x3800;
17+
_stm32_spi3_i2s3 = ORIGIN(APB1) + 0x3C00;
18+
_stm32_i2s3_ext = ORIGIN(APB1) + 0x4000;
19+
_stm32_usart2 = ORIGIN(APB1) + 0x4400;
20+
_stm32_usart3 = ORIGIN(APB1) + 0x4800;
21+
_stm32_uart4 = ORIGIN(APB1) + 0x4C00;
22+
_stm32_uart5 = ORIGIN(APB1) + 0x5000;
23+
_stm32_i2c1 = ORIGIN(APB1) + 0x5400;
24+
_stm32_i2c2 = ORIGIN(APB1) + 0x5800;
25+
_stm32_i2c3 = ORIGIN(APB1) + 0x5C00;
26+
_stm32_can1 = ORIGIN(APB1) + 0x6400;
27+
_stm32_can2 = ORIGIN(APB1) + 0x6800;
28+
_stm32_pwr = ORIGIN(APB1) + 0x7000;
29+
_stm32_dac = ORIGIN(APB1) + 0x7400;
30+
_stm32_uart7 = ORIGIN(APB1) + 0x7800;
31+
_stm32_uart8 = ORIGIN(APB1) + 0x7C00;
6332

6433
PROVIDE(_ZN5stm324f4xx6timer2E = _stm32_tim2);
6534
PROVIDE(_ZN5stm324f4xx4spi2E = _stm32_spi2_i2s2);
@@ -75,42 +44,23 @@
7544
PROVIDE(_ZN5stm324f4xx4i2c3E = _stm32_i2c3);
7645

7746
/* Arm Private Bus 2 */
78-
.apb2 (NOLOAD) : {
79-
. = ORIGIN(APB2) + 0x0000;
80-
_stm32_tim1 = . ;
81-
. = ORIGIN(APB2) + 0x0400;
82-
_stm32_tim8 = . ;
83-
. = ORIGIN(APB2) + 0x1000;
84-
_stm32_usart1 = . ;
85-
. = ORIGIN(APB2) + 0x1400;
86-
_stm32_usart6 = . ;
87-
. = ORIGIN(APB2) + 0x2000;
88-
_stm32_adc1 = . ;
89-
. = ORIGIN(APB2) + 0x2C00;
90-
_stm32_sdio = . ;
91-
. = ORIGIN(APB2) + 0x3000;
92-
_stm32_spi1 = . ;
93-
. = ORIGIN(APB2) + 0x3400;
94-
_stm32_spi4 = . ;
95-
. = ORIGIN(APB2) + 0x3800;
96-
_stm32_syscfg = . ;
97-
. = ORIGIN(APB2) + 0x3C00;
98-
_stm32_exti = . ;
99-
. = ORIGIN(APB2) + 0x4000;
100-
_stm32_tim9 = . ;
101-
. = ORIGIN(APB2) + 0x4400;
102-
_stm32_tim10 = . ;
103-
. = ORIGIN(APB2) + 0x4800;
104-
_stm32_tim11 = . ;
105-
. = ORIGIN(APB2) + 0x5000;
106-
_stm32_spi5 = . ;
107-
. = ORIGIN(APB2) + 0x5400;
108-
_stm32_spi6 = . ;
109-
. = ORIGIN(APB2) + 0x5800;
110-
_stm32_sai1 = . ;
111-
. = ORIGIN(APB2) + 0x6800;
112-
_stm32_lcd = . ;
113-
} > APB2
47+
_stm32_tim1 = ORIGIN(APB2) + 0x0000;
48+
_stm32_tim8 = ORIGIN(APB2) + 0x0400;
49+
_stm32_usart1 = ORIGIN(APB2) + 0x1000;
50+
_stm32_usart6 = ORIGIN(APB2) + 0x1400;
51+
_stm32_adc1 = ORIGIN(APB2) + 0x2000;
52+
_stm32_sdio = ORIGIN(APB2) + 0x2C00;
53+
_stm32_spi1 = ORIGIN(APB2) + 0x3000;
54+
_stm32_spi4 = ORIGIN(APB2) + 0x3400;
55+
_stm32_syscfg = ORIGIN(APB2) + 0x3800;
56+
_stm32_exti = ORIGIN(APB2) + 0x3C00;
57+
_stm32_tim9 = ORIGIN(APB2) + 0x4000;
58+
_stm32_tim10 = ORIGIN(APB2) + 0x4400;
59+
_stm32_tim11 = ORIGIN(APB2) + 0x4800;
60+
_stm32_spi5 = ORIGIN(APB2) + 0x5000;
61+
_stm32_spi6 = ORIGIN(APB2) + 0x5400;
62+
_stm32_sai1 = ORIGIN(APB2) + 0x5800;
63+
_stm32_lcd = ORIGIN(APB2) + 0x6800;
11464

11565
PROVIDE(_ZN5stm324f4xx6timer1E = _stm32_tim1);
11666
PROVIDE(_ZN5stm324f4xx4spi1E = _stm32_spi1);
@@ -121,28 +71,21 @@
12171
PROVIDE(_ZN5stm324f4xx6usart6E = _stm32_usart6);
12272

12373
/* Arm High Performance Bus 1 */
124-
.ahb1 (NOLOAD) : {
125-
. = ORIGIN(AHB1) + 0x0000;
126-
_stm32_gpio = . ;
127-
. = ORIGIN(AHB1) + 0x3000;
128-
_stm32_crc = . ;
129-
. = ORIGIN(AHB1) + 0x3800;
130-
_stm32_reset_and_clock_control = . ;
131-
. = ORIGIN(AHB1) + 0x3C00;
132-
_stm32_flash_control = . ;
133-
. = ORIGIN(AHB1) + 0x4000;
74+
_stm32_gpio = ORIGIN(AHB1) + 0x0000;
75+
_stm32_crc = ORIGIN(AHB1) + 0x3000;
76+
_stm32_reset_and_clock_control = ORIGIN(AHB1) + 0x3800;
77+
_stm32_flash_control = ORIGIN(AHB1) + 0x3C00;
78+
79+
.bkpsram ORIGIN(AHB1) + 0x4000 (NOLOAD) : {
13480
_stm32_bkpsram_start = . ;
13581
KEEP(*(.bkpsram))
13682
_stm32_bkpsram_end = . ;
137-
. = ORIGIN(AHB1) + 0x6000;
138-
_stm32_dma1 = . ;
139-
. = ORIGIN(AHB1) + 0x6400;
140-
_stm32_dma2 = . ;
141-
. = ORIGIN(AHB1) + 0x8000;
142-
_stm32_ethernet = . ;
143-
. = ORIGIN(AHB1) + 0xB000;
144-
_stm32_dma2d = . ;
145-
} > AHB1
83+
}
84+
85+
_stm32_dma1 = ORIGIN(AHB1) + 0x6000;
86+
_stm32_dma2 = ORIGIN(AHB1) + 0x6400;
87+
_stm32_ethernet = ORIGIN(AHB1) + 0x8000;
88+
_stm32_dma2d = ORIGIN(AHB1) + 0xB000;
14689

14790
/* Provide as the base for an array of peripherals */
14891
PROVIDE(_ZN5stm324f4xx28general_purpose_input_outputE = _stm32_gpio);
@@ -162,45 +105,25 @@
162105
PROVIDE(_ZN5stm324f4xx143dma2d_controlE = _stm32_dma2d);
163106

164107
/* Arm High Performance Bus 2 */
165-
.ahb2 (NOLOAD) : {
166-
. = ORIGIN(AHB2) + 0x00000;
167-
_stm32_dcmi = . ;
168-
. = ORIGIN(AHB2) + 0x10000;
169-
_stm32_crypto = . ;
170-
. = ORIGIN(AHB2) + 0x10400;
171-
_stm32_hash = . ;
172-
. = ORIGIN(AHB2) + 0x10800;
173-
_stm32_rng = . ;
174-
} > AHB2
108+
_stm32_dcmi = ORIGIN(AHB2) + 0x00000;
109+
_stm32_crypto = ORIGIN(AHB2) + 0x10000;
110+
_stm32_hash = ORIGIN(AHB2) + 0x10400;
111+
_stm32_rng = ORIGIN(AHB2) + 0x10800;
175112

176113
PROVIDE_HIDDEN(_ZN5stm324f4xx23random_number_generatorE = _stm32_rng);
177114

178115
/* USB On-The-Go High Speed */
179-
.usb_otg_hs (NOLOAD) : {
180-
. = ORIGIN(USB_OTG_HS) + 0x0000;
181-
_stm32_usb_otg_hs_device = . ;
182-
} > USB_OTG_HS
183-
116+
_stm32_usb_otg_hs_device = ORIGIN(USB_OTG_HS) + 0x0000;
184117

185118
/* USB On-The-Go Full Speed */
186-
.usb_otg_fs (NOLOAD) : {
187-
. = ORIGIN(USB_OTG_FS) + 0x0000;
188-
_stm32_usb_otg_fs_device = . ;
189-
} > USB_OTG_FS
119+
_stm32_usb_otg_fs_device = ORIGIN(USB_OTG_FS) + 0x0000;
190120

191121
/* Arm High Performance Bus 3 */
192-
.ahb3 (NOLOAD) : {
193-
. = ORIGIN(AHB3) + 0x00000000;
194-
_stm32_fsmc_bank_1 = . ;
195-
. = ORIGIN(AHB3) + 0x10000000;
196-
_stm32_fsmc_bank_2 = . ;
197-
. = ORIGIN(AHB3) + 0x20000000;
198-
_stm32_fsmc_bank_3 = . ;
199-
. = ORIGIN(AHB3) + 0x30000000;
200-
_stm32_fsmc_bank_4 = . ;
201-
. = ORIGIN(AHB3) + 0x40000000;
202-
_stm32_fsmc_control_block = . ;
203-
} > AHB3
122+
_stm32_fsmc_bank_1 = ORIGIN(AHB3) + 0x00000000;
123+
_stm32_fsmc_bank_2 = ORIGIN(AHB3) + 0x10000000;
124+
_stm32_fsmc_bank_3 = ORIGIN(AHB3) + 0x20000000;
125+
_stm32_fsmc_bank_4 = ORIGIN(AHB3) + 0x30000000;
126+
_stm32_fsmc_control_block = ORIGIN(AHB3) + 0x40000000;
204127

205128
/* These are used to zero initialize memory */
206129
__ccm_start = ORIGIN(CCM);
@@ -209,30 +132,18 @@
209132
__sram_limit = ORIGIN(SRAM) + LENGTH(SRAM);
210133

211134
/* Private Peripheral Block for Cortex M */
212-
.ppb (NOLOAD) : {
213-
. = ORIGIN(PPB) + 0x00000;
214-
_cortex_instruction_trace_macrocell = . ;
215-
. = ORIGIN(PPB) + 0x01000;
216-
_cortex_debug_watch_and_trace = . ;
217-
. = ORIGIN(PPB) + 0x0E010;
218-
_cortex_system_tick = . ;
219-
. = ORIGIN(PPB) + 0x0E100;
220-
_cortex_nested_vector_interrupt_controller = . ;
221-
. = ORIGIN(PPB) + 0x0ED00;
222-
_cortex_system_control_block = . ;
223-
. = ORIGIN(PPB) + 0x0ED90;
224-
_cortex_memory_protection_unit = . ;
225-
. = ORIGIN(PPB) + 0x0EDF0;
226-
_cortex_debug_system = . ;
227-
. = ORIGIN(PPB) + 0x0EF00;
228-
_cortex_software_trigger_interrupt = . ;
229-
. = ORIGIN(PPB) + 0x0EF34;
230-
_cortex_floating_point = . ;
231-
. = ORIGIN(PPB) + 0x40000;
232-
_cortex_trace_port_inferface_unit = . ;
233-
. = ORIGIN(PPB) + 0x42000;
234-
_stm32_debug = . ;
235-
} > PPB
135+
_cortex_instruction_trace_macrocell = ORIGIN(PPB) + 0x00000;
136+
_cortex_debug_watch_and_trace = ORIGIN(PPB) + 0x01000;
137+
_cortex_system_tick = ORIGIN(PPB) + 0x0E010;
138+
_cortex_nested_vector_interrupt_controller = ORIGIN(PPB) + 0x0E100;
139+
_cortex_system_control_block = ORIGIN(PPB) + 0x0ED00;
140+
_cortex_memory_protection_unit = ORIGIN(PPB) + 0x0ED90;
141+
_cortex_debug_system = ORIGIN(PPB) + 0x0EDF0;
142+
_cortex_software_trigger_interrupt = ORIGIN(PPB) + 0x0EF00;
143+
_cortex_floating_point = ORIGIN(PPB) + 0x0EF34;
144+
_cortex_trace_port_inferface_unit = ORIGIN(PPB) + 0x40000;
145+
_stm32_debug = ORIGIN(PPB) + 0x42000;
146+
236147
/* Provide the C++ mangled names */
237148
PROVIDE(_ZN6cortex11peripherals27instruction_trace_macrocellE = _cortex_instruction_trace_macrocell);
238149
PROVIDE(_ZN6cortex11peripherals20data_watch_and_traceE = _cortex_debug_watch_and_trace);

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