STM32H753 Clock tree running at 400Mhz

What's Wrong:

* CLock tree was incorrect in order and some values in BoardContext.cpp were incorrect.

How Was it Fixed (if not obvious):

* Human asking AI questions about hardware
* Claude and Copolit getting hardware wrong
* Human correcting AI from datasheet
* AI and Human find the answer.

What side effects does this have (could be none):

* H7 boards boot but may be unstable when debugging gets such a huge change

Which builds did you run to make sure they build?

[ ] arm-none-eabi-gcc Cortex M4
[X] arm-none-eabi-gcc Cortex M7
[ ] (Apple) Native Clang
[ ] (Apple) Homebrew GCC
[ ] (Apple) Homebrew LLVM

How Do We Know and Can Show It's Fixed:

* Boots to main()

Which Unittest Series did you Check?

[ ] (Apple) Native Clang
[ ] (Apple) Homebrew GCC
[ ] (Apple) Homebrew LLVM

Did this affect any on-target builds? If so which were tested?

[ ] STM32F407VE board
[X] STM32H753ZI board

Author: emrainey

boards/netduinoplus2/scripts/template.jdebug

@@ -2,7 +2,6 @@ void OnProjectLoad(void) {
     //
     // Dialog-generated settings
     //
-    Project.ConfigSemihosting("ModeBKPT=2");
     Debug.SetResetMode(RM_RESET_HALT);
     Project.SetTraceSource("SWO");
     Project.SetDevice("STM32F405RG");

boards/nucleo_h753zi/scripts/template.jdebug

@@ -2,7 +2,6 @@ void OnProjectLoad(void) {
     //
     // Dialog-generated settings
     //
-    Project.ConfigSemihosting("ModeBKPT=2");
     Debug.SetResetMode(RM_RESET_HALT);
     Project.SetTraceSource("SWO");
     Project.SetDevice("STM32H753ZI");

boards/nucleo_h753zi/source/BoardContext.cpp

@@ -7,6 +7,7 @@
 #include "lps35hw.hpp"
 #include "lsm9ds1.hpp"
 #include "segger/rtt.hpp"
+#include "stm32/h7xx/ResetAndClockControl.hpp"
 #include "strings.hpp"
 
 namespace stm32 {
@@ -27,10 +28,10 @@ ClockConfiguration const default_clock_configuration = {
     /* .low_speed_external_oscillator_frequency = */ low_speed_external_oscillator_frequency,
     /* .voltage_scaling = */ 0b11,             // VOS1 (up to 400 MHz without VOS0 boost)
     /* .d1_core_prescaler = */ 0b0000,         // /1 (cpu_ck = sys_ck)
-    /* .ahb_divider = */ 0b0000,               // /1 (hclk = sys_ck)
+    /* .ahb_divider = */ 0b1000,               // /2 (hclk3 = sys_ck/2)
     /* .apb1_low_speed_divider = */ 0b101,     // /4
     /* .apb2_high_speed_divider = */ 0b100,    // /2
-    /* .apb3_divider = */ 0b100,               // /2
+    /* .apb3_divider = */ 0b100,               // /2 (apb3 = hclk3/2)
     /* .apb4_divider = */ 0b100,               // /2
     /* .mcu_clock1_divider = */ 0b111,         // /5
     /* .mcu_clock2_divider = */ 0b111,         // /5
@@ -206,23 +207,33 @@ core::Status BoardContext::Initialize(void) {
         .SetOutputType(stm32::gpio::OutputType::PushPull);
 
     stm32::h7xx::ResetAndClockControl::AHB1PeripheralClockEnable ahb1_enable;
+    stm32::h7xx::ResetAndClockControl::AHB1PeripheralReset ahb1_reset;
     stm32::h7xx::ResetAndClockControl::AHB2PeripheralClockEnable ahb2_enable;
+    stm32::h7xx::ResetAndClockControl::AHB2PeripheralReset ahb2_reset;
     stm32::h7xx::ResetAndClockControl::APB1LowClockEnable apb1_enable;
     stm32::h7xx::ResetAndClockControl::APB2PeripheralClockEnable apb2_enable;
 
+    // Reset the AHB1 peripherals
+    ahb1_reset = stm32::h7xx::reset_and_clock_control.ahb1_peripheral_reset;    // read
+    ahb1_reset.bits.dma1_reset = 1U;
+    ahb1_reset.bits.dma2_reset = 1U;
+    stm32::h7xx::reset_and_clock_control.ahb1_peripheral_reset = ahb1_reset;    // write
+    ahb1_reset.bits.dma1_reset = 0U;
+    ahb1_reset.bits.dma2_reset = 0U;
+    stm32::h7xx::reset_and_clock_control.ahb1_peripheral_reset = ahb1_reset;    // write
+
+    // Reset the AHB2 peripherals
+    ahb2_reset = stm32::h7xx::reset_and_clock_control.ahb2_peripheral_reset;    // read
+    ahb2_reset.bits.random_number_generator_reset = 1U;
+    stm32::h7xx::reset_and_clock_control.ahb2_peripheral_reset = ahb2_reset;    // write
+    ahb2_reset.bits.random_number_generator_reset = 0U;
+    stm32::h7xx::reset_and_clock_control.ahb2_peripheral_reset = ahb2_reset;    // write
+
     // Enable the RNG in the AHB2 Periperhals
     ahb2_enable = stm32::h7xx::reset_and_clock_control.ahb2_peripheral_clock_enable;    // read
     ahb2_enable.bits.random_number_generator_enable = 1U;
     stm32::h7xx::reset_and_clock_control.ahb2_peripheral_clock_enable = ahb2_enable;    // write
 
-    // Reset the RNG
-    stm32::h7xx::ResetAndClockControl::AHB2PeripheralReset reset;
-    reset = stm32::h7xx::reset_and_clock_control.ahb2_peripheral_reset;    // read
-    reset.bits.random_number_generator_reset = 1U;
-    stm32::h7xx::reset_and_clock_control.ahb2_peripheral_reset = reset;    // write
-    reset.bits.random_number_generator_reset = 0U;
-    stm32::h7xx::reset_and_clock_control.ahb2_peripheral_reset = reset;    // write
-
     // enable the APB1 peripherals in the Reset and Clock Control register
     apb1_enable = stm32::h7xx::reset_and_clock_control.apb1_low_clock_enable;    // read
     apb1_enable.bits.timer2_enable = 1U;                                         // modify
@@ -242,22 +253,16 @@ core::Status BoardContext::Initialize(void) {
     apb2_enable.bits.spi1_enable = 1;                                                   // modify
     stm32::h7xx::reset_and_clock_control.apb2_peripheral_clock_enable = apb2_enable;    // write
 
-    jarnax::print(
-        "Feature Clock is %" PRIu32
-        "\r\n"
-        "APB1 Timer Clock is %" PRIu32
-        "\r\n"
-        "APB2 Timer Clock is %" PRIu32
-        "\r\n"
-        "APB1 Clock is %" PRIu32
-        "\r\n"
-        "APB2 Clock is %" PRIu32 "\r\n",
-        stm32::GetClockTree().fclk.value(),
-        stm32::GetClockTree().apb1_timer_clk.value(),
-        stm32::GetClockTree().apb2_timer_clk.value(),
-        stm32::GetClockTree().apb1_peripheral.value(),
-        stm32::GetClockTree().apb2_peripheral.value()
-    );
+    jarnax::print("Feature Clock is %" PRIu32 "\r\n", stm32::GetClockTree().fclk.value());
+    jarnax::print("APB1 Timer Clock is %" PRIu32 "\r\n", stm32::GetClockTree().apb1_timer_clk.value());
+    jarnax::print("APB2 Timer Clock is %" PRIu32 "\r\n", stm32::GetClockTree().apb2_timer_clk.value());
+    jarnax::print("APB1 Clock is %" PRIu32 "\r\n", stm32::GetClockTree().apb1_peripheral.value());
+    jarnax::print("APB2 Clock is %" PRIu32 "\r\n", stm32::GetClockTree().apb2_peripheral.value());
+    jarnax::print("APB3 Clock is %" PRIu32 "\r\n", stm32::GetClockTree().apb3_peripheral.value());
+    jarnax::print("APB4 Clock is %" PRIu32 "\r\n", stm32::GetClockTree().apb4_peripheral.value());
+    jarnax::print("AHB1 Clock is %" PRIu32 "\r\n", stm32::GetClockTree().ahb1_peripheral.value());
+    jarnax::print("AHB2 Clock is %" PRIu32 "\r\n", stm32::GetClockTree().ahb2_peripheral.value());
+
     do {
         // RNG
         status = random_number_generator_.Initialize();
@@ -281,7 +286,7 @@ core::Status BoardContext::Initialize(void) {
         // I2C2
         status = i2c2_driver_.Initialize(stm32::GetClockTree().apb1_peripheral, ::stm32::i2c2_bus_frequency);
         if (not status.IsSuccess()) {
-            jarnax::print("I2C1 failed to initialize\r\n");
+            jarnax::print("I2C2 failed to initialize\r\n");
             break;
         }
 

boards/stm32_f4ve_v2/scripts/template.jdebug

@@ -2,7 +2,6 @@ void OnProjectLoad(void) {
     //
     // Dialog-generated settings
     //
-    Project.ConfigSemihosting("ModeBKPT=2");
     Debug.SetResetMode(RM_RESET_HALT);
     Project.SetTraceSource("SWO");
     Project.SetDevice("STM32F407VE");

documentation/pdfs/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf

@@ -24,6 +24,9 @@ void ATTRIBUTE((used)) configure(void) {
 
     jarnax::print("Vector Table @ %p\r\n", static_cast<void const *>(&cortex::vector_table));
     if constexpr (cortex::initialize_system_clocks) {
+        // @FIXME this should work since the clock tree works, but doesn't link.
+        // jarnax::print("Initializing Early Power\r\n");
+        // vendor::initialize::early_power();
         jarnax::print("Initializing System Clocks\r\n");
         // each vendors clock tree is a unique and confusing flower, let them deal with it!
         vendor::initialize::clocks();

modules/jarnax/source/configure.cpp

@@ -1,6 +1,7 @@
 add_module(NAME stm32
     SOURCES
         ${CMAKE_CURRENT_SOURCE_DIR}/source/stm32f4xx/vectors.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/source/stm32f4xx/power.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/source/stm32f4xx/clocks.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/source/gpio/Pin.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/source/Conversions.cpp
@@ -30,6 +31,7 @@ add_module(NAME stm32
 add_module(NAME stm32
     SOURCES
         ${CMAKE_CURRENT_SOURCE_DIR}/source/stm32h7xx/vectors.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/source/stm32h7xx/power.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/source/stm32h7xx/clocks.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/source/gpio/Pin.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/source/Conversions.cpp

modules/stm32/CMakeLists.txt

@@ -10,6 +10,9 @@ namespace stm32 {
 /// Used to initialize chip specific drivers which need to be brought up very early.
 namespace initialize {
 
+/// @brief Initializes any Power needed to start the clock tree (e.g. enabling the voltage regulator)
+void early_power(void);
+
 /// @brief The required Clock initialization for all STM32 chips
 void clocks(void);
 

modules/stm32/include/stm32/Initialize.hpp

@@ -307,6 +307,13 @@ struct ResetAndClockControl final {
     static_assert(sizeof(ClockRecoveryCalibrationControl) == 4UL, "Must be this exact size");
     /// RCC Clock Configuration Register (CFGR)
     struct Configuration final {
+        /// System clock switch (SW)
+        enum class SystemClockSwitch : uint32_t {
+            HighSpeedInternalClock = 0b00,            ///<  (HSI_CLOCK)
+            CalibratedSiliconInternalClock = 0b01,    ///<  (CSI_CLOCK)
+            HighSpeedExternalClock = 0b10,            ///<  (HSE_CLOCK)
+            PhaseLockLoopClock = 0b11,                ///<  (PLL_CLOCK)
+        };
         /// Default Constructor
         Configuration()
             : whole{0u} {}
@@ -330,29 +337,29 @@ struct ResetAndClockControl final {
         /// The internal bitfield for the register
         struct Fields final {
             /// System clock switch (SW)
-            uint32_t system_clock_switch          : 3;    // bits 0:2
+            SystemClockSwitch system_clock_switch        : 3;    // bits 0:2
             /// System clock switch status (SWS)
-            uint32_t system_clock_switch_status   : 3;    // bits 3:5
+            SystemClockSwitch system_clock_switch_status : 3;    // bits 3:5
             /// System clock selection after a wake up from system Stop (STOPWUCK)
-            uint32_t stop_wakeup_clock            : 1;    // bit 6
+            uint32_t stop_wakeup_clock                   : 1;    // bit 6
             /// Kernel clock selection after a wake up from system Stop (STOPKERWUCK)
-            uint32_t stop_kernel_wakeup_clock     : 1;    // bit 7
+            uint32_t stop_kernel_wakeup_clock            : 1;    // bit 7
             /// HSE division factor for RTC clock (RTCPRE)
-            uint32_t real_time_clock_prescaler    : 6;    // bits 8:13
+            uint32_t real_time_clock_prescaler           : 6;    // bits 8:13
             /// High Resolution Timer clock prescaler selection (HRTIMSEL)
-            uint32_t high_resolution_timer_select : 1;    // bit 14
+            uint32_t high_resolution_timer_select        : 1;    // bit 14
             /// Timers clocks prescaler selection (TIMPRE)
-            uint32_t timers_clock_prescaler       : 1;    // bit 15
+            uint32_t timers_clock_prescaler              : 1;    // bit 15
             /// (reserved)
-            uint32_t                              : 2;    // bits 16:17
+            uint32_t                                     : 2;    // bits 16:17
             /// MCO1 prescaler (MCO1PRE)
-            uint32_t mco1_prescaler               : 4;    // bits 18:21
+            uint32_t mco1_prescaler                      : 4;    // bits 18:21
             /// Micro-controller clock output 1 (MCO1SEL)
-            uint32_t mco1_selection               : 3;    // bits 22:24
+            uint32_t mco1_selection                      : 3;    // bits 22:24
             /// MCO2 prescaler (MCO2PRE)
-            uint32_t mco2_prescaler               : 4;    // bits 25:28
+            uint32_t mco2_prescaler                      : 4;    // bits 25:28
             /// Micro-controller clock output 2 (MCO2SEL)
-            uint32_t mco2_selection               : 3;    // bits 29:31
+            uint32_t mco2_selection                      : 3;    // bits 29:31
         };
         //+=MEMORY======================================+
         union {
@@ -5970,11 +5977,11 @@ struct ResetAndClockControl final {
 
     //+=MEMORY======================================+
     /// clock control register (CR)
-    Control control;                                                    // offset 0x0UL
+    Control control;                                                       // offset 0x0UL
 #if defined(STM32H7_REV_Y)
-    InternalClockSourcesCalibration internalclocksourcescalibration;    // offset 0x4UL
+    InternalClockSourcesCalibration internal_clock_sources_calibration;    // offset 0x4UL
 #elif defined(STM32H7_REV_V)
-    HighSpeedInternalConfiguration highspeedinternalconfiguration;    // offset 0x4UL
+    HighSpeedInternalConfiguration high_speed_internal_configuration;    // offset 0x4UL
 #endif
     /// RCC Clock Recovery RC Register (CRRCR)
     ClockRecoveryCalibrationControl clock_recovery_calibration_control;    // offset 0x8UL
@@ -6016,12 +6023,12 @@ struct ResetAndClockControl final {
     Domain3PeripheralClockSelection domain3_peripheral_clock_selection;    // offset 0x58UL
     uint32_t : 32;                                                         // offset 0x5cUL
     /// RCC Clock Source Interrupt Enable Register (CIER)
-    ClockInterruptEnable clockinterruptenable;    // offset 0x60UL
+    ClockInterruptEnable clock_interrupt_enable;    // offset 0x60UL
     /// RCC Clock Source Interrupt Flag Register (CIFR)
-    ClockInterruptFlags clockinterruptflags;    // offset 0x64UL
+    ClockInterruptFlags clock_interrupt_flags;    // offset 0x64UL
     /// RCC Clock Source Interrupt Clear Register (CICR)
-    ClockInterruptClear clockinterruptclear;    // offset 0x68UL
-    uint32_t : 32;                              // offset 0x6cUL
+    ClockInterruptClear clock_interrupt_clear;    // offset 0x68UL
+    uint32_t : 32;                                // offset 0x6cUL
     /// RCC Backup Domain Control Register (BDCR)
     BackupDomainControl backup_domain_control;    // offset 0x70UL
     /// RCC Clock Control and Status Register (CSR)
@@ -6324,9 +6331,9 @@ static_assert(offsetof(ResetAndClockControl, domain1_peripheral_clock_selection)
 static_assert(offsetof(ResetAndClockControl, domain2_peripheral_clock_selection1) == 0x50UL, "Must be located at this offset");
 static_assert(offsetof(ResetAndClockControl, domain2_peripheral_clock_selection2) == 0x54UL, "Must be located at this offset");
 static_assert(offsetof(ResetAndClockControl, domain3_peripheral_clock_selection) == 0x58UL, "Must be located at this offset");
-static_assert(offsetof(ResetAndClockControl, clockinterruptenable) == 0x60UL, "Must be located at this offset");
-static_assert(offsetof(ResetAndClockControl, clockinterruptflags) == 0x64UL, "Must be located at this offset");
-static_assert(offsetof(ResetAndClockControl, clockinterruptclear) == 0x68UL, "Must be located at this offset");
+static_assert(offsetof(ResetAndClockControl, clock_interrupt_enable) == 0x60UL, "Must be located at this offset");
+static_assert(offsetof(ResetAndClockControl, clock_interrupt_flags) == 0x64UL, "Must be located at this offset");
+static_assert(offsetof(ResetAndClockControl, clock_interrupt_clear) == 0x68UL, "Must be located at this offset");
 static_assert(offsetof(ResetAndClockControl, backup_domain_control) == 0x70UL, "Must be located at this offset");
 static_assert(offsetof(ResetAndClockControl, clock_control_status) == 0x74UL, "Must be located at this offset");
 static_assert(offsetof(ResetAndClockControl, ahb3_peripheral_reset) == 0x7cUL, "Must be located at this offset");

modules/stm32/include/stm32/h7xx/ResetAndClockControl.hpp

@@ -31,6 +31,9 @@ constexpr Hertz high_speed_internal_oscillator_frequency = 64_MHz;
 /// @brief The speed of the HSE oscillator on most STM32 parts
 constexpr Hertz low_speed_internal_oscillator_frequency = 32_KHz;
 
+/// @brief The speed of the CSI oscillator on STM32H7 parts
+constexpr Hertz calibrated_silicon_internal_oscillator_frequency = 4_MHz;
+
 /// The clock speed of the STM32H7xxxx
 constexpr Hertz top_clock_frequency = 480_MHz;
 
@@ -328,23 +331,31 @@ struct ClockTree {
     Hertz low_speed_external;
     Hertz high_speed_internal;
     Hertz high_speed_external;
-    Hertz pll_input;          ///< The frequency of the input to the PLL
-    Hertz pll_vco;            ///< The frequency of the VCO
-    Hertz pll_output;         ///< The frequency of the PLL output
-    Hertz sysclk;             ///< the clock before the AHB/APB divider
-    Hertz eth_ptp;            ///< The frequency of the Ethernet PTP clock
-    Hertz fclk;               ///< The frequency of the cortex free running clock
-    Hertz hclk;               ///< The frequency of the AHB bus, DMA and Core Memory (HCLK)
-    Hertz system_timer;       ///< The frequency of the Cortex SYSTICK
-    Hertz apb1_peripheral;    ///< The frequency of the APB1 bus (low speed)
-    Hertz apb2_peripheral;    ///< The frequency of the APB2 bus (high speed)
+    Hertz pll_input;                    ///< The frequency of the input to the PLL
+    Hertz pll_vco;                      ///< The frequency of the VCO
+    Hertz pll_output;                   ///< The frequency of the PLL output
+    Hertz sysclk;                       ///< the clock before the D1CPRE dividers
+    Hertz fclk;                         ///< The frequency of the cortex free running clock
+    Hertz hclk;                         ///< The frequency of the AHB bus (HCLK in D1, HCLK1 in D2, HCLK3 in D3, and HCLK in D1)
+    Hertz system_timer;                 ///< The frequency of the Cortex SYSTICK is the CPU clock divided by 8 (HCLK/8)
+    Hertz apb1_peripheral;              ///< The frequency of the APB1 bus (low speed in D2)
+    Hertz apb2_peripheral;              ///< The frequency of the APB2 bus (high speed in D2)
+    Hertz apb3_peripheral;              ///< The frequency of the APB3 bus (in D1)
+    Hertz apb4_peripheral;              ///< The frequency of the APB4 bus (in D3)
+    Hertz ahb1_peripheral;              ///< The frequency of the AHB1 peripheral clock (HCLK1 in D2)
+    Hertz ahb2_peripheral;              ///< The frequency of the AHB2 peripheral clock (HCLK2 == HCLK1 in D2)
+    Hertz ahb3_peripheral;              ///< The frequency of the HCLK3 peripheral clock (HCLK3 in D1)
+    Hertz ahb4_peripheral;              ///< The frequency of the HCLK4 peripheral clock (HCLK4 in D3)
+    Hertz apb1_timer_clk;               ///< The frequency of the TIMx clocks  (TIMxCLK)
+    Hertz apb2_timer_clk;               ///< The frequency of the TIMx clocks  (TIMxCLK)
+    Hertz high_resolution_timer_clk;    ///< The frequency of the HRTIMx clocks (HRTIMxCLK)
+    // Specific Peripheral Clocks
+    Hertz eth_ptp;    ///< The frequency of the Ethernet PTP clock
     Hertz pll_i2s;
     Hertz pll_48ck;
     Hertz rtc;
     Hertz rng;
     Hertz usbotg;
-    Hertz apb1_timer_clk;    ///< The frequency of the TIMx clocks  (TIMxCLK)
-    Hertz apb2_timer_clk;    ///< The frequency of the TIMx clocks  (TIMxCLK)
 };
 
 /// @brief The STM32H7xxx clock configuration.