Effective Split of Peripheral Drivers

What's Wrong:

* The peripheral definitions of the f4xx and h7xx are different.
* Old templates had dated information.

How Was it Fixed (if not obvious):

* Made duplicates of all common peripheral headers from peripheralyzer.
* Checked in the naming maps and altered SVDs
* Updated template types to have updated information for openocd debug.

What side effects does this have (could be none):

* Include structure is a bit more complicated. This can be simplified in the future.

Which builds did you run to make sure they build?

[X] arm-none-eabi-gcc Cortex M4
[X] arm-none-eabi-gcc Cortex M7
[ ] (Apple) Native Clang
[ ] (Apple) Homebrew GCC
[X] (Apple) Homebrew LLVM

How Do We Know and Can Show It's Fixed:

* Builds.

Which Unittest Series did you Check?

[ ] (Apple) Native Clang
[ ] (Apple) Homebrew GCC
[X] (Apple) Homebrew LLVM

Did this affect any on-target builds? If so which were tested?

[X] STM32F407VE board
[ ] STM32H753ZI board

Author: emrainey

.gitignore

@@ -34,6 +34,10 @@
 # Ignore Build Output
 build/
 
+# Ingnore Testing Output like Jlink/Ozone or GDB configuration
+testing/*.jdebug*
+testing/*.gdb
+
 # Ignore Python virtual environments
 venv/
 .venv/

CMakeLists.txt

@@ -43,40 +43,45 @@ add_configuration(NAME full)
 add_configuration(NAME basic)
 add_configuration(NAME qemu)
 
-add_family(FAMILY stm32f40xxx
+add_family(FAMILY stm32f4xx
     VENDOR stm32
     DESCRIPTION "ST STM32F4xx family"
     MODULES stm32
     CORTEX_M 4
     ARCHITECTURE armv7e-m
     PRECISION SINGLE
+    NAMESPACE f4xx
 )
 
 add_chip(NAME stm32f407ve
-    FAMILY stm32f40xxx
+    FAMILY stm32f4xx
     DEVICE STM32F407VE
     PACKAGE LQFP100
+    DEFINES CORTEX_INTERRUPT_CHANNELS=82
 )
 
 add_chip(NAME stm32f405rg
-    FAMILY stm32f40xxx
+    FAMILY stm32f4xx
     DEVICE STM32F405RG
     PACKAGE LQFP64
+    DEFINES CORTEX_INTERRUPT_CHANNELS=82
 )
 
-add_family(FAMILY stm32h7xxxx
+add_family(FAMILY stm32h7xx
     VENDOR stm32
     DESCRIPTION "ST STM32H7xx family"
     MODULES stm32
     CORTEX_M 7
     ARCHITECTURE armv7e-m
     PRECISION DOUBLE
+    NAMESPACE h7xx
 )
 
 add_chip(NAME stm32h753zi
-    FAMILY stm32h7xxxx
+    FAMILY stm32h7xx
     DEVICE STM32H753ZI
     PACKAGE LQFP144
+    DEFINES CORTEX_INTERRUPT_CHANNELS=150
 )
 
 # After we define all the chips, families and configurations,

README.md

@@ -228,6 +228,24 @@ target remote localhost:1234
 
 The superloop on-target unit test now builds against a configuration for qemu which disables some things (ClockTree) which aren't implemented and cause hangs.
 
+### Debugging with OpenOCD
+
+OpenOCD is an open source tool which can be used to debug on-target using a variety of hardware debuggers. It is a bit more complex to set up than the Segger JLink tools but it is free and open source.
+
+```bash
+# In a separate terminal, start the OpenOCD server with the appropriate configuration for your board and debugger (observe the port here is 2331, not 3333 which is the default for OpenOCD)
+openocd --file modules/stm32/scripts/stm32h753zi.cfg
+
+# then in another terminal, start the GDB client and connect to the OpenOCD server
+cgdb -d `which arm-none-eabi-gdb` -x testing/firmware-nucleo-demo-basic-nucleo_h753zi.gdb
+(gdb) target remote localhost:2331
+
+# Or just normal GDB
+arm-none-eabi-gdb -x testing/firmware-nucleo-demo-basic-nucleo_h753zi.gdb
+```
+
+Once you are inside, run `setup` and then `reset` to start the program. You should see the output in the OpenOCD terminal.
+
 ## Modules
 
 Components are separated into modules which are independent and require build support to interwork. This is done to prevent accidental inclusion in single `include/` folder systems for all components. After a dependency is formed in the build system, the appropriate include paths, defines, sources, etc. will be provided.
@@ -329,11 +347,11 @@ extern Timer2 volatile timer2;
 }    // namespace stm32
 ```
 
-Thus only the memory map in the linker needs to know it's real address. If it needs to be known in code, we simply refer to it naturally as `&stm32::peripherals::timer2`. This works seemlessly in unit test and on-target, where we simply define a structure out in a global location for each peripheral.
+Thus only the memory map in the linker needs to know it's real address. If it needs to be known in code, we simply refer to it naturally as `&stm32::f4xx::timer2`. This works seemlessly in unit test and on-target, where we simply define a structure out in a global location for each peripheral.
 
 ```c++
 // in peripherals.cpp for the board, used by unit tests
-stm32::peripherals::Timer2 volatile timer2;
+stm32::f4xx::Timer2 volatile timer2;
 ```
 
 These should be moved to the chip specific vendor area for per-mcu builds.

boards/netduinoplus2/linkerscripts/board-zero-table.ld

@@ -1 +1 @@
-INCLUDE stm32f40xxx-zero-table.ld
+INCLUDE stm32f4xx-zero-table.ld

boards/netduinoplus2/scripts/client.gdb.in

@@ -0,0 +1,25 @@
+# define hookpost-connect
+#     monitor swo EnableTarget 0 0 0xFFFFFFFF 0
+#     monitor swo start 480000000 64000
+# end
+
+define reset
+    target remote localhost:2331
+    # Reset configuration
+    monitor reset halt
+    monitor flash probe 0
+    load @LOCAL_TARGET_BINARY_PATH@
+end
+
+define setup
+    file @LOCAL_TARGET_BINARY_PATH@
+    break cortex::initialize::on_startup
+    break vendor::initialize::clocks
+    break cortex::system::main
+    layout split
+    set print asm-demangle on
+    set print frame-arguments all
+    # Users may have their own breakpoints, so we want to load those after the reset sequence
+    source -s -v testing/breakpoints.gdb
+end
+

boards/netduinoplus2/scripts/template.gdb

@@ -35,8 +35,8 @@ ClockConfiguration const default_clock_configuration = {
 namespace jarnax {
 
 BoardContext::BoardContext()
-    : timer_{stm32::peripherals::timer2}
-    , random_number_generator_{}
+    : timer_{stm32::f4xx::timer2}
+    , random_number_generator_{stm32::f4xx::random_number_generator}
     , wakeup_pin_{stm32::gpio::Port::A, 0}
     , mco1_pin_{stm32::gpio::Port::A, 8}
     , mco2_pin_{stm32::gpio::Port::C, 9}
@@ -61,12 +61,12 @@ BoardContext::BoardContext()
     , spi2_miso_{stm32::gpio::Port::B, 14}
     , spi2_sclk_{stm32::gpio::Port::B, 13}
     , spi2_nss_{stm32::gpio::Port::B, 12}
-    , dma_manager_{stm32::peripherals::direct_memory_access}
-    , spi1_driver_{stm32::peripherals::spi1, dma_manager_, stm32::SPI1_RX, stm32::SPI1_TX}
-    , spi2_driver_{stm32::peripherals::spi2, dma_manager_, stm32::SPI2_RX, stm32::SPI2_TX}
+    , dma_manager_{stm32::f4xx::direct_memory_access}
+    , spi1_driver_{stm32::f4xx::spi1, dma_manager_, stm32::SPI1_RX, stm32::SPI1_TX}
+    , spi2_driver_{stm32::f4xx::spi2, dma_manager_, stm32::SPI2_RX, stm32::SPI2_TX}
     , usart1_tx_{stm32::gpio::Port::A, 9}
     , usart1_rx_{stm32::gpio::Port::A, 10}
-    , usart1_driver_{stm32::peripherals::usart1, dma_manager_, stm32::USART1_RX, stm32::USART1_TX, GetDmaAllocator(), stm32::usart_dma_buffer_size}
+    , usart1_driver_{stm32::f4xx::usart1, dma_manager_, stm32::USART1_RX, stm32::USART1_TX, GetDmaAllocator(), stm32::usart_dma_buffer_size}
     , usart_console_{usart1_driver_} {
     // construct the driver objects as part of the constructor above.
 }
@@ -144,41 +144,41 @@ core::Status BoardContext::Initialize(void) {
         .SetOutputSpeed(stm32::gpio::Speed::High)
         .SetOutputType(stm32::gpio::OutputType::PushPull);
 
-    stm32::peripherals::ResetAndClockControl::AHB1PeripheralClockEnable ahb1_enable;
-    stm32::peripherals::ResetAndClockControl::AHB2PeripheralClockEnable ahb2_enable;
-    stm32::peripherals::ResetAndClockControl::APB1PeripheralClockEnable apb1_enable;
-    stm32::peripherals::ResetAndClockControl::APB2PeripheralClockEnable apb2_enable;
+    stm32::f4xx::ResetAndClockControl::AHB1PeripheralClockEnable ahb1_enable;
+    stm32::f4xx::ResetAndClockControl::AHB2PeripheralClockEnable ahb2_enable;
+    stm32::f4xx::ResetAndClockControl::APB1PeripheralClockEnable apb1_enable;
+    stm32::f4xx::ResetAndClockControl::APB2PeripheralClockEnable apb2_enable;
 
     // Enable the RNG in the AHB2 Periperhals
-    ahb2_enable = stm32::peripherals::reset_and_clock_control.ahb2_peripheral_clock_enable;    // read
+    ahb2_enable = stm32::f4xx::reset_and_clock_control.ahb2_peripheral_clock_enable;    // read
     ahb2_enable.bits.random_number_generator_enable = 1U;
-    stm32::peripherals::reset_and_clock_control.ahb2_peripheral_clock_enable = ahb2_enable;    // write
+    stm32::f4xx::reset_and_clock_control.ahb2_peripheral_clock_enable = ahb2_enable;    // write
 
     // Reset the RNG
-    stm32::peripherals::ResetAndClockControl::AHB2PeripheralReset reset;
-    reset = stm32::peripherals::reset_and_clock_control.ahb2_peripheral_reset;    // read
+    stm32::f4xx::ResetAndClockControl::AHB2PeripheralReset reset;
+    reset = stm32::f4xx::reset_and_clock_control.ahb2_peripheral_reset;    // read
     reset.bits.random_number_generator_reset = 1U;
-    stm32::peripherals::reset_and_clock_control.ahb2_peripheral_reset = reset;    // write
+    stm32::f4xx::reset_and_clock_control.ahb2_peripheral_reset = reset;    // write
     reset.bits.random_number_generator_reset = 0U;
-    stm32::peripherals::reset_and_clock_control.ahb2_peripheral_reset = reset;    // write
+    stm32::f4xx::reset_and_clock_control.ahb2_peripheral_reset = reset;    // write
 
     // enable the APB1 peripherals in the Reset and Clock Control register
-    apb1_enable = stm32::peripherals::reset_and_clock_control.apb1_peripheral_clock_enable;    // read
-    apb1_enable.bits.tim2en = 1U;                                                              // modify
-    apb1_enable.bits.spi2en = 1U;                                                              // modify
-    stm32::peripherals::reset_and_clock_control.apb1_peripheral_clock_enable = apb1_enable;    // write
+    apb1_enable = stm32::f4xx::reset_and_clock_control.apb1_peripheral_clock_enable;    // read
+    apb1_enable.bits.tim2en = 1U;                                                       // modify
+    apb1_enable.bits.spi2en = 1U;                                                       // modify
+    stm32::f4xx::reset_and_clock_control.apb1_peripheral_clock_enable = apb1_enable;    // write
 
     // enable the AHB1 peripherals in the Reset and Clock Control register
-    ahb1_enable = stm32::peripherals::reset_and_clock_control.ahb1_peripheral_clock_enable;    // read
-    ahb1_enable.bits.dma1en = 1;                                                               // modify
-    ahb1_enable.bits.dma2en = 1;                                                               // modify
-    stm32::peripherals::reset_and_clock_control.ahb1_peripheral_clock_enable = ahb1_enable;    // write
+    ahb1_enable = stm32::f4xx::reset_and_clock_control.ahb1_peripheral_clock_enable;    // read
+    ahb1_enable.bits.dma1en = 1;                                                        // modify
+    ahb1_enable.bits.dma2en = 1;                                                        // modify
+    stm32::f4xx::reset_and_clock_control.ahb1_peripheral_clock_enable = ahb1_enable;    // write
 
     // enable the ABP2 peripherals in the Reset and Clock Control register
-    apb2_enable = stm32::peripherals::reset_and_clock_control.apb2_peripheral_clock_enable;    // read
-    apb2_enable.bits.spi1en = 1;                                                               // modify
-    apb2_enable.bits.usart1en = 1;                                                             // modify
-    stm32::peripherals::reset_and_clock_control.apb2_peripheral_clock_enable = apb2_enable;    // write
+    apb2_enable = stm32::f4xx::reset_and_clock_control.apb2_peripheral_clock_enable;    // read
+    apb2_enable.bits.spi1en = 1;                                                        // modify
+    apb2_enable.bits.usart1en = 1;                                                      // modify
+    stm32::f4xx::reset_and_clock_control.apb2_peripheral_clock_enable = apb2_enable;    // write
 
     jarnax::print(
         "Feature Clock is%" PRIu32

…ds/netduinoplus2/scripts/Ozone.jdebug.in …ds/netduinoplus2/scripts/template.jdebugboards/netduinoplus2/scripts/Ozone.jdebug.in renamed to boards/netduinoplus2/scripts/template.jdebug boards/netduinoplus2/scripts/Ozone.jdebug.in renamed to boards/netduinoplus2/scripts/template.jdebug

@@ -1 +1 @@
-INCLUDE stm32h7xxxx-zero-table.ld
+INCLUDE stm32h7xx-zero-table.ld