Merge iQ-L range catalog support

Author: fa-yoshinobu

README.md

@@ -78,7 +78,7 @@ For normal application code:
 | --- | --- | --- | --- | --- | --- |
 | `iq-f` | `3e` | `ql` | octal | `iq-f` | live-validated |
 | `iq-r` | `4e` | `iqr` | hexadecimal | `iq-r` | live-validated |
-| `iq-l` | `4e` | `iqr` | hexadecimal | `iq-r` | live-validated on `L16HCPU` |
+| `iq-l` | `4e` | `iqr` | hexadecimal | `iq-l` | live-validated on `L16HCPU` |
 | `mx-f` | `4e` | `iqr` | hexadecimal | `mx-f` | provisional; review in `TODO.md` |
 | `mx-r` | `4e` | `iqr` | hexadecimal | `mx-r` | provisional; review in `TODO.md` |
 | `qcpu` | `3e` | `ql` | hexadecimal | `qcpu` | retained path |
@@ -94,7 +94,7 @@ High-level accepted `plc_family` values:
 | --- | --- | --- |
 | `iq-f` | FX5 / iQ-F | `X` / `Y` use manual octal text |
 | `iq-r` | iQ-R | `X` / `Y` use hexadecimal text |
-| `iq-l` | iQ-L | mapped to the `iq-r` range rules; live-validated on `L16HCPU` |
+| `iq-l` | iQ-L | independent iQ-L range rules; live-validated on `L16HCPU` |
 | `mx-f` | MX-F | pending live validation |
 | `mx-r` | MX-R | pending live validation |
 | `qcpu` | QCPU | `3e/ql` fixed profile |

TODO.md

@@ -4,18 +4,18 @@ This file tracks the remaining tasks and unresolved issues for the SLMP Python l
 
 ## 1. Protocol Implementation Gaps
 
-- **`G/HG` Extended Specification live coverage expansion**
+- **Extended Specification live coverage expansion**
   The capture-aligned implementation is working on validated paths, but broader
-  address-range, transport, and PLC-family coverage is still open.
+  address-range, transport, and PLC-family coverage is still open. QnUDV has no
+  `HG`; `U0\G10` read-only on the current QnUDV target returned `0xC070` with
+  command `0x0401` subcommand `0x0080`.
 
 - **Mixed block write root cause**
   The practical fallback is implemented, but the reason some validated PLC
   paths reject the first one-request mixed `1406` write with `0xC05B` is still
-  not fully explained.
-
-- **`1617` Clear Error operator-visible effect**
-  Transport-level acceptance is confirmed, but the operator-visible behavior on
-  real hardware still needs better evidence.
+  not fully explained. On the current QnUDV target, word-only, bit-only, and
+  mixed `1406` block writes returned `0xC059`, so this appears to be block-write
+  command support rather than a mixed-only rejection on that target.
 
 ## 2. Testing & Validation
 
@@ -35,8 +35,10 @@ This file tracks the remaining tasks and unresolved issues for the SLMP Python l
 
 ## 4. Cross-Stack API Alignment
 
+- [x] **Validate iQ-F X/Y octal handling on FX5 hardware**: FX5UC-32MT/D returned `X0000-X1777` and `Y0000-Y1777` as `Base8`; `X100` and `Y100` read successfully through iQ-F octal address parsing.
+- [x] **Split iQ-L from iQ-R range rules**: `iq-l` now resolves to its own range family while keeping 4E/iQR communication and iQ-R-style address parsing. `L16HCPU` was live-validated with `SM0-SM4095`, `SD0-SD4095`, `D0-D18431`, `LZ0-LZ1`, `LTN0-LTN1023`, `LSTN0-LSTN31`, and `LCN0-LCN511`.
+- [x] **Resolve Q-series runtime device ranges**: QCPU/LCPU/QnU/QnUDV `ZR` ranges are selected by probing readable addresses, `R` follows the probed `ZR` count capped at `R32767`, QCPU `Z` is selected by probing `Z15`, and LCPU/QnU/QnUDV `Z` is fixed at 20 points.
 - [ ] **Keep helper naming aligned with the managed stacks**: Preserve the shared high-level contract around `open_and_connect`, `read_typed`, `write_typed`, `write_bit_in_word`, `read_named`, and `poll`.
 - [ ] **Review public address helper exposure**: Decide whether the address parse/normalize/format helpers should be elevated into an explicit public utility API so applications do not need private string-parsing copies.
 - [ ] **Keep `plc_family` as the only high-level PLC selector**: Raw `frame_type`, access-profile, and range-family knobs should stay low-level only unless new live evidence forces a public exception.
 - [ ] **Preserve semantic atomicity by default**: Do not silently split reads or writes that callers would reasonably treat as one logical value or one logical block. Protocol-defined boundaries are acceptable, but fallback retries that change semantics should be opt-in and explicitly named.
-- [ ] **Preserve semantic atomicity by default**: Do not silently split reads or writes that callers would reasonably treat as one logical value or one logical block. Protocol-defined boundaries are acceptable, but fallback retries that change semantics should be opt-in and explicitly named.

docsrc/user/GETTING_STARTED.md

@@ -54,7 +54,7 @@ Current fixed mapping:
 | --- | --- | --- | --- | --- |
 | `iq-f` | `3e` | `ql` | octal | `iq-f` |
 | `iq-r` | `4e` | `iqr` | hexadecimal | `iq-r` |
-| `iq-l` | `4e` | `iqr` | hexadecimal | `iq-r` |
+| `iq-l` | `4e` | `iqr` | hexadecimal | `iq-l` |
 | `mx-f` | `4e` | `iqr` | hexadecimal | `mx-f` |
 | `mx-r` | `4e` | `iqr` | hexadecimal | `mx-r` |
 | `qcpu` | `3e` | `ql` | hexadecimal | `qcpu` |

docsrc/user/USER_GUIDE.md

@@ -95,7 +95,7 @@ For the recommended high-level helper layer, `plc_family` is the only PLC select
 | --- | --- | --- | --- | --- | --- |
 | `iq-f` | `3e` | `ql` | octal | `iq-f` | live-validated |
 | `iq-r` | `4e` | `iqr` | hexadecimal | `iq-r` | live-validated |
-| `iq-l` | `4e` | `iqr` | hexadecimal | `iq-r` | live-validated on `L16HCPU` |
+| `iq-l` | `4e` | `iqr` | hexadecimal | `iq-l` | live-validated on `L16HCPU` |
 | `mx-f` | `4e` | `iqr` | hexadecimal | `mx-f` | provisional |
 | `mx-r` | `4e` | `iqr` | hexadecimal | `mx-r` | provisional |
 | `qcpu` | `3e` | `ql` | hexadecimal | `qcpu` | retained path |

slmp/core.py

@@ -135,7 +135,7 @@ class _PlcFamilyDefaults:
 _PLC_FAMILY_DEFAULTS: dict[str, _PlcFamilyDefaults] = {
     "iq-f": _PlcFamilyDefaults(FrameType.FRAME_3E, PLCSeries.QL, "iq-f", "iq-f"),
     "iq-r": _PlcFamilyDefaults(FrameType.FRAME_4E, PLCSeries.IQR, "iq-r", "iq-r"),
-    "iq-l": _PlcFamilyDefaults(FrameType.FRAME_4E, PLCSeries.IQR, "iq-r", "iq-r"),
+    "iq-l": _PlcFamilyDefaults(FrameType.FRAME_4E, PLCSeries.IQR, "iq-r", "iq-l"),
     "mx-f": _PlcFamilyDefaults(FrameType.FRAME_4E, PLCSeries.IQR, "mx-f", "mx-f"),
     "mx-r": _PlcFamilyDefaults(FrameType.FRAME_4E, PLCSeries.IQR, "mx-r", "mx-r"),
     "qcpu": _PlcFamilyDefaults(FrameType.FRAME_3E, PLCSeries.QL, "qcpu", "qcpu"),

slmp/device_ranges.py

@@ -15,6 +15,7 @@ class SlmpDeviceRangeFamily(str, Enum):
     """Explicit PLC family used to read device-range configuration."""
 
     IqR = "iq-r"
+    IqL = "iq-l"
     MxF = "mx-f"
     MxR = "mx-r"
     IqF = "iq-f"
@@ -493,6 +494,11 @@ def _undefined(notes: str) -> _RangeValueSpec:
     ),
 }
 
+_PROFILES[SlmpDeviceRangeFamily.IqL] = replace(
+    _PROFILES[SlmpDeviceRangeFamily.IqR],
+    family=SlmpDeviceRangeFamily.IqL,
+)
+
 
 def normalize_device_range_family(value: SlmpDeviceRangeFamily | str) -> SlmpDeviceRangeFamily:
     """Normalize one canonical family identifier."""
@@ -512,6 +518,7 @@ def family_label(family: SlmpDeviceRangeFamily | str) -> str:
     normalized = normalize_device_range_family(family)
     return {
         SlmpDeviceRangeFamily.IqR: "IQ-R",
+        SlmpDeviceRangeFamily.IqL: "iQ-L",
         SlmpDeviceRangeFamily.MxF: "MX-F",
         SlmpDeviceRangeFamily.MxR: "MX-R",
         SlmpDeviceRangeFamily.IqF: "IQ-F",

tests/test_async_client.py

@@ -225,7 +225,7 @@ def test_async_client_plc_family_derives_fixed_profile_defaults() -> None:
     assert cli.plc_series == PLCSeries.IQR
     assert cli.frame_type.value == "4e"
     assert cli.device_family == "iq-r"
-    assert cli.device_range_family == "iq-r"
+    assert cli.device_range_family == "iq-l"
 
 
 @pytest.mark.asyncio

tests/test_device_ranges.py

@@ -140,7 +140,7 @@ def test_read_device_range_catalog_uses_client_plc_family_defaults(self) -> None
 
         catalog = client.read_device_range_catalog()
 
-        self.assertEqual(catalog.family, SlmpDeviceRangeFamily.IqR)
+        self.assertEqual(catalog.family, SlmpDeviceRangeFamily.IqL)
         self.assertEqual(client.plc_family, "iq-l")
         self.assertEqual(
             client.last_request,

tests/test_slmp.py

@@ -1792,7 +1792,7 @@ def test_plc_family_derives_fixed_profile_defaults(self) -> None:
         self.assertEqual(client.plc_series, PLCSeries.IQR)
         self.assertEqual(client.frame_type, FrameType.FRAME_4E)
         self.assertEqual(client.device_family, "iq-r")
-        self.assertEqual(client.device_range_family, "iq-r")
+        self.assertEqual(client.device_range_family, "iq-l")
 
     def test_plc_family_rejects_manual_profile_override(self) -> None:
         with self.assertRaisesRegex(ValueError, "plc_family already determines"):

tests/test_utils.py

@@ -580,7 +580,7 @@ def test_connection_options_derive_fixed_profile_from_plc_family(self):
         self.assertEqual(options.plc_series.value, "iqr")
         self.assertEqual(options.frame_type.value, "4e")
         self.assertEqual(options.device_family, "iq-r")
-        self.assertEqual(options.device_range_family, "iq-r")
+        self.assertEqual(options.device_range_family, "iq-l")
 
 
 # ---------------------------------------------------------------------------