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Merge pull request #4435 from zijianli1234/dev
add riscv ci
2 parents afa96bb + 534860c commit a1e11db

3 files changed

Lines changed: 78 additions & 61 deletions

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‎.github/workflows/dev-short-tests.yml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,9 @@ jobs:
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if: ${{ matrix.name == 'RISC-V' }}
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run: |
462462
LDFLAGS="-static" CC=$XCC QEMU_SYS=$XEMU make clean check
463+
CFLAGS="-march=rv64gcv -O3" LDFLAGS="-static -DMEM_FORCE_MEMORY_ACCESS=0" CC=$XCC QEMU_SYS="$XEMU -cpu rv64,v=true,vlen=128" make clean check
464+
CFLAGS="-march=rv64gcv -O3" LDFLAGS="-static -DMEM_FORCE_MEMORY_ACCESS=0" CC=$XCC QEMU_SYS="$XEMU -cpu rv64,v=true,vlen=256" make clean check
465+
CFLAGS="-march=rv64gcv -O3" LDFLAGS="-static -DMEM_FORCE_MEMORY_ACCESS=0" CC=$XCC QEMU_SYS="$XEMU -cpu rv64,v=true,vlen=512" make clean check
463466
- name: M68K
464467
if: ${{ matrix.name == 'M68K' }}
465468
run: |

‎lib/common/compiler.h‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -224,9 +224,17 @@
224224
# if defined(__ARM_FEATURE_SVE2)
225225
# define ZSTD_ARCH_ARM_SVE2
226226
# endif
227-
# if defined(__riscv) && defined(__riscv_vector)
228-
# define ZSTD_ARCH_RISCV_RVV
229-
# endif
227+
#if defined(__riscv) && defined(__riscv_vector)
228+
#if defined(__GNUC__)
229+
#if (__GNUC__ > 14 || (__GNUC__ == 14 && __GNUC_MINOR__ >= 1))
230+
#define ZSTD_ARCH_RISCV_RVV
231+
#endif
232+
#elif defined(__clang__)
233+
#if __clang_major__ > 18 || (__clang_major__ == 18 && __clang_minor__ >= 1)
234+
#define ZSTD_ARCH_RISCV_RVV
235+
#endif
236+
#endif
237+
#endif
230238
#
231239
# if defined(ZSTD_ARCH_X86_AVX2)
232240
# include <immintrin.h>

‎lib/compress/zstd_compress.c‎

Lines changed: 64 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -7295,7 +7295,7 @@ size_t convertSequences_noRepcodes(
72957295
#elif defined ZSTD_ARCH_RISCV_RVV
72967296
#include <riscv_vector.h>
72977297
/*
7298-
* Convert `vl` sequences per iteration, using AVX2 intrinsics:
7298+
* Convert `vl` sequences per iteration, using RVV intrinsics:
72997299
* - offset -> offBase = offset + 2
73007300
* - litLength -> (U16) litLength
73017301
* - matchLength -> (U16)(matchLength - 3)
@@ -7308,7 +7308,8 @@ size_t convertSequences_noRepcodes(
73087308
*/
73097309
size_t convertSequences_noRepcodes(SeqDef* dstSeqs, const ZSTD_Sequence* inSeqs, size_t nbSequences) {
73107310
size_t longLen = 0;
7311-
7311+
size_t vl = 0;
7312+
typedef uint32_t __attribute__((may_alias)) aliased_u32;
73127313
/* RVV depends on the specific definition of target structures */
73137314
ZSTD_STATIC_ASSERT(sizeof(ZSTD_Sequence) == 16);
73147315
ZSTD_STATIC_ASSERT(offsetof(ZSTD_Sequence, offset) == 0);
@@ -7318,62 +7319,68 @@ size_t convertSequences_noRepcodes(SeqDef* dstSeqs, const ZSTD_Sequence* inSeqs,
73187319
ZSTD_STATIC_ASSERT(offsetof(SeqDef, offBase) == 0);
73197320
ZSTD_STATIC_ASSERT(offsetof(SeqDef, litLength) == 4);
73207321
ZSTD_STATIC_ASSERT(offsetof(SeqDef, mlBase) == 6);
7321-
size_t vl = 0;
7322+
73227323
for (size_t i = 0; i < nbSequences; i += vl) {
73237324

7324-
vl = __riscv_vsetvl_e32m2(nbSequences-i);
7325-
// Loading structure member variables
7326-
vuint32m2x4_t v_tuple = __riscv_vlseg4e32_v_u32m2x4(
7327-
(const int32_t*)&inSeqs[i],
7328-
vl
7329-
);
7330-
vuint32m2_t v_offset = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 0);
7331-
vuint32m2_t v_lit = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 1);
7332-
vuint32m2_t v_match = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 2);
7333-
// offset + ZSTD_REP_NUM
7334-
vuint32m2_t v_offBase = __riscv_vadd_vx_u32m2(v_offset, ZSTD_REP_NUM, vl);
7335-
// Check for integer overflow
7336-
// Cast to a 16-bit variable
7337-
vbool16_t lit_overflow = __riscv_vmsgtu_vx_u32m2_b16(v_lit, 65535, vl);
7338-
vuint16m1_t v_lit_clamped = __riscv_vncvt_x_x_w_u16m1(v_lit, vl);
7339-
7340-
vbool16_t ml_overflow = __riscv_vmsgtu_vx_u32m2_b16(v_match, 65535+MINMATCH, vl);
7341-
vuint16m1_t v_ml_clamped = __riscv_vncvt_x_x_w_u16m1(__riscv_vsub_vx_u32m2(v_match, MINMATCH, vl), vl);
7342-
7343-
// Pack two 16-bit fields into a 32-bit value (little-endian)
7344-
// The lower 16 bits contain litLength, and the upper 16 bits contain mlBase
7345-
vuint32m2_t v_lit_ml_combined = __riscv_vsll_vx_u32m2(
7346-
__riscv_vwcvtu_x_x_v_u32m2(v_ml_clamped, vl), // Convert matchLength to 32-bit
7347-
16,
7348-
vl
7349-
);
7350-
v_lit_ml_combined = __riscv_vor_vv_u32m2(
7351-
v_lit_ml_combined,
7352-
__riscv_vwcvtu_x_x_v_u32m2(v_lit_clamped, vl),
7353-
vl
7354-
);
7355-
// Create a vector of SeqDef structures
7356-
// Store the offBase, litLength, and mlBase in a vector of SeqDef
7357-
vuint32m2x2_t store_data = __riscv_vcreate_v_u32m2x2(
7358-
v_offBase,
7359-
v_lit_ml_combined
7360-
);
7361-
__riscv_vsseg2e32_v_u32m2x2(
7362-
(uint32_t*)&dstSeqs[i],
7363-
store_data,
7364-
vl
7365-
);
7366-
// Find the first index where an overflow occurs
7367-
int first_ml = __riscv_vfirst_m_b16(ml_overflow, vl);
7368-
int first_lit = __riscv_vfirst_m_b16(lit_overflow, vl);
7325+
vl = __riscv_vsetvl_e32m2(nbSequences-i);
7326+
{
7327+
// Loading structure member variables
7328+
vuint32m2x4_t v_tuple = __riscv_vlseg4e32_v_u32m2x4(
7329+
(const aliased_u32*)((const void*)&inSeqs[i]),
7330+
vl
7331+
);
7332+
vuint32m2_t v_offset = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 0);
7333+
vuint32m2_t v_lit = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 1);
7334+
vuint32m2_t v_match = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 2);
7335+
// offset + ZSTD_REP_NUM
7336+
vuint32m2_t v_offBase = __riscv_vadd_vx_u32m2(v_offset, ZSTD_REP_NUM, vl);
7337+
// Check for integer overflow
7338+
// Cast to a 16-bit variable
7339+
vbool16_t lit_overflow = __riscv_vmsgtu_vx_u32m2_b16(v_lit, 65535, vl);
7340+
vuint16m1_t v_lit_clamped = __riscv_vncvt_x_x_w_u16m1(v_lit, vl);
7341+
7342+
vbool16_t ml_overflow = __riscv_vmsgtu_vx_u32m2_b16(v_match, 65535+MINMATCH, vl);
7343+
vuint16m1_t v_ml_clamped = __riscv_vncvt_x_x_w_u16m1(__riscv_vsub_vx_u32m2(v_match, MINMATCH, vl), vl);
7344+
7345+
// Pack two 16-bit fields into a 32-bit value (little-endian)
7346+
// The lower 16 bits contain litLength, and the upper 16 bits contain mlBase
7347+
vuint32m2_t v_lit_ml_combined = __riscv_vsll_vx_u32m2(
7348+
__riscv_vwcvtu_x_x_v_u32m2(v_ml_clamped, vl), // Convert matchLength to 32-bit
7349+
16,
7350+
vl
7351+
);
7352+
v_lit_ml_combined = __riscv_vor_vv_u32m2(
7353+
v_lit_ml_combined,
7354+
__riscv_vwcvtu_x_x_v_u32m2(v_lit_clamped, vl),
7355+
vl
7356+
);
7357+
{
7358+
// Create a vector of SeqDef structures
7359+
// Store the offBase, litLength, and mlBase in a vector of SeqDef
7360+
vuint32m2x2_t store_data = __riscv_vcreate_v_u32m2x2(
7361+
v_offBase,
7362+
v_lit_ml_combined
7363+
);
7364+
__riscv_vsseg2e32_v_u32m2x2(
7365+
(aliased_u32*)((void*)&dstSeqs[i]),
7366+
store_data,
7367+
vl
7368+
);
7369+
}
7370+
{
7371+
// Find the first index where an overflow occurs
7372+
int first_ml = __riscv_vfirst_m_b16(ml_overflow, vl);
7373+
int first_lit = __riscv_vfirst_m_b16(lit_overflow, vl);
73697374

7370-
if (UNLIKELY(first_ml != -1)) {
7371-
assert(longLen == 0);
7372-
longLen = i + first_ml + 1;
7373-
}
7374-
if (UNLIKELY(first_lit != -1)) {
7375-
assert(longLen == 0);
7376-
longLen = i + first_lit + 1 + nbSequences;
7375+
if (UNLIKELY(first_ml != -1)) {
7376+
assert(longLen == 0);
7377+
longLen = i + first_ml + 1;
7378+
}
7379+
if (UNLIKELY(first_lit != -1)) {
7380+
assert(longLen == 0);
7381+
longLen = i + first_lit + 1 + nbSequences;
7382+
}
7383+
}
73777384
}
73787385
}
73797386
return longLen;
@@ -7677,18 +7684,17 @@ BlockSummary ZSTD_get1BlockSummary(const ZSTD_Sequence* seqs, size_t nbSeqs)
76777684
size_t i = 0;
76787685
int found_terminator = 0;
76797686
size_t vl_max = __riscv_vsetvlmax_e32m1();
7687+
typedef uint32_t __attribute__((may_alias)) aliased_u32;
76807688
vuint32m1_t v_lit_sum = __riscv_vmv_v_x_u32m1(0, vl_max);
76817689
vuint32m1_t v_match_sum = __riscv_vmv_v_x_u32m1(0, vl_max);
76827690

76837691
for (; i < nbSeqs; ) {
76847692
size_t vl = __riscv_vsetvl_e32m2(nbSeqs - i);
76857693

7686-
ptrdiff_t stride = sizeof(ZSTD_Sequence); // 16
76877694
vuint32m2x4_t v_tuple = __riscv_vlseg4e32_v_u32m2x4(
7688-
(const int32_t*)&seqs[i],
7695+
(const aliased_u32*)((const void*)&seqs[i]),
76897696
vl
76907697
);
7691-
vuint32m2_t v_offset = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 0);
76927698
vuint32m2_t v_lit = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 1);
76937699
vuint32m2_t v_match = __riscv_vget_v_u32m2x4_u32m2(v_tuple, 2);
76947700

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