add riscv ci#4435
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This PR adds RISCV RVV CI support, including tests for vlen=128, 256, 512, and includes detection of compiler versions for RVV extensions. Some compilation warnings have also been fixed. Additionally, on the Spacemit® X60 @1.6 GHz platform, when the RISC-V Vector (V) extension is enabled along with O3 optimization,unaligned memory access errors may occur if
-DMEM_FORCE_MEMORY_ACCESS=0is not specified. Therefore, this compile-time flag has been added to the CI configuration.This PR is largely identical to a previous one(#4422 ). The reason for closing and resubmitting is that the previous branch was out of sync due to an outdated version. After pulling the latest changes, the PR is re-submitted.