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python-release.yml
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More README cleanup, add a note on why we use just to the justfile. Build and publish release #34: Commit 3f06544 pushed by fdxmw
20s development
development
20s
Revert to python 3.13, remove gcc dependency Build and publish release #33: Commit e1456bb pushed by fdxmw
19s development
development
19s
github actions workflow cleanup Build and publish release #32: Commit c2a1d87 pushed by fdxmw
17s development
development
17s
Minor README rewording. Build and publish release #31: Commit d5fc8d1 pushed by fdxmw
15s development
development
15s
Experimental uv support for PyRTL. Build and publish release #30: Commit 44119c4 pushed by fdxmw
27s development
development
27s
Fix code style issues identified by newer versions of ruff. Also: Build and publish release #29: Commit 8c706f6 pushed by fdxmw
13s development
development
13s
Update CHANGELOG.md for 0.12 release Build and publish release #28: Commit 5ad9ed6 pushed by fdxmw
16s development
development
16s
Clean up output_to_verilog's newline logic. This simplifies the cod… Build and publish release #27: Commit a3bc638 pushed by fdxmw
16s verilog
verilog
16s
Minor Verilog output improvements: Move lines with only "begin" to th… Build and publish release #26: Commit bd716e8 pushed by fdxmw
12s verilog
verilog
12s
Improve Verilog output by using sanitized MemBlock and RomBlock names… Build and publish release #25: Commit c4265e9 pushed by fdxmw
17s verilog
verilog
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Update _NameSanitizer to try appending the current internal_index bef… Build and publish release #24: Commit 07ec4c3 pushed by fdxmw
14s verilog
verilog
14s
Improve Verilog identifier naming, fix two bugs, add tests, refactor … Build and publish release #23: Commit 7be57c8 pushed by fdxmw
14s verilog
verilog
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Fix two bugs, add tests, refactor duplicated code: Build and publish release #22: Commit 5508deb pushed by fdxmw
20s verilog
verilog
20s
Update output_to_verilog to inline temporary wires, using GateGraph: Build and publish release #21: Commit c94b341 pushed by fdxmw
17s verilog
verilog
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Update output_to_verilog to inline single-use temporaries, using `G… Build and publish release #20: Commit 0c3041f pushed by fdxmw
19s verilog
verilog
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Update export_verilog_testbench to use gates. Build and publish release #19: Commit ca47fd9 pushed by fdxmw
14s verilog
verilog
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Initial implementation of GateGraph, an alternative PyRTL logic rep… Build and publish release #18: Commit 3deeedd pushed by fdxmw
12s development
development
12s
Add more documentation examples and references. Build and publish release #17: Commit 875f56a pushed by fdxmw
18s gate
gate
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Minor documentation rewording, trying to better explain the differenc… Build and publish release #16: Commit be6a12a pushed by fdxmw
17s gate
gate
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Split GateGraph.memories into GateGraph.mem_reads and `GateGraph.… Build and publish release #15: Commit 3b6491b pushed by fdxmw
14s gate
gate
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Make gates, sources, and sinks sets instead of lists, so it… Build and publish release #14: Commit c4d4fa8 pushed by fdxmw
13s gate
gate
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Reduce figure size. Build and publish release #13: Commit cfa50aa pushed by fdxmw
16s gate
gate
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Apply a bunch of renames: Build and publish release #12: Commit 38ed8f9 pushed by fdxmw
15s gate
gate
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Minor documentation improvements and add a test with a register self-… Build and publish release #11: Commit f0d73fb pushed by fdxmw
13s gate
gate
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Improve test coverage. Build and publish release #10: Commit 81fa28b pushed by fdxmw
17s gate
gate
17s