Update output_to_verilog to inline single-use temporaries, using GateGraph:

- Any Gate with a user-specified name is never inlined.
- Unnamed constant Gates are always inlined.
- Unnamed non-constant Gates are inlined if:
  - The Gate has one user, AND
  - The Gate is not a MemBlock read, AND
  - The Gate is not an arg to a bit-select Gate.

Also:

- Update `output_verilog_testbench` to use `GateGraph`.
- Define `GateGraph.__iter__` to make it easier to iterate over all Gates.
- Delete some disabled tests in `test_aes.py`.

Author: fdxmw

pyrtl/gate_graph.py

@@ -1114,3 +1114,25 @@ def __str__(self) -> str:
             self.gates, key=lambda gate: gate.name if gate.name else "~~~"
         )
         return "\n".join([str(gate) for gate in sorted_gates])
+
+    def __iter__(self):
+        """Iterate over each gate in the :class:`GateGraph`.
+
+        .. doctest only::
+
+            >>> import pyrtl
+            >>> pyrtl.reset_working_block()
+
+        Example::
+
+            >>> a = pyrtl.Input(name="a", bitwidth=2)
+            >>> b = pyrtl.Input(name="b", bitwidth=2)
+            >>> sum = a + b
+            >>> sum.name = "sum"
+
+            >>> gate_graph = pyrtl.GateGraph()
+
+            >>> sorted(gate.name for gate in gate_graph)
+            ['a', 'b', 'sum']
+        """
+        return iter(self.gates)