Revert isinstance changes from 3a1bbd2 because they weren't always working.

3a1bbd2 attempted to make `wire_struct` and `wire_matrix` pass `isinstance`
checks without a call to `as_wires`. This did not work reliably because there
is only one `wire_struct` or `wire_matrix` class created for each type, and
that one class would get registered as subclasses for different WireVector
types. So this example did not work:

```
const_byte = Byte(Byte=0xAB)
input_byte = Byte(concatenated_type=pyrtl.Input)

# With 3a1bbd2, this would return True, but it should return False.
isinstance(const_byte, pyrtl.Input)
```

This commit reverts broken the subclass registration.

The safest way to check the actual type of a `wire_struct` or `wire_matrix` is
to call `as_wires` to unwrap the `WrappedWireVector`. Added documentation and
tests.

Author: fdxmw

pyrtl/helperfuncs.py

@@ -1507,13 +1507,19 @@ def wire_struct(wire_struct_spec):
     Both the instance and the slices are first-class :class:`WireVector`, so they can be
     manipulated with all the usual PyRTL operators::
 
-        >>> isinstance(byte, pyrtl.WireVector)
+        >>> isinstance(pyrtl.as_wires(byte), pyrtl.WireVector)
         True
-        >>> isinstance(byte.low, pyrtl.WireVector)
+        >>> isinstance(pyrtl.as_wires(byte.low), pyrtl.WireVector)
         True
-        >>> isinstance(byte.high, pyrtl.WireVector)
+        >>> isinstance(pyrtl.as_wires(byte.high), pyrtl.WireVector)
         True
 
+    .. NOTE::
+
+        The instance and slices may be proxies with the same interface as
+        :class:`WireVector`, so you must call :func:`as_wires` before inspecting their
+        types.
+
     ``len()`` returns the number of components in the ``@wire_struct``::
 
         >>> byte = Byte(Byte=0xAB)
@@ -1609,7 +1615,7 @@ class CacheLine:
         >>> byte = Byte(name="output_byte", component_type=pyrtl.Output,
         ...             Byte=0xCD)
 
-        >>> isinstance(byte.high, pyrtl.Output)
+        >>> isinstance(pyrtl.as_wires(byte.high), pyrtl.Output)
         True
         >>> byte.high.name
         'output_byte.high'
@@ -1619,7 +1625,7 @@ class CacheLine:
 
         # Generates an Input named ``input_byte``.
         >>> input_byte = Byte(name="input_byte", concatenated_type=pyrtl.Input)
-        >>> isinstance(input_byte, pyrtl.Input)
+        >>> isinstance(pyrtl.as_wires(input_byte), pyrtl.Input)
         True
         >>> isinstance(input_byte, Byte)
         True
@@ -1823,10 +1829,6 @@ class Byte:
                 bitwidth=self._bitwidth, name=name, block=block
             )
 
-        # Register our type as a subclass of `concatenated_type` so
-        #     isinstance(wire_struct_instance, concatenated_type)
-        # returns `True`. See the documentation for `abc.ABCMeta.register()`.
-        concatenated_type.register(type(self))
         WrappedWireVector.__init__(self, wire=concatenated)
 
         # self._components maps from component name to each component's WireVector.
@@ -1978,11 +1980,11 @@ def wire_matrix(component_schema, size: int, class_name: str | None = None):
     Both the instance and the slices are first-class :class:`WireVector`, so they can be
     manipulated with all the usual PyRTL operators::
 
-        >>> isinstance(word, pyrtl.WireVector)
+        >>> isinstance(pyrtl.as_wires(word), pyrtl.WireVector)
         True
         >>> word.bitwidth
         32
-        >>> isinstance(word[0], pyrtl.WireVector)
+        >>> isinstance(pyrtl.as_wires(word[0]), pyrtl.WireVector)
         True
         >>> word[0].bitwidth
         8
@@ -2068,7 +2070,7 @@ class Byte:
         ...             component_type=pyrtl.Output,
         ...             values=[0x89ABCDEF])
 
-        >>> isinstance(word[1], pyrtl.Output)
+        >>> isinstance(pyrtl.as_wires(word[1]), pyrtl.Output)
         True
         >>> word[1].name
         'output_word[1]'
@@ -2078,7 +2080,7 @@ class Byte:
 
         # Generates an Input named ``input_word``.
         >>> word = Word(name="input_word", concatenated_type=pyrtl.Input)
-        >>> isinstance(word, pyrtl.Input)
+        >>> isinstance(pyrtl.as_wires(word), pyrtl.Input)
         True
         >>> isinstance(word, Word)
         True
@@ -2129,10 +2131,6 @@ def _init(
                 bitwidth=self._bitwidth, name=name, block=block
             )
 
-        # Register our type as a subclass of `concatenated_type` so
-        #     isinstance(wire_matrix_instance, concatenated_type)
-        # returns `True`. See the documentation for `abc.ABCMeta.register()`.
-        concatenated_type.register(type(self))
         WrappedWireVector.__init__(self, wire=concatenated)
 
         schema = []

pyrtl/memory.py

@@ -19,7 +19,6 @@
 import collections
 import numbers
 import types
-from abc import ABCMeta
 from collections.abc import Callable, Sequence
 from typing import NamedTuple
 
@@ -48,7 +47,7 @@ def _reset_memory_indexer():
     _memIndex = _NameIndexer()
 
 
-class _MemIndexed(WireVector, metaclass=ABCMeta):
+class _MemIndexed(WireVector):
     """Object used internally to route memory assigns correctly.
 
     The normal PyRTL user should never need to be aware that this class exists, hence

pyrtl/wire.py

@@ -19,7 +19,6 @@
 import numbers
 import re
 import traceback
-from abc import ABCMeta
 
 from pyrtl import core  # needed for _setting_keep_wirevector_call_stack
 from pyrtl.core import Block, LogicNet, _NameIndexer, working_block
@@ -57,7 +56,7 @@ def next_tempvar_name(name=""):
     return name
 
 
-class WireVector(metaclass=ABCMeta):
+class WireVector:
     """The main class for describing the connections between operators.
 
     :class:`WireVectors<WireVector>` act much like a list of wires, except that there is
@@ -1465,7 +1464,7 @@ def _extend_with_bit(self, bitwidth, extbit):
 # |__  \_/  |  |__  |\ | |  \ |__  |  \    \  / |__  /  `  |  /  \ |__) /__`
 # |___ / \  |  |___ | \| |__/ |___ |__/     \/  |___ \__,  |  \__/ |  \ .__/
 #
-class Input(WireVector, metaclass=ABCMeta):
+class Input(WireVector):
     """A :class:`WireVector` placeholder for inputs to a :class:`Block`.
 
     .. doctest only::
@@ -1527,7 +1526,7 @@ def __ior__(self, _):
         raise PyrtlError(msg)
 
 
-class Output(WireVector, metaclass=ABCMeta):
+class Output(WireVector):
     """A :class:`WireVector` type denoting outputs of a :class:`Block`.
 
     .. doctest only::
@@ -1555,7 +1554,7 @@ def __init__(
         super().__init__(bitwidth, name, block)
 
 
-class Const(WireVector, metaclass=ABCMeta):
+class Const(WireVector):
     """A :class:`WireVector` representation of a constant value.
 
     Converts from :class:`bool`, :class:`int`, or Verilog-style :class:`str` to a
@@ -1661,7 +1660,7 @@ def __ior__(self, _):
         raise PyrtlError(msg)
 
 
-class Register(WireVector, metaclass=ABCMeta):
+class Register(WireVector):
     """A WireVector with an embedded register state element.
 
     Registers only update their outputs on the rising edges of an implicit clock signal.

tests/test_helperfuncs.py

@@ -1351,15 +1351,15 @@ def test_concatenate(self):
         # Concatenates to 'byte'.
         byte = Byte(name="byte", high=0xA, low=0xB)
         self.assertTrue(isinstance(byte, Byte))
-        self.assertTrue(isinstance(byte, pyrtl.WireVector))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte), pyrtl.WireVector))
         self.assertEqual(Byte.__name__, "Byte")
         self.assertEqual(len(byte), 2)
         self.assertEqual(byte.bitwidth, 8)
         self.assertEqual(len(pyrtl.as_wires(byte)), 8)
         self.assertEqual(len(byte.high), 4)
-        self.assertTrue(isinstance(byte.high, pyrtl.WireVector))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.high), pyrtl.WireVector))
         self.assertEqual(len(byte.low), 4)
-        self.assertTrue(isinstance(byte.low, pyrtl.WireVector))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.low), pyrtl.WireVector))
 
         sim = pyrtl.Simulation()
         sim.step()
@@ -1392,11 +1392,11 @@ def test_slice(self):
         byte = Byte(name="byte", Byte=0xCD)
 
         # Constants are sliced immediately.
-        self.assertTrue(isinstance(byte, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte), pyrtl.Const))
         self.assertEqual(byte.val, 0xCD)
-        self.assertTrue(isinstance(byte.high, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.high), pyrtl.Const))
         self.assertEqual(byte.high.val, 0xC)
-        self.assertTrue(isinstance(byte.low, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.low), pyrtl.Const))
         self.assertEqual(byte.low.val, 0xD)
 
     def test_underscore_value_slice(self):
@@ -1407,31 +1407,37 @@ def test_underscore_value_slice(self):
         byte = Byte(name="byte", _value=0xCD)
 
         # Constants are sliced immediately.
-        self.assertTrue(isinstance(byte, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte), pyrtl.Const))
         self.assertEqual(byte.val, 0xCD)
-        self.assertTrue(isinstance(byte.high, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.high), pyrtl.Const))
         self.assertEqual(byte.high.val, 0xC)
-        self.assertTrue(isinstance(byte.low, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.low), pyrtl.Const))
         self.assertEqual(byte.low.val, 0xD)
 
     def test_input_slice(self):
         """Given Input concatenated high+low, observe high and low."""
         byte = Byte(name="byte", concatenated_type=pyrtl.Input)
 
-        self.assertTrue(isinstance(byte, pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte), pyrtl.Input))
 
         sim = pyrtl.Simulation()
         sim.step(provided_inputs={"byte": 0xAB})
         self.assertEqual(sim.inspect("byte"), 0xAB)
         self.assertEqual(sim.inspect("byte.high"), 0xA)
         self.assertEqual(sim.inspect("byte.low"), 0xB)
 
+        # Make a Const byte and check its type. This ensures we don't get the type of
+        # `const_byte` mixed up with the type of `byte`.
+        const_byte = Byte(name="const_byte", Byte=0xCD)
+        self.assertEqual(type(pyrtl.as_wires(const_byte)), pyrtl.Const)
+        self.assertFalse(isinstance(pyrtl.as_wires(const_byte), pyrtl.Input))
+
     def test_input_concatenate(self):
         """Given Input high and low, observe concatenated high+low."""
         byte = Byte(name="byte", component_type=pyrtl.Input)
 
-        self.assertTrue(isinstance(byte.high, pyrtl.Input))
-        self.assertTrue(isinstance(byte.low, pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.high), pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.low), pyrtl.Input))
 
         sim = pyrtl.Simulation()
         sim.step(provided_inputs={"byte.low": 0xB, "byte.high": 0xA})
@@ -1443,8 +1449,8 @@ def test_output_slice(self):
         """Drive concatenated high+low, observe high and low as Outputs."""
         byte = Byte(name="byte", component_type=pyrtl.Output, Byte=0xCD)
 
-        self.assertTrue(isinstance(byte.high, pyrtl.Output))
-        self.assertTrue(isinstance(byte.low, pyrtl.Output))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.high), pyrtl.Output))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte.low), pyrtl.Output))
 
         sim = pyrtl.Simulation()
         sim.step()
@@ -1456,7 +1462,7 @@ def test_output_concatenate(self):
         """Drive high and low, observe concatenated high+low as Output."""
         byte = Byte(name="byte", concatenated_type=pyrtl.Output, high=0xA, low=0xB)
 
-        self.assertTrue(isinstance(byte, pyrtl.Output))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte), pyrtl.Output))
 
         sim = pyrtl.Simulation()
         sim.step()
@@ -1470,7 +1476,7 @@ def test_register_slice(self):
         next_value = pyrtl.Input(name="next_value", bitwidth=8)
         byte.next <<= next_value
 
-        self.assertTrue(isinstance(byte, pyrtl.Register))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte), pyrtl.Register))
 
         sim = pyrtl.Simulation()
         # On the first cycle, set the register's value to 0xAB, but it will take one
@@ -1524,28 +1530,28 @@ def test_pixel_slice(self):
         self.assertEqual(len(pyrtl.as_wires(pixel)), 24)
 
         # Constants are sliced immediately.
-        self.assertTrue(isinstance(pixel, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel), pyrtl.Const))
         self.assertEqual(pixel.val, 0xABCDEF)
 
-        self.assertTrue(isinstance(pixel.red, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.red), pyrtl.Const))
         self.assertEqual(pixel.red.val, 0xAB)
-        self.assertTrue(isinstance(pixel.red.high, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.red.high), pyrtl.Const))
         self.assertEqual(pixel.red.high.val, 0xA)
-        self.assertTrue(isinstance(pixel.red.low, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.red.low), pyrtl.Const))
         self.assertEqual(pixel.red.low.val, 0xB)
 
-        self.assertTrue(isinstance(pixel.green, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.green), pyrtl.Const))
         self.assertEqual(pixel.green.val, 0xCD)
-        self.assertTrue(isinstance(pixel.green.high, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.green.high), pyrtl.Const))
         self.assertEqual(pixel.green.high.val, 0xC)
-        self.assertTrue(isinstance(pixel.green.low, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.green.low), pyrtl.Const))
         self.assertEqual(pixel.green.low.val, 0xD)
 
-        self.assertTrue(isinstance(pixel.blue, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.blue), pyrtl.Const))
         self.assertEqual(pixel.blue.val, 0xEF)
-        self.assertTrue(isinstance(pixel.blue.high, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.blue.high), pyrtl.Const))
         self.assertEqual(pixel.blue.high.val, 0xE)
-        self.assertTrue(isinstance(pixel.blue.low, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(pixel.blue.low), pyrtl.Const))
         self.assertEqual(pixel.blue.low.val, 0xF)
 
     def test_pixel_concatenate(self):
@@ -1693,14 +1699,14 @@ def setUp(self):
     def test_wire_matrix_slice(self):
         bitpair = BitPair(name="bitpair", values=[2])
         self.assertTrue(isinstance(bitpair, BitPair))
-        self.assertTrue(isinstance(bitpair, pyrtl.WireVector))
+        self.assertTrue(isinstance(pyrtl.as_wires(bitpair), pyrtl.WireVector))
         self.assertEqual(BitPair.__name__, "BitPair")
         self.assertEqual(len(bitpair), 2)
         self.assertEqual(bitpair.bitwidth, 2)
         self.assertEqual(len(pyrtl.as_wires(bitpair)), 2)
-        self.assertTrue(isinstance(bitpair[0], pyrtl.WireVector))
+        self.assertTrue(isinstance(pyrtl.as_wires(bitpair[0]), pyrtl.WireVector))
         self.assertEqual(len(bitpair[0]), 1)
-        self.assertTrue(isinstance(bitpair[1], pyrtl.WireVector))
+        self.assertTrue(isinstance(pyrtl.as_wires(bitpair[1]), pyrtl.WireVector))
         self.assertEqual(len(bitpair[1]), 1)
 
         # Constants are sliced immediately.
@@ -1787,8 +1793,8 @@ def test_anonymous_wire_matrix_concatenate(self):
     def test_wire_matrix_input(self):
         word = Word(name="word", component_type=pyrtl.Input)
 
-        self.assertTrue(isinstance(word[0], pyrtl.Input))
-        self.assertTrue(isinstance(word[1], pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(word[0]), pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(word[1]), pyrtl.Input))
 
         sim = pyrtl.Simulation()
         sim.step(provided_inputs={"word[0]": 0xAB, "word[1]": 0xCD})
@@ -1804,7 +1810,7 @@ def test_wire_matrix_register(self):
         word = Word(name="word", concatenated_type=pyrtl.Register)
         word.next <<= 0xABCD
 
-        self.assertTrue(isinstance(word, pyrtl.Register))
+        self.assertTrue(isinstance(pyrtl.as_wires(word), pyrtl.Register))
 
         sim = pyrtl.Simulation()
         sim.step()
@@ -1818,7 +1824,7 @@ def test_wire_matrix_composition_dword(self):
         dword = DWord(name="dword", values=[0x89ABCDEF])
 
         # Constants are sliced immediately.
-        self.assertTrue(isinstance(dword, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(dword), pyrtl.Const))
         self.assertEqual(dword.val, 0x89ABCDEF)
         self.assertEqual(dword[0].val, 0x89AB)
         self.assertEqual(dword[0][0].val, 0x89)
@@ -1858,7 +1864,7 @@ def test_byte_matrix_const(self):
         self.assertEqual(len(pyrtl.as_wires(byte_matrix)), 8)
 
         # Constants are sliced immediately.
-        self.assertTrue(isinstance(byte_matrix, pyrtl.Const))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte_matrix), pyrtl.Const))
         self.assertEqual(byte_matrix.val, 0xAB)
         self.assertEqual(byte_matrix[0].val, 0xAB)
         self.assertEqual(byte_matrix[0].high.val, 0xA)
@@ -1867,7 +1873,7 @@ def test_byte_matrix_const(self):
     def test_byte_matrix_input_slice(self):
         byte_matrix = ByteMatrix(name="byte_matrix", component_type=pyrtl.Input)
 
-        self.assertTrue(isinstance(byte_matrix[0], pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte_matrix[0]), pyrtl.Input))
 
         sim = pyrtl.Simulation()
         sim.step(provided_inputs={"byte_matrix[0]": 0xAB})
@@ -1879,7 +1885,7 @@ def test_byte_matrix_input_slice(self):
     def test_byte_matrix_input_concatenate(self):
         byte_matrix = ByteMatrix(name="byte_matrix", concatenated_type=pyrtl.Input)
 
-        self.assertTrue(isinstance(byte_matrix, pyrtl.Input))
+        self.assertTrue(isinstance(pyrtl.as_wires(byte_matrix), pyrtl.Input))
 
         sim = pyrtl.Simulation()
         sim.step(provided_inputs={"byte_matrix": 0xAB})