Run all tests with Python 3.14 by default. Remove Python 3.9 support because it has reached end-of-life. (UCSBarchlab#478)

Apply some lint fixes that are possible now that we no longer support Python 3.9.

Author: fdxmw

.python-version

@@ -1 +1 @@
-3.13
+3.14

justfile

@@ -11,7 +11,7 @@ tests:
 
         # Run `pytest` in an isolated virtual environment, with the earliest
         # version of Python supported by PyRTL.
-        uv run --python=3.9 --isolated pytest -n auto
+        uv run --python=3.10 --isolated pytest -n auto
 
         # Run `ruff format` to check that code is formatted properly.
         #

pyproject.toml

@@ -23,7 +23,7 @@ authors = [
 description = "RTL-level Hardware Design and Simulation Toolkit"
 readme = "README.md"
 license = {file = "LICENSE.md"}
-requires-python = ">=3.9"
+requires-python = ">=3.10"
 classifiers = [
     "Development Status :: 4 - Beta",
     "Environment :: Console",

pyrtl/analysis.py

@@ -12,8 +12,7 @@
 import subprocess
 import sys
 import tempfile
-from collections.abc import Iterable
-from typing import Callable
+from collections.abc import Callable, Iterable
 
 from pyrtl.core import Block, LogicNet, working_block
 from pyrtl.helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex

pyrtl/helperfuncs.py

@@ -493,7 +493,7 @@ def fn(n):
             msg = f"bitpattern field {exc.args[0]} was not provided in named_field list"
             raise PyrtlError(msg) from exc
 
-    fmap = dict(zip(lifo, intfields))
+    fmap = dict(zip(lifo, intfields, strict=True))
     for c in bitpattern[::-1]:
         if c == "0" or c == "1":
             bitlist.append(c)
@@ -582,7 +582,7 @@ def chop(w: WireVector, *segment_widths: int) -> list[WireVector]:
     n_segments = len(segment_widths)
     starts = [sum(segment_widths[i + 1 :]) for i in range(n_segments)]
     ends = [sum(segment_widths[i:]) for i in range(n_segments)]
-    return [w[s:e] for s, e in zip(starts, ends)]
+    return [w[s:e] for s, e in zip(starts, ends, strict=True)]
 
 
 def input_list(
@@ -706,7 +706,7 @@ def wirevector_list(
         )
 
     wirelist = []
-    for fullname, bw in zip(names, bitwidth):
+    for fullname, bw in zip(names, bitwidth, strict=True):
         try:
             name, bw = fullname.split("/")
         except ValueError:

pyrtl/memory.py

@@ -19,8 +19,8 @@
 import collections
 import numbers
 import types
-from collections.abc import Sequence
-from typing import Callable, NamedTuple
+from collections.abc import Callable, Sequence
+from typing import NamedTuple
 
 from pyrtl.core import Block, LogicNet, _NameIndexer, working_block
 from pyrtl.corecircuits import as_wires

pyrtl/rtllib/adders.py

@@ -10,7 +10,7 @@
 
 import itertools
 import math
-from typing import Callable
+from collections.abc import Callable
 
 import pyrtl
 

pyrtl/rtllib/multipliers.py

@@ -9,7 +9,7 @@
 """
 
 import math
-from typing import Callable
+from collections.abc import Callable
 
 import pyrtl
 from pyrtl.rtllib import adders

pyrtl/rtllib/muxes.py

@@ -258,7 +258,7 @@ def _add_signal(self, data_signals):
             )
             raise pyrtl.PyrtlError(msg)
 
-        for dw, sig in zip(self.dest_wires, data_signals):
+        for dw, sig in zip(self.dest_wires, data_signals, strict=True):
             data_signal = pyrtl.as_wires(sig, dw.bitwidth)
             self.dest_instrs_info[dw].append(data_signal)
 
@@ -268,7 +268,7 @@ def finalize(self):
         self._final = True
 
         for dest_w, values in self.dest_instrs_info.items():
-            mux_vals = dict(zip(self.instructions, values))
+            mux_vals = dict(zip(self.instructions, values, strict=False))
             dest_w <<= sparse_mux(self.signal_wire, mux_vals)
 
 

pyrtl/rtllib/testingutils.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 
 import random
-from typing import Callable
+from collections.abc import Callable
 
 import pyrtl
 
@@ -62,7 +62,8 @@ def make_inputs_and_values(
                     random_dist=dist,
                 )
                 for i in range(num_wires)
-            )
+            ),
+            strict=True,
         )
     )
     return wires, vals
@@ -165,7 +166,7 @@ def sim_and_ret_outws(
              :class:`list` of its values in each cycle.
     """
     sim = pyrtl.Simulation()
-    sim.step_multiple(provided_inputs=dict(zip(inwires, invals)))
+    sim.step_multiple(provided_inputs=dict(zip(inwires, invals, strict=True)))
     return sim.tracer.trace