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clk: rockchip: Fix fractional PLL calculation for RK3588
RK3588/RK3576 have several fractional PLLs using a delta-sigma adjustment factor (k) for the fractional component of the PLL output frequency. According to the TRM, the k is a two's complement 16-bit value, not an unsiged integer (see for example the TRM description of CRU_GPLL_CON2, and also a related U-boot fix at [1]). Adjust the code to properly handle negative k values. While at it, also fix the denominator to use the correct value of 65536, not 65535 for the full range of PLL ratios. Cc: stable@vger.kernel.org Fixes: 8f65944 ("clk: rockchip: add pll type for RK3588") Link: https://lore.kernel.org/all/20231012101828.27195-1-zhangqing@rock-chips.com/ [1] Signed-off-by: Alexey Charkov <alchark@flipper.net>
1 parent ad75bcd commit 0634875

2 files changed

Lines changed: 6 additions & 6 deletions

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drivers/clk/rockchip/clk-pll.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include <linux/delay.h>
1414
#include <linux/clk-provider.h>
1515
#include <linux/iopoll.h>
16+
#include <linux/math64.h>
1617
#include <linux/regmap.h>
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#include <linux/clk.h>
1819
#include "clk.h"
@@ -897,7 +898,7 @@ static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
897898
rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK);
898899

899900
pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
900-
rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
901+
rate->k = (s16)((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
901902
}
902903

903904
static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
@@ -913,11 +914,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned
913914

914915
if (cur.k) {
915916
/* fractional mode */
916-
u64 frac_rate64 = prate * cur.k;
917+
s64 frac_rate64 = prate * cur.k;
917918

918-
postdiv = cur.p * 65535;
919-
do_div(frac_rate64, postdiv);
920-
rate64 += frac_rate64;
919+
postdiv = cur.p * 65536ULL;
920+
rate64 += div_s64(frac_rate64, postdiv);
921921
}
922922
rate64 = rate64 >> cur.s;
923923

drivers/clk/rockchip/clk.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -638,7 +638,7 @@ struct rockchip_pll_rate_table {
638638
unsigned int m;
639639
unsigned int p;
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unsigned int s;
641-
unsigned int k;
641+
int k;
642642
};
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};
644644
};

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