clk: rockchip: rk3576: add PLL rates for weird display clocks

Add precomputed PLL parameters for the display clocks found out in the
wild which can't be cleanly derived from the existing PLL rates.

These have been computed in a semi-bruteforce way to solve for low overall
error while preferring smaller integer dividers and multipliers, and
avoiding the fractional delta-sigma K component where possible.

Signed-off-by: Alexey Charkov <alchark@flipper.net>

Author: alchark

drivers/clk/rockchip/clk-rk3576.c

@@ -68,13 +68,16 @@ static struct rockchip_pll_rate_table rk3576_pll_rates[] = {
 	RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
 	RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
 	RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
+	RK3588_PLL_RATE(1478740000, 1, 123, 1, 14964),
 	RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
 	RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
 	RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
 	RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
 	RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
+	RK3588_PLL_RATE(1275830000, 1, 851, 4, -29273),
 	RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
 	RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
+	RK3588_PLL_RATE(1186813000, 1, 791, 4, 13675),
 	RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
 	RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
 	RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
@@ -87,11 +90,43 @@ static struct rockchip_pll_rate_table rk3576_pll_rates[] = {
 	RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
 	RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
 	RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+	RK3588_PLL_RATE(645000000, 1, 215, 3, 0),
 	RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
 	RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
+	RK3588_PLL_RATE(593410000, 1, 791, 5, 13981),
+	RK3588_PLL_RATE(593407000, 7, 173, 0, 5049),
+	RK3588_PLL_RATE(533250000, 4, 355, 2, 32767),
+	RK3588_PLL_RATE(497750000, 3, 124, 1, 28672),
+	RK3588_PLL_RATE(488400000, 5, 407, 2, 0),
 	RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
+	RK3588_PLL_RATE(368881000, 5, 307, 2, 26269),
 	RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
+	RK3588_PLL_RATE(304250000, 4, 811, 4, 10923),
+	RK3588_PLL_RATE(296703000, 5, 989, 4, 655),
+	RK3588_PLL_RATE(296700000, 5, 989, 4, 0),
+	RK3588_PLL_RATE(285500000, 3, 571, 4, 0),
+	RK3588_PLL_RATE(277250000, 3, 69,  1, 20480),
+	RK3588_PLL_RATE(262750000, 4, 701, 4, 10923),
+	RK3588_PLL_RATE(248880000, 1, 166, 4, -5243),
+	RK3588_PLL_RATE(245500000, 3, 491, 4, 0),
+	RK3588_PLL_RATE(241700000, 1, 81,  3, -28399),
+	RK3588_PLL_RATE(241500000, 1, 161, 4, 0),
+	RK3588_PLL_RATE(237600000, 5, 99, 1, 0),
 	RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
+	RK3588_PLL_RATE(193250000, 3, 773, 5, 0),
+	RK3588_PLL_RATE(177500000, 3, 355, 4, 0),
+	RK3588_PLL_RATE(174250000, 3, 87, 2, 8192),
+	RK3588_PLL_RATE(167000000, 3, 167, 3, 0),
+	RK3588_PLL_RATE(163240000, 5, 272, 3, 4369),
+	RK3588_PLL_RATE(148360000, 5, 989, 5, 4369),
+	RK3588_PLL_RATE(148352000, 1, 396, 6, -25865),
+	RK3588_PLL_RATE(147180000, 5, 981, 5, 13107),
+	RK3588_PLL_RATE(146250000, 1, 195, 5, 0),
+	RK3588_PLL_RATE(119000000, 3, 119, 3, 0),
+	RK3588_PLL_RATE(116460000, 1, 156, 5, -23593),
+	RK3588_PLL_RATE(108108000, 3, 865, 6, -8913),
+	RK3588_PLL_RATE(100700000, 2, 537, 6, 4369),
+	RK3588_PLL_RATE(100680000, 5, 671, 5, 13107),
 	RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
 	{ /* sentinel */ },
 };