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hz2hz2
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arm64: dts: rockchip: add camera pipeline nodes to rk3576
Add device tree nodes for the RK3576 camera capture pipeline: - Two Innosilicon CSI D-PHY instances (csi_dphy0, csi_dphy1) - Two MIPI D-PHY GRF syscon nodes (mipidphy0_grf, mipidphy1_grf) - Five MIPI CSI-2 receiver nodes (csi0 through csi4) - Video Capture (VICAP) unit with five MIPI input ports - VICAP IOMMU The CSI hosts are connected to the VICAP ports and wired to the Innosilicon D-PHY instances. All nodes are disabled by default and must be enabled by board device trees that have camera connectors. Signed-off-by: hz2 <hz2@users.noreply.github.com>
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‎arch/arm64/boot/dts/rockchip/rk3576.dtsi‎

Lines changed: 266 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -988,11 +988,22 @@
988988
reg = <0x0 0x26038000 0x0 0x1000>;
989989
};
990990

991+
mipidphy0_grf: syscon@2603a000 {
992+
compatible = "rockchip,rk3576-mipi-dphy-grf", "syscon";
993+
reg = <0x0 0x2603a000 0x0 0x2000>;
994+
clocks = <&cru PCLK_PMUPHY_ROOT>;
995+
};
996+
991997
ioc_grf: syscon@26040000 {
992998
compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
993999
reg = <0x0 0x26040000 0x0 0xc000>;
9941000
};
9951001

1002+
mipidphy1_grf: syscon@2604c000 {
1003+
compatible = "rockchip,rk3576-mipi-dphy-grf", "syscon";
1004+
reg = <0x0 0x2604c000 0x0 0x2000>;
1005+
};
1006+
9961007
cru: clock-controller@27200000 {
9971008
compatible = "rockchip,rk3576-cru";
9981009
reg = <0x0 0x27200000 0x0 0x50000>;
@@ -1355,6 +1366,235 @@
13551366
#iommu-cells = <0>;
13561367
};
13571368

1369+
vicap: video-capture@27c10000 {
1370+
compatible = "rockchip,rk3576-vicap";
1371+
reg = <0x0 0x27c10000 0x0 0x800>;
1372+
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
1373+
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
1374+
<&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>,
1375+
<&cru ICLK_CSIHOST01>;
1376+
clock-names = "aclk", "hclk", "dclk", "iclk_host0", "iclk_host1";
1377+
iommus = <&vicap_mmu>;
1378+
power-domains = <&power RK3576_PD_VI>;
1379+
resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
1380+
<&cru SRST_D_VICAP>, <&cru SRST_VICAP_I0CLK>,
1381+
<&cru SRST_VICAP_I1CLK>, <&cru SRST_VICAP_I2CLK>,
1382+
<&cru SRST_VICAP_I3CLK>, <&cru SRST_VICAP_I4CLK>;
1383+
status = "disabled";
1384+
1385+
ports {
1386+
#address-cells = <1>;
1387+
#size-cells = <0>;
1388+
1389+
vicap_mipi0: port@1 {
1390+
reg = <1>;
1391+
1392+
vicap_mipi0_input: endpoint {
1393+
remote-endpoint = <&csi0_output>;
1394+
};
1395+
};
1396+
1397+
vicap_mipi1: port@2 {
1398+
reg = <2>;
1399+
1400+
vicap_mipi1_input: endpoint {
1401+
remote-endpoint = <&csi1_output>;
1402+
};
1403+
};
1404+
1405+
vicap_mipi2: port@3 {
1406+
reg = <3>;
1407+
1408+
vicap_mipi2_input: endpoint {
1409+
remote-endpoint = <&csi2_output>;
1410+
};
1411+
};
1412+
1413+
vicap_mipi3: port@4 {
1414+
reg = <4>;
1415+
1416+
vicap_mipi3_input: endpoint {
1417+
remote-endpoint = <&csi3_output>;
1418+
};
1419+
};
1420+
1421+
vicap_mipi4: port@5 {
1422+
reg = <5>;
1423+
1424+
vicap_mipi4_input: endpoint {
1425+
remote-endpoint = <&csi4_output>;
1426+
};
1427+
};
1428+
};
1429+
};
1430+
1431+
vicap_mmu: iommu@27c10800 {
1432+
compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
1433+
reg = <0x0 0x27c10800 0x0 0x100>;
1434+
interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1435+
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
1436+
clock-names = "aclk", "iface";
1437+
power-domains = <&power RK3576_PD_VI>;
1438+
rockchip,disable-mmu-reset;
1439+
#iommu-cells = <0>;
1440+
status = "disabled";
1441+
};
1442+
1443+
csi0: csi@27c80000 {
1444+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1445+
reg = <0x0 0x27c80000 0x0 0x10000>;
1446+
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1447+
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
1448+
interrupt-names = "err1", "err2";
1449+
clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>;
1450+
clock-names = "pclk", "iclk";
1451+
phys = <&csi_dphy0>;
1452+
power-domains = <&power RK3576_PD_VI>;
1453+
resets = <&cru SRST_P_CSI_HOST_0>;
1454+
status = "disabled";
1455+
1456+
ports {
1457+
#address-cells = <1>;
1458+
#size-cells = <0>;
1459+
1460+
csi0_in: port@0 {
1461+
reg = <0>;
1462+
};
1463+
1464+
csi0_out: port@1 {
1465+
reg = <1>;
1466+
1467+
csi0_output: endpoint {
1468+
remote-endpoint = <&vicap_mipi0_input>;
1469+
};
1470+
};
1471+
};
1472+
};
1473+
1474+
csi1: csi@27c90000 {
1475+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1476+
reg = <0x0 0x27c90000 0x0 0x10000>;
1477+
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1478+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
1479+
interrupt-names = "err1", "err2";
1480+
clocks = <&cru PCLK_CSI_HOST_1>;
1481+
clock-names = "pclk";
1482+
phys = <&csi_dphy0>;
1483+
power-domains = <&power RK3576_PD_VI>;
1484+
resets = <&cru SRST_P_CSI_HOST_1>;
1485+
status = "disabled";
1486+
1487+
ports {
1488+
#address-cells = <1>;
1489+
#size-cells = <0>;
1490+
1491+
csi1_in: port@0 {
1492+
reg = <0>;
1493+
};
1494+
1495+
csi1_out: port@1 {
1496+
reg = <1>;
1497+
1498+
csi1_output: endpoint {
1499+
remote-endpoint = <&vicap_mipi1_input>;
1500+
};
1501+
};
1502+
};
1503+
};
1504+
1505+
csi2: csi@27ca0000 {
1506+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1507+
reg = <0x0 0x27ca0000 0x0 0x10000>;
1508+
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1509+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
1510+
interrupt-names = "err1", "err2";
1511+
clocks = <&cru PCLK_CSI_HOST_2>;
1512+
clock-names = "pclk";
1513+
phys = <&csi_dphy1>;
1514+
power-domains = <&power RK3576_PD_VI>;
1515+
resets = <&cru SRST_P_CSI_HOST_2>;
1516+
status = "disabled";
1517+
1518+
ports {
1519+
#address-cells = <1>;
1520+
#size-cells = <0>;
1521+
1522+
csi2_in: port@0 {
1523+
reg = <0>;
1524+
};
1525+
1526+
csi2_out: port@1 {
1527+
reg = <1>;
1528+
1529+
csi2_output: endpoint {
1530+
remote-endpoint = <&vicap_mipi2_input>;
1531+
};
1532+
};
1533+
};
1534+
};
1535+
1536+
csi3: csi@27cb0000 {
1537+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1538+
reg = <0x0 0x27cb0000 0x0 0x10000>;
1539+
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
1540+
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1541+
interrupt-names = "err1", "err2";
1542+
clocks = <&cru PCLK_CSI_HOST_3>;
1543+
clock-names = "pclk";
1544+
phys = <&csi_dphy1>;
1545+
power-domains = <&power RK3576_PD_VI>;
1546+
resets = <&cru SRST_P_CSI_HOST_3>;
1547+
status = "disabled";
1548+
1549+
ports {
1550+
#address-cells = <1>;
1551+
#size-cells = <0>;
1552+
1553+
csi3_in: port@0 {
1554+
reg = <0>;
1555+
};
1556+
1557+
csi3_out: port@1 {
1558+
reg = <1>;
1559+
1560+
csi3_output: endpoint {
1561+
remote-endpoint = <&vicap_mipi3_input>;
1562+
};
1563+
};
1564+
};
1565+
};
1566+
1567+
csi4: csi@27cc0000 {
1568+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1569+
reg = <0x0 0x27cc0000 0x0 0x10000>;
1570+
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
1571+
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
1572+
interrupt-names = "err1", "err2";
1573+
clocks = <&cru PCLK_CSI_HOST_4>;
1574+
clock-names = "pclk";
1575+
phys = <&csi_dphy1>;
1576+
power-domains = <&power RK3576_PD_VI>;
1577+
resets = <&cru SRST_P_CSI_HOST_4>;
1578+
status = "disabled";
1579+
1580+
ports {
1581+
#address-cells = <1>;
1582+
#size-cells = <0>;
1583+
1584+
csi4_in: port@0 {
1585+
reg = <0>;
1586+
};
1587+
1588+
csi4_out: port@1 {
1589+
reg = <1>;
1590+
1591+
csi4_output: endpoint {
1592+
remote-endpoint = <&vicap_mipi4_input>;
1593+
};
1594+
};
1595+
};
1596+
};
1597+
13581598
vop: vop@27d00000 {
13591599
compatible = "rockchip,rk3576-vop";
13601600
reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
@@ -2974,6 +3214,19 @@
29743214
status = "disabled";
29753215
};
29763216

3217+
csi_dphy0: phy@2b030000 {
3218+
compatible = "rockchip,rk3576-csi-dphy";
3219+
reg = <0x0 0x2b030000 0x0 0x8000>;
3220+
clocks = <&cru PCLK_CSIDPHY>;
3221+
clock-names = "pclk";
3222+
#phy-cells = <0>;
3223+
power-domains = <&power RK3576_PD_VI>;
3224+
resets = <&cru SRST_P_CSIPHY>, <&cru SRST_SCAN_CSIPHY>;
3225+
reset-names = "apb", "phy";
3226+
rockchip,grf = <&mipidphy0_grf>;
3227+
status = "disabled";
3228+
};
3229+
29773230
combphy0_ps: phy@2b050000 {
29783231
compatible = "rockchip,rk3576-naneng-combphy";
29793232
reg = <0x0 0x2b050000 0x0 0x100>;
@@ -3010,6 +3263,19 @@
30103263
status = "disabled";
30113264
};
30123265

3266+
csi_dphy1: phy@2b070000 {
3267+
compatible = "rockchip,rk3576-csi-dphy";
3268+
reg = <0x0 0x2b070000 0x0 0x8000>;
3269+
clocks = <&cru PCLK_CSIDPHY1>;
3270+
clock-names = "pclk";
3271+
#phy-cells = <0>;
3272+
power-domains = <&power RK3576_PD_VI>;
3273+
resets = <&cru SRST_P_CSIDPHY1>, <&cru SRST_SCAN_CSIDPHY1>;
3274+
reset-names = "apb", "phy";
3275+
rockchip,grf = <&mipidphy1_grf>;
3276+
status = "disabled";
3277+
};
3278+
30133279
usbdp_phy: phy@2b010000 {
30143280
compatible = "rockchip,rk3576-usbdp-phy";
30153281
reg = <0x0 0x2b010000 0x0 0x10000>;

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