arm64: dts: rockchip: rk3576: assign dclk_vp{0,1}_src to VPLL

Reparent dclk_vp{0,1}_src from GPLL to VPLL on Rockchip RK3576. VPLL is a
programmable PLL with no other consumers, allowing the CCF to synthesize
accurate pixel clocks for the two display outputs with arbitrary modes,
as long as only one of them is active at a time (or using the HDMI PHY
as the clock source, which works for HDMI modes up to 4K@60Hz).

This gives much greater flexibility for display modes as compared to the
boot-time default of using GPLL, which is effectively fixed at 1188 MHz
due to a large number of system components depending on it and making
runtime rate changes unrealistic.

Signed-off-by: Alexey Charkov <alchark@flipper.net>

Author: alchark

arch/arm64/boot/dts/rockchip/rk3576.dtsi

@@ -1379,6 +1379,8 @@
 				      "dclk_vp1",
 				      "dclk_vp2",
 				      "pll_hdmiphy0";
+			assigned-clocks = <&cru DCLK_VP0_SRC>, <&cru DCLK_VP1_SRC>;
+			assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_VPLL>;
 			iommus = <&vop_mmu>;
 			power-domains = <&power RK3576_PD_VOP>;
 			rockchip,grf = <&sys_grf>;