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arm64: dts: rockchip: add camera pipeline nodes to rk3576
Add device tree nodes for the RK3576 camera capture pipeline: - Two Innosilicon CSI D-PHY instances (csi_dphy0, csi_dphy1) - Two MIPI D-PHY GRF syscon nodes (mipidphy0_grf, mipidphy1_grf) - Five MIPI CSI-2 receiver nodes (csi0 through csi4) - Video Capture (VICAP) unit with five MIPI input ports - VICAP IOMMU The CSI hosts are connected to the VICAP ports and wired to the Innosilicon D-PHY instances. All nodes are disabled by default and must be enabled by board device trees that have camera connectors. Signed-off-by: Jason Devers <dev.json2@gmail.com>
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‎arch/arm64/boot/dts/rockchip/rk3576.dtsi‎

Lines changed: 265 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -988,11 +988,21 @@
988988
reg = <0x0 0x26038000 0x0 0x1000>;
989989
};
990990

991+
mipidphy0_grf: syscon@2603a000 {
992+
compatible = "rockchip,rk3576-csidphy-grf", "syscon";
993+
reg = <0x0 0x2603a000 0x0 0x2000>;
994+
};
995+
991996
ioc_grf: syscon@26040000 {
992997
compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
993998
reg = <0x0 0x26040000 0x0 0xc000>;
994999
};
9951000

1001+
mipidphy1_grf: syscon@2604c000 {
1002+
compatible = "rockchip,rk3576-csidphy-grf", "syscon";
1003+
reg = <0x0 0x2604c000 0x0 0x2000>;
1004+
};
1005+
9961006
cru: clock-controller@27200000 {
9971007
compatible = "rockchip,rk3576-cru";
9981008
reg = <0x0 0x27200000 0x0 0x50000>;
@@ -1355,6 +1365,235 @@
13551365
#iommu-cells = <0>;
13561366
};
13571367

1368+
vicap: video-capture@27c10000 {
1369+
compatible = "rockchip,rk3576-vicap";
1370+
reg = <0x0 0x27c10000 0x0 0x800>;
1371+
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
1372+
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
1373+
<&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>,
1374+
<&cru ICLK_CSIHOST01>;
1375+
clock-names = "aclk", "hclk", "dclk", "iclk_host0", "iclk_host1";
1376+
iommus = <&vicap_mmu>;
1377+
power-domains = <&power RK3576_PD_VI>;
1378+
resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
1379+
<&cru SRST_D_VICAP>, <&cru SRST_VICAP_I0CLK>,
1380+
<&cru SRST_VICAP_I1CLK>, <&cru SRST_VICAP_I2CLK>,
1381+
<&cru SRST_VICAP_I3CLK>, <&cru SRST_VICAP_I4CLK>;
1382+
status = "disabled";
1383+
1384+
ports {
1385+
#address-cells = <1>;
1386+
#size-cells = <0>;
1387+
1388+
vicap_mipi0: port@1 {
1389+
reg = <1>;
1390+
1391+
vicap_mipi0_input: endpoint {
1392+
remote-endpoint = <&csi0_output>;
1393+
};
1394+
};
1395+
1396+
vicap_mipi1: port@2 {
1397+
reg = <2>;
1398+
1399+
vicap_mipi1_input: endpoint {
1400+
remote-endpoint = <&csi1_output>;
1401+
};
1402+
};
1403+
1404+
vicap_mipi2: port@3 {
1405+
reg = <3>;
1406+
1407+
vicap_mipi2_input: endpoint {
1408+
remote-endpoint = <&csi2_output>;
1409+
};
1410+
};
1411+
1412+
vicap_mipi3: port@4 {
1413+
reg = <4>;
1414+
1415+
vicap_mipi3_input: endpoint {
1416+
remote-endpoint = <&csi3_output>;
1417+
};
1418+
};
1419+
1420+
vicap_mipi4: port@5 {
1421+
reg = <5>;
1422+
1423+
vicap_mipi4_input: endpoint {
1424+
remote-endpoint = <&csi4_output>;
1425+
};
1426+
};
1427+
};
1428+
};
1429+
1430+
vicap_mmu: iommu@27c10800 {
1431+
compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
1432+
reg = <0x0 0x27c10800 0x0 0x100>;
1433+
interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1434+
clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
1435+
clock-names = "aclk", "iface";
1436+
power-domains = <&power RK3576_PD_VI>;
1437+
rockchip,disable-mmu-reset;
1438+
#iommu-cells = <0>;
1439+
status = "disabled";
1440+
};
1441+
1442+
csi0: csi@27c80000 {
1443+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1444+
reg = <0x0 0x27c80000 0x0 0x10000>;
1445+
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1446+
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
1447+
interrupt-names = "err1", "err2";
1448+
clocks = <&cru PCLK_CSI_HOST_0>, <&cru ICLK_CSIHOST0>;
1449+
clock-names = "per", "pixel";
1450+
phys = <&csi_dphy0>;
1451+
power-domains = <&power RK3576_PD_VI>;
1452+
resets = <&cru SRST_P_CSI_HOST_0>;
1453+
status = "disabled";
1454+
1455+
ports {
1456+
#address-cells = <1>;
1457+
#size-cells = <0>;
1458+
1459+
csi0_in: port@0 {
1460+
reg = <0>;
1461+
};
1462+
1463+
csi0_out: port@1 {
1464+
reg = <1>;
1465+
1466+
csi0_output: endpoint {
1467+
remote-endpoint = <&vicap_mipi0_input>;
1468+
};
1469+
};
1470+
};
1471+
};
1472+
1473+
csi1: csi@27c90000 {
1474+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1475+
reg = <0x0 0x27c90000 0x0 0x10000>;
1476+
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1477+
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
1478+
interrupt-names = "err1", "err2";
1479+
clocks = <&cru PCLK_CSI_HOST_1>;
1480+
clock-names = "per";
1481+
phys = <&csi_dphy0>;
1482+
power-domains = <&power RK3576_PD_VI>;
1483+
resets = <&cru SRST_P_CSI_HOST_1>;
1484+
status = "disabled";
1485+
1486+
ports {
1487+
#address-cells = <1>;
1488+
#size-cells = <0>;
1489+
1490+
csi1_in: port@0 {
1491+
reg = <0>;
1492+
};
1493+
1494+
csi1_out: port@1 {
1495+
reg = <1>;
1496+
1497+
csi1_output: endpoint {
1498+
remote-endpoint = <&vicap_mipi1_input>;
1499+
};
1500+
};
1501+
};
1502+
};
1503+
1504+
csi2: csi@27ca0000 {
1505+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1506+
reg = <0x0 0x27ca0000 0x0 0x10000>;
1507+
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1508+
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
1509+
interrupt-names = "err1", "err2";
1510+
clocks = <&cru PCLK_CSI_HOST_2>;
1511+
clock-names = "per";
1512+
phys = <&csi_dphy1>;
1513+
power-domains = <&power RK3576_PD_VI>;
1514+
resets = <&cru SRST_P_CSI_HOST_2>;
1515+
status = "disabled";
1516+
1517+
ports {
1518+
#address-cells = <1>;
1519+
#size-cells = <0>;
1520+
1521+
csi2_in: port@0 {
1522+
reg = <0>;
1523+
};
1524+
1525+
csi2_out: port@1 {
1526+
reg = <1>;
1527+
1528+
csi2_output: endpoint {
1529+
remote-endpoint = <&vicap_mipi2_input>;
1530+
};
1531+
};
1532+
};
1533+
};
1534+
1535+
csi3: csi@27cb0000 {
1536+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1537+
reg = <0x0 0x27cb0000 0x0 0x10000>;
1538+
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
1539+
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1540+
interrupt-names = "err1", "err2";
1541+
clocks = <&cru PCLK_CSI_HOST_3>;
1542+
clock-names = "per";
1543+
phys = <&csi_dphy1>;
1544+
power-domains = <&power RK3576_PD_VI>;
1545+
resets = <&cru SRST_P_CSI_HOST_3>;
1546+
status = "disabled";
1547+
1548+
ports {
1549+
#address-cells = <1>;
1550+
#size-cells = <0>;
1551+
1552+
csi3_in: port@0 {
1553+
reg = <0>;
1554+
};
1555+
1556+
csi3_out: port@1 {
1557+
reg = <1>;
1558+
1559+
csi3_output: endpoint {
1560+
remote-endpoint = <&vicap_mipi3_input>;
1561+
};
1562+
};
1563+
};
1564+
};
1565+
1566+
csi4: csi@27cc0000 {
1567+
compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
1568+
reg = <0x0 0x27cc0000 0x0 0x10000>;
1569+
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
1570+
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
1571+
interrupt-names = "err1", "err2";
1572+
clocks = <&cru PCLK_CSI_HOST_4>;
1573+
clock-names = "per";
1574+
phys = <&csi_dphy1>;
1575+
power-domains = <&power RK3576_PD_VI>;
1576+
resets = <&cru SRST_P_CSI_HOST_4>;
1577+
status = "disabled";
1578+
1579+
ports {
1580+
#address-cells = <1>;
1581+
#size-cells = <0>;
1582+
1583+
csi4_in: port@0 {
1584+
reg = <0>;
1585+
};
1586+
1587+
csi4_out: port@1 {
1588+
reg = <1>;
1589+
1590+
csi4_output: endpoint {
1591+
remote-endpoint = <&vicap_mipi4_input>;
1592+
};
1593+
};
1594+
};
1595+
};
1596+
13581597
vop: vop@27d00000 {
13591598
compatible = "rockchip,rk3576-vop";
13601599
reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
@@ -2974,6 +3213,19 @@
29743213
status = "disabled";
29753214
};
29763215

3216+
csi_dphy0: phy@2b030000 {
3217+
compatible = "rockchip,rk3576-csi-dphy";
3218+
reg = <0x0 0x2b030000 0x0 0x8000>;
3219+
clocks = <&cru PCLK_CSIDPHY>;
3220+
clock-names = "pclk";
3221+
#phy-cells = <0>;
3222+
power-domains = <&power RK3576_PD_VI>;
3223+
resets = <&cru SRST_P_CSIPHY>, <&cru SRST_SCAN_CSIPHY>;
3224+
reset-names = "apb", "phy";
3225+
rockchip,grf = <&mipidphy0_grf>;
3226+
status = "disabled";
3227+
};
3228+
29773229
combphy0_ps: phy@2b050000 {
29783230
compatible = "rockchip,rk3576-naneng-combphy";
29793231
reg = <0x0 0x2b050000 0x0 0x100>;
@@ -3010,6 +3262,19 @@
30103262
status = "disabled";
30113263
};
30123264

3265+
csi_dphy1: phy@2b070000 {
3266+
compatible = "rockchip,rk3576-csi-dphy";
3267+
reg = <0x0 0x2b070000 0x0 0x8000>;
3268+
clocks = <&cru PCLK_CSIDPHY1>;
3269+
clock-names = "pclk";
3270+
#phy-cells = <0>;
3271+
power-domains = <&power RK3576_PD_VI>;
3272+
resets = <&cru SRST_P_CSIDPHY1>, <&cru SRST_SCAN_CSIDPHY1>;
3273+
reset-names = "apb", "phy";
3274+
rockchip,grf = <&mipidphy1_grf>;
3275+
status = "disabled";
3276+
};
3277+
30133278
usbdp_phy: phy@2b010000 {
30143279
compatible = "rockchip,rk3576-usbdp-phy";
30153280
reg = <0x0 0x2b010000 0x0 0x10000>;

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