clk: rockchip: rk3576: allow dclk_vp{0,1}_src to propagate rate to parent PLL

dclk_vp{0,1}_src muxes feed the display clock for Video Ports 0 and 1.
With CLK_SET_RATE_NO_REPARENT the mux is locked to its current parent, but
without CLK_SET_RATE_PARENT rate requests stop at the integer divider and
never reach the parent PLL, making it impossible to achieve certain pixel
clock frequencies.

Add CLK_SET_RATE_PARENT so that when dclk_vp{0,1}_src is reparented to a
programmable PLL (e.g. VPLL via assigned-clock-parents), the CCF divider
can ask the PLL to retune, utilizing its fractional capabilities to
obtain the exact pixel clock.

This flag relies on reparenting the VP0-1 source clock to VPLL at DT level
to ensure no consumer calls clk_set_rate on dclk_vp{0,1} while its parent
is set to the boot-time default of GPLL, which may skew clocks for other
consumers.

Signed-off-by: Alexey Charkov <alchark@flipper.net>

Author: alchark

drivers/clk/rockchip/clk-rk3576.c

@@ -1137,10 +1137,10 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
 			RK3576_CLKGATE_CON(61), 8, GFLAGS),
 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
 			RK3576_CLKGATE_CON(61), 9, GFLAGS),
-	COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
 			RK3576_CLKSEL_CON(145), 8, 3, MFLAGS, 0, 8, DFLAGS,
 			RK3576_CLKGATE_CON(61), 10, GFLAGS),
-	COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
 			RK3576_CLKSEL_CON(146), 8, 3, MFLAGS, 0, 8, DFLAGS,
 			RK3576_CLKGATE_CON(61), 11, GFLAGS),
 	COMPOSITE(DCLK_VP2_SRC, "dclk_vp2_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,