ADC_CMP_IRQHandler ⇒ ADC_CMP_IRQHandler
+
+
+
+Function Pointers
+
+ - ADC_CMP_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- BusFault_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN0_RX0_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN0_RX1_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN0_SCE_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN0_TX_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN1_RX0_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CAN1_TX_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- CEC_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- DMA_Channel0_IRQHandler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- DMA_Channel1_2_IRQHandler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- DMA_Channel3_4_IRQHandler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- DMA_Channel5_6_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- DebugMon_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- EXTI0_1_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- EXTI2_3_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- EXTI4_15_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- FMC_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- HardFault_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- I2C0_ER_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- I2C0_EV_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- I2C1_ER_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- I2C1_EV_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- I2C2_ER_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- I2C2_EV_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- LVD_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- MemManage_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- NMI_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- PendSV_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- RCU_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- RTC_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- Reset_Handler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SLCD_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SPI0_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SPI1_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SPI2_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SVC_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SysTick_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- SystemInit from system_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(.text)
+
- TIMER0_BRK_UP_TRG_COM_IRQHandler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER0_Channel_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER13_IRQHandler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER14_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER15_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER16_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER1_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER2_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TIMER5_DAC_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- TSI_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- USART0_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- USART1_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- USBDWakeUp_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- USBD_HP_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- USBD_LP_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- UsageFault_Handler from it.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- WWDGT_IRQHandler from startup_gd32f1x0.o(.text) referenced from startup_gd32f1x0.o(RESET)
+
- __main from __main.o(!!!main) referenced from startup_gd32f1x0.o(.text)
+
+
+
+Global Symbols
+
+__main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main))
+
[Calls]
- >> __scatterload
+
- >> __rt_entry
+
+
+__scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter))
+
[Called By]
+
+__scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
[Calls]
+
+__scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
+
__scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
+
__scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
+
[Calls]
+
[Called By]
+
+__scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
+
+
__rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
+
[Called By]
+
+__rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
+
+
__rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
+
+
__rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
+
+
__rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
+
+
__rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
+
+
__rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
+
+
__rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002))
+
+
__rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
+
+
__rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
+
+
__rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
+
+
__rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
+
+
__rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
+
+
__rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
+
+
__rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
+
+
__rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
+
+
__rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
+
+
__rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
+
+
__rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
+
+
__rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
+
+
__rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
+
+
__rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
+
+
__rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
+
[Called By]
+
+__rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
+
+
__rt_lib_shutdown_fini_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
+
+
__rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009))
+
+
__rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000011))
+
+
__rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000012))
+
+
__rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
+
+
__rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006))
+
+
__rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E))
+
+
__rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
+
[Called By]
- >> __scatterload_rt2
+
- >> __main
+
+
+__rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
+
+
__rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap
+
+
[Calls]- >> __user_setup_stackheap
+
+
+__rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A))
+
[Calls]
+
+__rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
+
+
__rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
+
[Stack]
- Max Depth = 160 + Unknown Stack Size
+
- Call Chain = __rt_entry_main ⇒ main ⇒ USART_Steer_COM_init ⇒ usart_baudrate_set ⇒ rcu_clock_freq_get
+
+
[Calls]
+
+__rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
+
+
__rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
+
[Called By]
+
+__rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003))
+
[Calls]
+
+__rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
+
+
__rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
+
[Calls]
+
+ShutOff (Thumb, 92 bytes, Stack size 0 bytes, main.o(.text))
+
[Stack]
- Max Depth = 80
- Call Chain = ShutOff ⇒ SendHUGSReply ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> usart_deinit
+
- >> gpio_bit_write
+
- >> fwdgt_counter_reload
+
- >> SetPWM
+
- >> SetEnable
+
- >> SendHUGSReply
+
- >> SendHUGSCmd
+
- >> Delay
+
+
[Called By]
+
+ShowBatteryState (Thumb, 78 bytes, Stack size 8 bytes, main.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = ShowBatteryState
+
+
[Calls]
+
[Called By]
+
+main (Thumb, 382 bytes, Stack size 0 bytes, main.o(.text))
+
[Stack]
- Max Depth = 160
- Call Chain = main ⇒ USART_Steer_COM_init ⇒ usart_baudrate_set ⇒ rcu_clock_freq_get
+
+
[Calls]- >> gpio_input_bit_get
+
- >> gpio_bit_write
+
- >> fwdgt_counter_reload
+
- >> Watchdog_init
+
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> TimeoutTimer_init
+
- >> SystemCoreClockUpdate
+
- >> PWM_init
+
- >> Interrupt_init
+
- >> GPIO_init
+
- >> Delay
+
- >> ADC_init
+
- >> ShowBatteryState
+
- >> ShutOff
+
+
[Called By]
+
+resetInactivityTimer (Thumb, 8 bytes, Stack size 0 bytes, main.o(.text))
+
[Called By]
- >> SetPower
+
- >> SetSpeed
+
+
+SetEnable (Thumb, 20 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
- >> CheckUSARTHUGSInput
+
- >> CheckUSARTSteerInput
+
- >> ShutOff
+
+
+abs16 (Thumb, 10 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
- >> CheckUSARTSteerInput
+
- >> SetPower
+
- >> SetSpeed
+
+
+SetSpeed (Thumb, 172 bytes, Stack size 8 bytes, bldc.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = SetSpeed
+
+
[Calls]- >> abs16
+
- >> resetInactivityTimer
+
+
[Called By]- >> CheckUSARTHUGSInput
+
- >> CheckUSARTSteerInput
+
+
+SetPWM (Thumb, 30 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
- >> CalculateBLDC
+
- >> SetPower
+
- >> ShutOff
+
+
+SetPower (Thumb, 46 bytes, Stack size 8 bytes, bldc.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = SetPower
+
+
[Calls]- >> abs16
+
- >> SetPWM
+
- >> resetInactivityTimer
+
+
[Called By]- >> CheckUSARTHUGSInput
+
- >> CheckUSARTSteerInput
+
- >> TIMER13_IRQHandler
+
+
+GetPWM (Thumb, 8 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
+
+GetSpeed (Thumb, 8 bytes, Stack size 0 bytes, bldc.o(.text), UNUSED)
+
+
CalculateSpeed (Thumb, 64 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
+
+GetPosition (Thumb, 26 bytes, Stack size 16 bytes, bldc.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = GetPosition ⇒ __aeabi_fmul
+
+
[Calls]- >> __aeabi_fmul
+
- >> __aeabi_i2f
+
- >> __aeabi_f2iz
+
+
[Called By]
+
+setPhaseAngle (Thumb, 112 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
+
+abs32 (Thumb, 8 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
+
+runPID (Thumb, 194 bytes, Stack size 4 bytes, bldc.o(.text))
+
[Stack]
- Max Depth = 4
- Call Chain = runPID
+
+
[Calls]
+
[Called By]
+
+getTransitionAngle (Thumb, 46 bytes, Stack size 0 bytes, bldc.o(.text))
+
[Called By]
+
+hallToPos (Thumb, 56 bytes, Stack size 24 bytes, bldc.o(.text))
+
[Stack]
- Max Depth = 24
- Call Chain = hallToPos
+
+
[Calls]
+
[Called By]
+
+CalculateBLDC (Thumb, 1150 bytes, Stack size 32 bytes, bldc.o(.text))
+
[Stack]
- Max Depth = 64
- Call Chain = CalculateBLDC ⇒ __aeabi_cdcmple
+
+
[Calls]- >> timer_channel_output_pulse_value_config
+
- >> timer_automatic_output_enable
+
- >> timer_automatic_output_disable
+
- >> blockPWM
+
- >> hallToPos
+
- >> getTransitionAngle
+
- >> runPID
+
- >> setPhaseAngle
+
- >> gpio_bit_write
+
- >> SetPWM
+
- >> __aeabi_cdcmple
+
- >> __aeabi_i2d
+
+
[Called By]- >> DMA_Channel0_IRQHandler
+
+
+Interrupt_init (Thumb, 12 bytes, Stack size 8 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = Interrupt_init
+
+
[Calls]- >> nvic_priority_group_set
+
+
[Called By]
+
+Watchdog_init (Thumb, 54 bytes, Stack size 8 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = Watchdog_init ⇒ fwdgt_config
+
+
[Calls]- >> rcu_flag_get
+
- >> rcu_all_reset_flag_clear
+
- >> fwdgt_window_value_config
+
- >> fwdgt_enable
+
- >> fwdgt_config
+
+
[Called By]
+
+TimeoutTimer_init (Thumb, 80 bytes, Stack size 8 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 28
- Call Chain = TimeoutTimer_init ⇒ nvic_irq_enable
+
+
[Calls]- >> timer_interrupt_enable
+
- >> timer_init
+
- >> timer_enable
+
- >> timer_deinit
+
- >> timer_auto_reload_shadow_disable
+
- >> rcu_periph_clock_enable
+
- >> nvic_irq_enable
+
+
[Called By]
+
+GPIO_init (Thumb, 836 bytes, Stack size 8 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 28
- Call Chain = GPIO_init ⇒ gpio_output_options_set
+
+
[Calls]- >> rcu_periph_clock_enable
+
- >> gpio_output_options_set
+
- >> gpio_mode_set
+
- >> gpio_af_set
+
+
[Called By]
+
+PWM_init (Thumb, 388 bytes, Stack size 8 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 28
- Call Chain = PWM_init ⇒ nvic_irq_enable
+
+
[Calls]- >> timer_interrupt_enable
+
- >> timer_init
+
- >> timer_enable
+
- >> timer_disable
+
- >> timer_deinit
+
- >> timer_channel_output_state_config
+
- >> timer_channel_output_shadow_config
+
- >> timer_channel_output_mode_config
+
- >> timer_channel_output_fast_config
+
- >> timer_channel_output_config
+
- >> timer_channel_complementary_output_state_config
+
- >> timer_break_config
+
- >> timer_auto_reload_shadow_disable
+
- >> rcu_periph_clock_enable
+
- >> nvic_irq_enable
+
- >> timer_channel_output_pulse_value_config
+
+
[Called By]
+
+ADC_init (Thumb, 226 bytes, Stack size 32 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 56
- Call Chain = ADC_init ⇒ dma_init
+
+
[Calls]- >> rcu_periph_clock_enable
+
- >> rcu_adc_clock_config
+
- >> nvic_irq_enable
+
- >> dma_transfer_number_config
+
- >> dma_memory_to_memory_disable
+
- >> dma_interrupt_enable
+
- >> dma_init
+
- >> dma_deinit
+
- >> dma_circulation_enable
+
- >> dma_channel_enable
+
- >> adc_watchdog_disable
+
- >> adc_vbat_disable
+
- >> adc_tempsensor_vrefint_disable
+
- >> adc_special_function_config
+
- >> adc_regular_channel_config
+
- >> adc_external_trigger_source_config
+
- >> adc_external_trigger_config
+
- >> adc_enable
+
- >> adc_dma_mode_enable
+
- >> adc_data_alignment_config
+
- >> adc_channel_length_config
+
- >> adc_calibration_enable
+
- >> __aeabi_memcpy4
+
+
[Called By]
+
+USART_HUGS_init (Thumb, 206 bytes, Stack size 32 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 160
- Call Chain = USART_HUGS_init ⇒ usart_baudrate_set ⇒ rcu_clock_freq_get
+
+
[Calls]- >> usart_word_length_set
+
- >> usart_transmit_config
+
- >> usart_stop_bit_set
+
- >> usart_receive_config
+
- >> usart_parity_config
+
- >> usart_oversample_config
+
- >> usart_enable
+
- >> usart_dma_receive_config
+
- >> usart_baudrate_set
+
- >> rcu_periph_clock_enable
+
- >> nvic_irq_enable
+
- >> dma_transfer_number_config
+
- >> dma_memory_to_memory_disable
+
- >> dma_interrupt_enable
+
- >> dma_init
+
- >> dma_deinit
+
- >> dma_circulation_enable
+
- >> dma_channel_enable
+
- >> __aeabi_memcpy4
+
+
[Called By]
+
+USART_Steer_COM_init (Thumb, 206 bytes, Stack size 32 bytes, setup.o(.text))
+
[Stack]
- Max Depth = 160
- Call Chain = USART_Steer_COM_init ⇒ usart_baudrate_set ⇒ rcu_clock_freq_get
+
+
[Calls]- >> usart_word_length_set
+
- >> usart_transmit_config
+
- >> usart_stop_bit_set
+
- >> usart_receive_config
+
- >> usart_parity_config
+
- >> usart_oversample_config
+
- >> usart_enable
+
- >> usart_dma_receive_config
+
- >> usart_baudrate_set
+
- >> rcu_periph_clock_enable
+
- >> nvic_irq_enable
+
- >> dma_transfer_number_config
+
- >> dma_memory_to_memory_disable
+
- >> dma_interrupt_enable
+
- >> dma_init
+
- >> dma_deinit
+
- >> dma_circulation_enable
+
- >> dma_channel_enable
+
- >> __aeabi_memcpy4
+
+
[Called By]
+
+SysTick_Handler (Thumb, 12 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+ResetTimeout (Thumb, 8 bytes, Stack size 0 bytes, it.o(.text))
+
[Called By]
- >> CheckUSARTHUGSInput
+
- >> CheckUSARTSteerInput
+
+
+TIMER13_IRQHandler (Thumb, 98 bytes, Stack size 8 bytes, it.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = TIMER13_IRQHandler ⇒ SetPower
+
+
[Calls]- >> timer_interrupt_flag_clear
+
- >> CalculateSpeed
+
- >> SetPower
+
+
[Address Reference Count : 1]- startup_gd32f1x0.o(RESET)
+
+TIMER0_BRK_UP_TRG_COM_IRQHandler (Thumb, 18 bytes, Stack size 8 bytes, it.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = TIMER0_BRK_UP_TRG_COM_IRQHandler
+
+
[Calls]- >> timer_interrupt_flag_clear
+
- >> adc_software_trigger_enable
+
+
[Address Reference Count : 1]- startup_gd32f1x0.o(RESET)
+
+DMA_Channel0_IRQHandler (Thumb, 26 bytes, Stack size 8 bytes, it.o(.text))
+
[Stack]
- Max Depth = 72
- Call Chain = DMA_Channel0_IRQHandler ⇒ CalculateBLDC ⇒ __aeabi_cdcmple
+
+
[Calls]- >> dma_interrupt_flag_get
+
- >> dma_interrupt_flag_clear
+
- >> CalculateBLDC
+
+
[Address Reference Count : 1]- startup_gd32f1x0.o(RESET)
+
+DMA_Channel1_2_IRQHandler (Thumb, 26 bytes, Stack size 8 bytes, it.o(.text))
+
[Stack]
- Max Depth = 160
- Call Chain = DMA_Channel1_2_IRQHandler ⇒ UpdateUSARTSteerInput ⇒ CheckUSARTSteerInput ⇒ SendHUGSCmd ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> dma_interrupt_flag_get
+
- >> dma_interrupt_flag_clear
+
- >> UpdateUSARTSteerInput
+
+
[Address Reference Count : 1]- startup_gd32f1x0.o(RESET)
+
+DMA_Channel3_4_IRQHandler (Thumb, 26 bytes, Stack size 8 bytes, it.o(.text))
+
[Stack]
- Max Depth = 128
- Call Chain = DMA_Channel3_4_IRQHandler ⇒ UpdateUSARTHUGSInput ⇒ CheckUSARTHUGSInput ⇒ SendHUGSReply ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> dma_interrupt_flag_get
+
- >> dma_interrupt_flag_clear
+
- >> UpdateUSARTHUGSInput
+
+
[Address Reference Count : 1]- startup_gd32f1x0.o(RESET)
+
+millis (Thumb, 6 bytes, Stack size 0 bytes, it.o(.text), UNUSED)
+
+
Delay (Thumb, 20 bytes, Stack size 0 bytes, it.o(.text))
+
[Called By]
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, it.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+SendBuffer (Thumb, 50 bytes, Stack size 24 bytes, comms.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> usart_flag_get
+
- >> usart_data_transmit
+
+
[Called By]- >> CheckUSARTSteerInput
+
- >> SendHUGSReply
+
- >> SendHUGSCmd
+
+
+CalcCRC (Thumb, 62 bytes, Stack size 12 bytes, comms.o(.text))
+
[Stack]
- Max Depth = 12
- Call Chain = CalcCRC
+
+
[Called By]- >> CheckUSARTHUGSInput
+
- >> CheckUSARTSteerInput
+
- >> SendHUGSReply
+
- >> SendHUGSCmd
+
+
+max (Thumb, 14 bytes, Stack size 0 bytes, commssteering.o(.text))
+
[Called By]
- >> CheckUSARTSteerInput
+
+
+CheckUSARTSteerInput (Thumb, 300 bytes, Stack size 56 bytes, commssteering.o(.text))
+
[Stack]
- Max Depth = 128
- Call Chain = CheckUSARTSteerInput ⇒ SendHUGSCmd ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> SetESTOP
+
- >> max
+
- >> CalcCRC
+
- >> SendBuffer
+
- >> ResetTimeout
+
- >> SetPower
+
- >> SetSpeed
+
- >> abs16
+
- >> SetEnable
+
- >> SendHUGSCmd
+
- >> __aeabi_i2f
+
- >> __aeabi_f2d
+
- >> __aeabi_dmul
+
- >> __aeabi_d2iz
+
+
[Called By]- >> UpdateUSARTSteerInput
+
+
+UpdateUSARTSteerInput (Thumb, 188 bytes, Stack size 24 bytes, commssteering.o(.text))
+
[Stack]
- Max Depth = 152
- Call Chain = UpdateUSARTSteerInput ⇒ CheckUSARTSteerInput ⇒ SendHUGSCmd ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> CheckUSARTSteerInput
+
- >> __aeabi_memcpy
+
+
[Called By]- >> DMA_Channel1_2_IRQHandler
+
+
+SetESTOP (Thumb, 8 bytes, Stack size 0 bytes, commshugs.o(.text))
+
[Called By]
- >> CheckUSARTHUGSInput
+
- >> CheckUSARTSteerInput
+
+
+SendHUGSReply (Thumb, 490 bytes, Stack size 48 bytes, commshugs.o(.text))
+
[Stack]
- Max Depth = 80
- Call Chain = SendHUGSReply ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> CalcCRC
+
- >> SendBuffer
+
- >> GetPosition
+
- >> GetPWM
+
+
[Called By]- >> CheckUSARTHUGSInput
+
- >> ShutOff
+
+
+CheckUSARTHUGSInput (Thumb, 266 bytes, Stack size 16 bytes, commshugs.o(.text))
+
[Stack]
- Max Depth = 96
- Call Chain = CheckUSARTHUGSInput ⇒ SendHUGSReply ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> SetESTOP
+
- >> CalcCRC
+
- >> ResetTimeout
+
- >> SetPower
+
- >> SetSpeed
+
- >> SetEnable
+
- >> SendHUGSReply
+
+
[Called By]- >> UpdateUSARTHUGSInput
+
+
+UpdateUSARTHUGSInput (Thumb, 188 bytes, Stack size 24 bytes, commshugs.o(.text))
+
[Stack]
- Max Depth = 120
- Call Chain = UpdateUSARTHUGSInput ⇒ CheckUSARTHUGSInput ⇒ SendHUGSReply ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> CheckUSARTHUGSInput
+
- >> __aeabi_memcpy
+
+
[Called By]- >> DMA_Channel3_4_IRQHandler
+
+
+SendHUGSCmd (Thumb, 212 bytes, Stack size 40 bytes, commshugs.o(.text))
+
[Stack]
- Max Depth = 72
- Call Chain = SendHUGSCmd ⇒ SendBuffer ⇒ usart_flag_get
+
+
[Calls]- >> CalcCRC
+
- >> SendBuffer
+
+
[Called By]- >> CheckUSARTSteerInput
+
- >> ShutOff
+
+
+adc_deinit (Thumb, 20 bytes, Stack size 8 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
[Calls]
- >> rcu_periph_reset_enable
+
- >> rcu_periph_reset_disable
+
+
+adc_enable (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_disable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_calibration_enable (Thumb, 54 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_dma_mode_enable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_dma_mode_disable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_tempsensor_vrefint_enable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_tempsensor_vrefint_disable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_vbat_enable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_vbat_disable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_discontinuous_mode_config (Thumb, 94 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_special_function_config (Thumb, 130 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_data_alignment_config (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_channel_length_config (Thumb, 88 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_regular_channel_config (Thumb, 218 bytes, Stack size 16 bytes, gd32f1x0_adc.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = adc_regular_channel_config
+
+
[Called By]
+
+adc_inserted_channel_config (Thumb, 146 bytes, Stack size 20 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_inserted_channel_offset_config (Thumb, 42 bytes, Stack size 12 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_external_trigger_config (Thumb, 88 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_external_trigger_source_config (Thumb, 60 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_software_trigger_enable (Thumb, 38 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
- >> TIMER0_BRK_UP_TRG_COM_IRQHandler
+
+
+adc_regular_data_read (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_inserted_data_read (Thumb, 60 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_flag_get (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_flag_clear (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_interrupt_flag_get (Thumb, 108 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_interrupt_flag_clear (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_interrupt_enable (Thumb, 68 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_interrupt_disable (Thumb, 68 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_watchdog_single_channel_enable (Thumb, 40 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_watchdog_group_channel_enable (Thumb, 92 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
adc_watchdog_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text))
+
[Called By]
+
+adc_watchdog_threshold_config (Thumb, 12 bytes, Stack size 0 bytes, gd32f1x0_adc.o(.text), UNUSED)
+
+
dma_deinit (Thumb, 88 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_init (Thumb, 270 bytes, Stack size 24 bytes, gd32f1x0_dma.o(.text))
+
[Stack]
- Max Depth = 24
- Call Chain = dma_init
+
+
[Called By]- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_circulation_enable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_circulation_disable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_memory_to_memory_enable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_memory_to_memory_disable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_channel_enable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_channel_disable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_periph_address_config (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_memory_address_config (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_transfer_number_config (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_transfer_number_get (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_priority_config (Thumb, 34 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_memory_width_config (Thumb, 34 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_periph_width_config (Thumb, 34 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_memory_increase_enable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_memory_increase_disable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_periph_increase_enable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_periph_increase_disable (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_transfer_direction_config (Thumb, 64 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_interrupt_flag_get (Thumb, 196 bytes, Stack size 20 bytes, gd32f1x0_dma.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = dma_interrupt_flag_get
+
+
[Called By]- >> DMA_Channel3_4_IRQHandler
+
- >> DMA_Channel1_2_IRQHandler
+
- >> DMA_Channel0_IRQHandler
+
+
+dma_interrupt_flag_clear (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text))
+
[Called By]
- >> DMA_Channel3_4_IRQHandler
+
- >> DMA_Channel1_2_IRQHandler
+
- >> DMA_Channel0_IRQHandler
+
+
+dma_interrupt_enable (Thumb, 30 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = dma_interrupt_enable
+
+
[Called By]- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
+
+dma_interrupt_disable (Thumb, 30 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_flag_get (Thumb, 26 bytes, Stack size 8 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
dma_flag_clear (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_dma.o(.text), UNUSED)
+
+
fwdgt_write_disable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_fwdgt.o(.text), UNUSED)
+
+
fwdgt_counter_reload (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_fwdgt.o(.text))
+
[Called By]
+
+fwdgt_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_fwdgt.o(.text))
+
[Called By]
+
+fwdgt_window_value_config (Thumb, 54 bytes, Stack size 8 bytes, gd32f1x0_fwdgt.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = fwdgt_window_value_config
+
+
[Called By]
+
+fwdgt_config (Thumb, 94 bytes, Stack size 12 bytes, gd32f1x0_fwdgt.o(.text))
+
[Stack]
- Max Depth = 12
- Call Chain = fwdgt_config
+
+
[Called By]
+
+fwdgt_flag_get (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_fwdgt.o(.text), UNUSED)
+
+
gpio_deinit (Thumb, 140 bytes, Stack size 8 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
[Calls]
- >> rcu_periph_reset_enable
+
- >> rcu_periph_reset_disable
+
+
+gpio_mode_set (Thumb, 78 bytes, Stack size 20 bytes, gd32f1x0_gpio.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = gpio_mode_set
+
+
[Called By]
+
+gpio_output_options_set (Thumb, 66 bytes, Stack size 20 bytes, gd32f1x0_gpio.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = gpio_output_options_set
+
+
[Called By]
+
+gpio_bit_set (Thumb, 4 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
gpio_bit_reset (Thumb, 4 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
gpio_bit_write (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text))
+
[Called By]
- >> CalculateBLDC
+
- >> main
+
- >> ShowBatteryState
+
- >> ShutOff
+
+
+gpio_port_write (Thumb, 4 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
gpio_input_bit_get (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text))
+
[Called By]
+
+gpio_input_port_get (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
gpio_output_bit_get (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
gpio_output_port_get (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
gpio_af_set (Thumb, 94 bytes, Stack size 20 bytes, gd32f1x0_gpio.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = gpio_af_set
+
+
[Called By]
+
+gpio_pin_lock (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_gpio.o(.text), UNUSED)
+
+
nvic_priority_group_set (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_misc.o(.text))
+
[Called By]
+
+nvic_irq_enable (Thumb, 156 bytes, Stack size 20 bytes, gd32f1x0_misc.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = nvic_irq_enable
+
+
[Called By]- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> TimeoutTimer_init
+
- >> PWM_init
+
- >> ADC_init
+
+
+nvic_irq_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_misc.o(.text), UNUSED)
+
+
nvic_vector_table_set (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_misc.o(.text), UNUSED)
+
+
system_lowpower_set (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_misc.o(.text), UNUSED)
+
+
system_lowpower_reset (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_misc.o(.text), UNUSED)
+
+
systick_clksource_set (Thumb, 40 bytes, Stack size 0 bytes, gd32f1x0_misc.o(.text), UNUSED)
+
+
rcu_deinit (Thumb, 112 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_periph_clock_enable (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> TimeoutTimer_init
+
- >> PWM_init
+
- >> GPIO_init
+
- >> ADC_init
+
+
+rcu_periph_clock_disable (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_periph_clock_sleep_enable (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_periph_clock_sleep_disable (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_periph_reset_enable (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text))
+
[Called By]
- >> gpio_deinit
+
- >> adc_deinit
+
- >> timer_deinit
+
- >> usart_deinit
+
+
+rcu_periph_reset_disable (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text))
+
[Called By]
- >> gpio_deinit
+
- >> adc_deinit
+
- >> timer_deinit
+
- >> usart_deinit
+
+
+rcu_bkp_reset_enable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_bkp_reset_disable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_system_clock_source_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_system_clock_source_get (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_ahb_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_apb1_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_apb2_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_adc_clock_config (Thumb, 148 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text))
+
[Called By]
+
+rcu_usbd_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_ckout_config (Thumb, 24 bytes, Stack size 8 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_pll_config (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_usart_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_cec_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_rtc_clock_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_hxtal_prediv_config (Thumb, 20 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_lxtal_drive_capability_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_flag_get (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text))
+
[Called By]
- >> Watchdog_init
+
- >> rcu_osci_stab_wait
+
+
+rcu_all_reset_flag_clear (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text))
+
[Called By]
+
+rcu_interrupt_flag_get (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_interrupt_flag_clear (Thumb, 12 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_interrupt_enable (Thumb, 12 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_interrupt_disable (Thumb, 12 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_osci_stab_wait (Thumb, 284 bytes, Stack size 20 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
[Calls]
+
+rcu_osci_on (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_osci_off (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_osci_bypass_mode_enable (Thumb, 94 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_osci_bypass_mode_disable (Thumb, 94 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_hxtal_clock_monitor_enable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_hxtal_clock_monitor_disable (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_irc8m_adjust_value_set (Thumb, 20 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_irc14m_adjust_value_set (Thumb, 20 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_voltage_key_unlock (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_deepsleep_voltage_set (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_power_down_voltage_set (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_rcu.o(.text), UNUSED)
+
+
rcu_clock_freq_get (Thumb, 690 bytes, Stack size 96 bytes, gd32f1x0_rcu.o(.text))
+
[Stack]
- Max Depth = 96
- Call Chain = rcu_clock_freq_get
+
+
[Called By]
+
+timer_deinit (Thumb, 210 bytes, Stack size 8 bytes, gd32f1x0_timer.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = timer_deinit
+
+
[Calls]- >> rcu_periph_reset_enable
+
- >> rcu_periph_reset_disable
+
+
[Called By]- >> TimeoutTimer_init
+
- >> PWM_init
+
+
+timer_init (Thumb, 126 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
- >> TimeoutTimer_init
+
- >> PWM_init
+
+
+timer_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
- >> TimeoutTimer_init
+
- >> PWM_init
+
+
+timer_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_auto_reload_shadow_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_auto_reload_shadow_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
- >> TimeoutTimer_init
+
- >> PWM_init
+
+
+timer_update_event_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_update_event_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_counter_alignment (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_counter_up_direction (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_counter_down_direction (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_prescaler_config (Thumb, 14 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_repetition_value_config (Thumb, 4 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_autoreload_value_config (Thumb, 4 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_counter_value_config (Thumb, 4 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_counter_read (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_prescaler_read (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_single_pulse_mode_config (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_update_source_config (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_interrupt_enable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
- >> TimeoutTimer_init
+
- >> PWM_init
+
+
+timer_interrupt_disable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_interrupt_flag_get (Thumb, 32 bytes, Stack size 8 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_interrupt_flag_clear (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
- >> TIMER0_BRK_UP_TRG_COM_IRQHandler
+
- >> TIMER13_IRQHandler
+
+
+timer_flag_get (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_flag_clear (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_dma_enable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_dma_disable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_dma_request_source_select (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_dma_transfer_config (Thumb, 24 bytes, Stack size 8 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_event_software_generate (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_break_config (Thumb, 30 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_break_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_break_disable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_automatic_output_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_automatic_output_disable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_primary_output_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_control_shadow_config (Thumb, 22 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_control_shadow_update_config (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_output_config (Thumb, 472 bytes, Stack size 8 bytes, gd32f1x0_timer.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = timer_channel_output_config
+
+
[Called By]
+
+timer_channel_output_mode_config (Thumb, 90 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_channel_output_pulse_value_config (Thumb, 38 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
- >> CalculateBLDC
+
- >> PWM_init
+
+
+timer_channel_output_shadow_config (Thumb, 90 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_channel_output_fast_config (Thumb, 90 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_channel_output_clear_config (Thumb, 90 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_output_polarity_config (Thumb, 92 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_complementary_output_polarity_config (Thumb, 70 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_ocpre_clear_source_config (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_output_state_config (Thumb, 92 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_channel_complementary_output_state_config (Thumb, 70 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text))
+
[Called By]
+
+timer_channel_input_capture_prescaler_config (Thumb, 90 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Called By]
- >> timer_input_pwm_capture_config
+
- >> timer_input_capture_config
+
+
+timer_input_capture_config (Thumb, 332 bytes, Stack size 16 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Calls]
- >> timer_channel_input_capture_prescaler_config
+
+
+timer_channel_capture_value_register_read (Thumb, 42 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_input_pwm_capture_config (Thumb, 352 bytes, Stack size 24 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Calls]
- >> timer_channel_input_capture_prescaler_config
+
+
+timer_hall_mode_config (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_input_trigger_source_select (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Called By]
- >> timer_external_trigger_as_external_clock_config
+
- >> timer_internal_trigger_as_external_clock_config
+
+
+timer_master_output_trigger_source_select (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_slave_mode_select (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_master_slave_mode_config (Thumb, 26 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_external_trigger_config (Thumb, 30 bytes, Stack size 12 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Called By]
- >> timer_external_clock_mode1_config
+
- >> timer_external_clock_mode0_config
+
+
+timer_quadrature_decoder_mode_config (Thumb, 64 bytes, Stack size 12 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_internal_clock_config (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_internal_trigger_as_external_clock_config (Thumb, 32 bytes, Stack size 8 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Calls]
- >> timer_input_trigger_source_select
+
+
+timer_external_trigger_as_external_clock_config (Thumb, 164 bytes, Stack size 16 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Calls]
- >> timer_input_trigger_source_select
+
+
+timer_external_clock_mode0_config (Thumb, 56 bytes, Stack size 20 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Calls]
- >> timer_external_trigger_config
+
+
+timer_external_clock_mode1_config (Thumb, 32 bytes, Stack size 20 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
[Calls]
- >> timer_external_trigger_config
+
+
+timer_external_clock_mode1_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
timer_channel_remap_config (Thumb, 6 bytes, Stack size 0 bytes, gd32f1x0_timer.o(.text), UNUSED)
+
+
usart_deinit (Thumb, 58 bytes, Stack size 8 bytes, gd32f1x0_usart.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = usart_deinit
+
+
[Calls]- >> rcu_periph_reset_enable
+
- >> rcu_periph_reset_disable
+
+
[Called By]
+
+usart_baudrate_set (Thumb, 120 bytes, Stack size 32 bytes, gd32f1x0_usart.o(.text))
+
[Stack]
- Max Depth = 128
- Call Chain = usart_baudrate_set ⇒ rcu_clock_freq_get
+
+
[Calls]
+
[Called By]- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_parity_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_word_length_set (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_stop_bit_set (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_transmit_config (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_receive_config (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_data_transmit (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
+
+usart_data_receive (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_data_first_config (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_invert_config (Thumb, 110 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_overrun_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_overrun_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_oversample_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_sample_bit_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_autobaud_detection_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_autobaud_detection_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_autobaud_detection_mode_config (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_mute_mode_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_mute_mode_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_mute_mode_wakeup_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_address_detection_mode_config (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_address_config (Thumb, 32 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_receiver_timeout_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_receiver_timeout_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_receiver_timeout_config (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_lin_mode_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_lin_mode_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_lin_break_dection_length_config (Thumb, 20 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_halfduplex_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_halfduplex_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_clock_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_clock_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_synchronous_clock_config (Thumb, 50 bytes, Stack size 12 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_smartcard_mode_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_smartcard_mode_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_smartcard_mode_nack_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_smartcard_mode_nack_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_guard_time_config (Thumb, 36 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_block_length_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_smartcard_autoretry_config (Thumb, 32 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_irda_mode_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_irda_mode_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_irda_lowpower_config (Thumb, 20 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_prescaler_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_hardware_flow_rts_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_hardware_flow_cts_config (Thumb, 24 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_rs485_driver_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_rs485_driver_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_driver_assertime_config (Thumb, 32 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_driver_deassertime_config (Thumb, 32 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_depolarity_config (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_dma_receive_config (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text))
+
[Called By]
- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
+
+usart_dma_transmit_config (Thumb, 16 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_reception_error_dma_disable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_reception_error_dma_enable (Thumb, 18 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_wakeup_enable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_wakeup_disable (Thumb, 10 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_wakeup_mode_config (Thumb, 28 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_flag_get (Thumb, 30 bytes, Stack size 8 bytes, gd32f1x0_usart.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = usart_flag_get
+
+
[Called By]
+
+usart_flag_clear (Thumb, 18 bytes, Stack size 8 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_interrupt_enable (Thumb, 26 bytes, Stack size 8 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_interrupt_disable (Thumb, 26 bytes, Stack size 8 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_command_enable (Thumb, 8 bytes, Stack size 0 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_interrupt_flag_get (Thumb, 56 bytes, Stack size 16 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
usart_interrupt_flag_clear (Thumb, 18 bytes, Stack size 8 bytes, gd32f1x0_usart.o(.text), UNUSED)
+
+
Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+ADC_CMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_gd32f1x0.o(RESET)
+
+CAN0_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN0_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN0_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN0_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+DMA_Channel5_6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+EXTI0_1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+EXTI2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+EXTI4_15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+I2C0_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+I2C0_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+LVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+RCU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+SLCD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+SPI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER0_Channel_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER16_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TIMER5_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+TSI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+USART0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+USBDWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+USBD_HP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+USBD_LP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+WWDGT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Address Reference Count : 1]
- startup_gd32f1x0.o(RESET)
+
+__user_initial_stackheap (Thumb, 10 bytes, Stack size 0 bytes, startup_gd32f1x0.o(.text))
+
[Called By]
- >> __user_setup_stackheap
+
+
+SystemInit (Thumb, 118 bytes, Stack size 8 bytes, system_gd32f1x0.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = SystemInit ⇒ system_clock_config
+
+
[Calls]
+
[Address Reference Count : 1]- startup_gd32f1x0.o(.text)
+
+SystemCoreClockUpdate (Thumb, 208 bytes, Stack size 44 bytes, system_gd32f1x0.o(.text))
+
[Stack]
- Max Depth = 44
- Call Chain = SystemCoreClockUpdate
+
+
[Called By]
+
+__aeabi_memcpy (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text))
+
[Called By]
- >> UpdateUSARTSteerInput
+
- >> UpdateUSARTHUGSInput
+
+
+__rt_memcpy (Thumb, 138 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text), UNUSED)
+
[Calls]
+
+_memcpy_lastbytes (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED)
+
+
__aeabi_memcpy4 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = __aeabi_memcpy4
+
+
[Called By]- >> USART_Steer_COM_init
+
- >> USART_HUGS_init
+
- >> ADC_init
+
- >> __rt_memcpy
+
+
+__aeabi_memcpy8 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+
+
__rt_memcpy_w (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+
+
_memcpy_lastbytes_aligned (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED)
+
+
__use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = __user_setup_stackheap
+
+
[Calls]- >> __user_perproc_libspace
+
- >> __user_initial_stackheap
+
+
[Called By]
+
+exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = exit
+
+
[Calls]
+
[Called By]
+
+__user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+
+
__user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
+
[Called By]
- >> __user_setup_stackheap
+
+
+__user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+
+
_sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text))
+
[Called By]
+
+__I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+
+
__use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+
+
__semihosting_library_function (Thumb, 0 bytes, Stack size 12 bytes, indicate_semi.o(.text), UNUSED)
+
+
blockPWM (Thumb, 104 bytes, Stack size 12 bytes, bldc.o(i.blockPWM))
+
[Stack]
- Max Depth = 12
- Call Chain = blockPWM
+
+
[Called By]
+
+__fpl_dcmp_Inf (Thumb, 24 bytes, Stack size 0 bytes, dcmpi.o(x$fpl$dcmpinf), UNUSED)
+
[Called By]
+
+__aeabi_d2iz (Thumb, 0 bytes, Stack size 32 bytes, dfix.o(x$fpl$dfix))
+
[Stack]
- Max Depth = 32
- Call Chain = __aeabi_d2iz
+
+
[Called By]- >> CheckUSARTSteerInput
+
+
+_dfix (Thumb, 94 bytes, Stack size 32 bytes, dfix.o(x$fpl$dfix), UNUSED)
+
[Calls]
+
+__aeabi_i2d (Thumb, 0 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dflt))
+
[Called By]
+
+_dflt (Thumb, 46 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dflt), UNUSED)
+
+
__aeabi_cdcmple (Thumb, 0 bytes, Stack size 32 bytes, dleqf.o(x$fpl$dleqf))
+
[Stack]
- Max Depth = 32
- Call Chain = __aeabi_cdcmple
+
+
[Called By]
+
+_dcmple (Thumb, 120 bytes, Stack size 32 bytes, dleqf.o(x$fpl$dleqf), UNUSED)
+
[Calls]
- >> __fpl_dnaninf
+
- >> __fpl_dcmp_Inf
+
+
+__fpl_dcmple_InfNaN (Thumb, 0 bytes, Stack size unknown bytes, dleqf.o(x$fpl$dleqf), UNUSED)
+
+
__aeabi_dmul (Thumb, 0 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul))
+
[Stack]
- Max Depth = 32
- Call Chain = __aeabi_dmul
+
+
[Called By]- >> CheckUSARTSteerInput
+
+
+_dmul (Thumb, 332 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul), UNUSED)
+
[Calls]
- >> __fpl_dretinf
+
- >> __fpl_dnaninf
+
+
+__fpl_dnaninf (Thumb, 156 bytes, Stack size 16 bytes, dnaninf.o(x$fpl$dnaninf), UNUSED)
+
[Called By]
- >> _dmul
+
- >> _dcmple
+
- >> _dfix
+
+
+__fpl_dretinf (Thumb, 12 bytes, Stack size 0 bytes, dretinf.o(x$fpl$dretinf), UNUSED)
+
[Called By]
+
+__aeabi_f2d (Thumb, 0 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d))
+
[Stack]
- Max Depth = 16
- Call Chain = __aeabi_f2d
+
+
[Called By]- >> CheckUSARTSteerInput
+
+
+_f2d (Thumb, 86 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d), UNUSED)
+
[Calls]
- >> __fpl_fnaninf
+
- >> __fpl_dretinf
+
+
+__aeabi_f2iz (Thumb, 0 bytes, Stack size 16 bytes, ffix.o(x$fpl$ffix))
+
[Stack]
- Max Depth = 16
- Call Chain = __aeabi_f2iz
+
+
[Called By]
+
+_ffix (Thumb, 54 bytes, Stack size 16 bytes, ffix.o(x$fpl$ffix), UNUSED)
+
[Calls]
+
+__aeabi_i2f (Thumb, 0 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$fflt))
+
[Called By]
- >> CheckUSARTSteerInput
+
- >> GetPosition
+
+
+_fflt (Thumb, 48 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$fflt), UNUSED)
+
+
__aeabi_fmul (Thumb, 0 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul))
+
[Stack]
- Max Depth = 16
- Call Chain = __aeabi_fmul
+
+
[Called By]
+
+_fmul (Thumb, 258 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul), UNUSED)
+
[Calls]
- >> __fpl_fretinf
+
- >> __fpl_fnaninf
+
+
+__fpl_fnaninf (Thumb, 140 bytes, Stack size 8 bytes, fnaninf.o(x$fpl$fnaninf), UNUSED)
+
[Called By]
+
+__fpl_fretinf (Thumb, 10 bytes, Stack size 0 bytes, fretinf.o(x$fpl$fretinf), UNUSED)
+
[Called By]
+
+
+Local Symbols
+
+system_clock_72m_hxtal (Thumb, 154 bytes, Stack size 0 bytes, system_gd32f1x0.o(.text))
+
[Called By]
+
+system_clock_config (Thumb, 8 bytes, Stack size 8 bytes, system_gd32f1x0.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = system_clock_config
+
+
[Calls]- >> system_clock_72m_hxtal
+
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/HUGS/Objects/HUGS.lnp b/HUGS/Objects/HUGS.lnp
new file mode 100644
index 00000000..e762f499
--- /dev/null
+++ b/HUGS/Objects/HUGS.lnp
@@ -0,0 +1,29 @@
+--cpu Cortex-M3
+".\objects\main.o"
+".\objects\bldc.o"
+".\objects\setup.o"
+".\objects\it.o"
+".\objects\comms.o"
+".\objects\commssteering.o"
+".\objects\led.o"
+".\objects\commshugs.o"
+".\objects\gd32f1x0_adc.o"
+".\objects\gd32f1x0_dbg.o"
+".\objects\gd32f1x0_dma.o"
+".\objects\gd32f1x0_fwdgt.o"
+".\objects\gd32f1x0_gpio.o"
+".\objects\gd32f1x0_i2c.o"
+".\objects\gd32f1x0_misc.o"
+".\objects\gd32f1x0_opa.o"
+".\objects\gd32f1x0_pmu.o"
+".\objects\gd32f1x0_rcu.o"
+".\objects\gd32f1x0_syscfg.o"
+".\objects\gd32f1x0_timer.o"
+".\objects\gd32f1x0_usart.o"
+".\objects\gd32f1x0_wwdgt.o"
+".\objects\startup_gd32f1x0.o"
+".\objects\system_gd32f1x0.o"
+--strict --scatter ".\Objects\HUGS.sct"
+--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\Listings\HUGS.map" -o .\Objects\HUGS.axf
\ No newline at end of file
diff --git a/HUGS/Objects/HUGS.sct b/HUGS/Objects/HUGS.sct
new file mode 100644
index 00000000..6c8e805a
--- /dev/null
+++ b/HUGS/Objects/HUGS.sct
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00010000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00002000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/HUGS/Objects/HUGS_Target 1.dep b/HUGS/Objects/HUGS_Target 1.dep
new file mode 100644
index 00000000..e3d63daa
--- /dev/null
+++ b/HUGS/Objects/HUGS_Target 1.dep
@@ -0,0 +1,612 @@
+Dependencies for Project 'HUGS', Target 'Target 1': (DO NOT MODIFY !)
+CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
+F (.\Src\main.c)(0x60C63284)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/setup.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/defines.h)(0x60C63284)
+I (Src\../Inc/it.h)(0x60C6314A)
+I (Src\../Inc/bldc.h)(0x60C63284)
+I (Src\../Inc/comms.h)(0x60C6314A)
+I (Src\../Inc/commsHUGS.h)(0x60C63284)
+I (Src\../Inc/commsSteering.h)(0x60C63284)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x5E8EE582)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x5E8EE582)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5E8EE582)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x5E8EE582)
+F (.\Src\bldc.c)(0x60C63284)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\bldc.o --omf_browse .\objects\bldc.crf --depend .\objects\bldc.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/setup.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/defines.h)(0x60C63284)
+I (Src\../Inc/bldc.h)(0x60C63284)
+F (.\Src\setup.c)(0x60C63284)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\setup.o --omf_browse .\objects\setup.crf --depend .\objects\setup.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/setup.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/defines.h)(0x60C63284)
+I (Src\../Inc/it.h)(0x60C6314A)
+F (.\Src\it.c)(0x60C63284)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\it.o --omf_browse .\objects\it.crf --depend .\objects\it.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/it.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/defines.h)(0x60C63284)
+I (Src\../Inc/bldc.h)(0x60C63284)
+I (Src\../Inc/led.h)(0x60C6314A)
+I (Src\../Inc/commsHUGS.h)(0x60C63284)
+I (Src\../Inc/commsSteering.h)(0x60C63284)
+F (.\Src\comms.c)(0x60C6314B)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\comms.o --omf_browse .\objects\comms.crf --depend .\objects\comms.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (.\Src\commsSteering.c)(0x60C63284)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\commssteering.o --omf_browse .\objects\commssteering.crf --depend .\objects\commssteering.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/it.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/comms.h)(0x60C6314A)
+I (Src\../Inc/commsHUGS.h)(0x60C63284)
+I (Src\../Inc/commsSteering.h)(0x60C63284)
+I (Src\../Inc/setup.h)(0x60C6314A)
+I (Src\../Inc/defines.h)(0x60C63284)
+I (Src\../Inc/bldc.h)(0x60C63284)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x5E8EE582)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5E8EE582)
+F (.\Src\led.c)(0x60C6314B)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\led.o --omf_browse .\objects\led.crf --depend .\objects\led.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/led.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/defines.h)(0x60C63284)
+F (.\Src\commsHUGS.c)(0x60C63284)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -I C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.2.0\Device\Firmware\Peripherals\inc -I .\Inc -I .\RTE\target_1
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\commshugs.o --omf_browse .\objects\commshugs.crf --depend .\objects\commshugs.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+I (Src\../Inc/it.h)(0x60C6314A)
+I (Src\../Inc/../Inc/config.h)(0x60C63284)
+I (Src\../Inc/comms.h)(0x60C6314A)
+I (Src\../Inc/commsHUGS.h)(0x60C63284)
+I (Src\../Inc/setup.h)(0x60C6314A)
+I (Src\../Inc/defines.h)(0x60C63284)
+I (Src\../Inc/bldc.h)(0x60C63284)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x5E8EE582)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5E8EE582)
+F (.\Inc\defines.h)(0x60C63284)()
+F (.\Inc\config.h)(0x60C63284)()
+F (.\Inc\bldc.h)(0x60C63284)()
+F (.\Inc\setup.h)(0x60C6314A)()
+F (.\Inc\it.h)(0x60C6314A)()
+F (.\Inc\comms.h)(0x60C6314A)()
+F (.\Inc\commsSteering.h)(0x60C63284)()
+F (.\Inc\led.h)(0x60C6314A)()
+F (.\Inc\commsHUGS.h)(0x60C63284)()
+F (RTE\Device\GD32F130C8\gd32f1x0_adc.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_adc.o --omf_browse .\objects\gd32f1x0_adc.crf --depend .\objects\gd32f1x0_adc.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_dbg.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_dbg.o --omf_browse .\objects\gd32f1x0_dbg.crf --depend .\objects\gd32f1x0_dbg.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_dma.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_dma.o --omf_browse .\objects\gd32f1x0_dma.crf --depend .\objects\gd32f1x0_dma.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_fwdgt.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_fwdgt.o --omf_browse .\objects\gd32f1x0_fwdgt.crf --depend .\objects\gd32f1x0_fwdgt.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_gpio.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_gpio.o --omf_browse .\objects\gd32f1x0_gpio.crf --depend .\objects\gd32f1x0_gpio.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_i2c.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_i2c.o --omf_browse .\objects\gd32f1x0_i2c.crf --depend .\objects\gd32f1x0_i2c.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_misc.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_misc.o --omf_browse .\objects\gd32f1x0_misc.crf --depend .\objects\gd32f1x0_misc.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_opa.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_opa.o --omf_browse .\objects\gd32f1x0_opa.crf --depend .\objects\gd32f1x0_opa.d)
+F (RTE\Device\GD32F130C8\gd32f1x0_pmu.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_pmu.o --omf_browse .\objects\gd32f1x0_pmu.crf --depend .\objects\gd32f1x0_pmu.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_rcu.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_rcu.o --omf_browse .\objects\gd32f1x0_rcu.crf --depend .\objects\gd32f1x0_rcu.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_syscfg.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_syscfg.o --omf_browse .\objects\gd32f1x0_syscfg.crf --depend .\objects\gd32f1x0_syscfg.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_timer.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_timer.o --omf_browse .\objects\gd32f1x0_timer.crf --depend .\objects\gd32f1x0_timer.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_usart.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_usart.o --omf_browse .\objects\gd32f1x0_usart.crf --depend .\objects\gd32f1x0_usart.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\gd32f1x0_wwdgt.c)(0x5A7B5838)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\gd32f1x0_wwdgt.o --omf_browse .\objects\gd32f1x0_wwdgt.crf --depend .\objects\gd32f1x0_wwdgt.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
+F (RTE\Device\GD32F130C8\startup_gd32f1x0.s)(0x5A7B583A)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
--pd "__UVISION_VERSION SETA 534" --pd "_RTE_ SETA 1" --pd "GD32F1x0 SETA 1" --pd "GD32F130_150 SETA 1" --pd "USE_STDPERIPH_DRIVER SETA 1" --pd "_RTE_ SETA 1"
--list .\listings\startup_gd32f1x0.lst --xref -o .\objects\startup_gd32f1x0.o --depend .\objects\startup_gd32f1x0.d)
+F (RTE\Device\GD32F130C8\system_gd32f1x0.c)(0x5A7B583A)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork
-I.\RTE\_Target_1
-IC:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc
-IC:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include
-D__UVISION_VERSION="534" -D_RTE_ -DGD32F1x0 -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -D_RTE_
-o .\objects\system_gd32f1x0.o --omf_browse .\objects\system_gd32f1x0.crf --depend .\objects\system_gd32f1x0.d)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h)(0x5E8F79E2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5E8EE582)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5E83AF82)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h)(0x5E8F79E2)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h)(0x5A7C59D6)
+I (.\RTE\_Target_1\RTE_Components.h)(0x60C93F55)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h)(0x5A7B5838)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h)(0x5A7B583A)
+I (C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h)(0x5A7B5838)
diff --git a/HUGS/Objects/bldc.crf b/HUGS/Objects/bldc.crf
new file mode 100644
index 00000000..bb872ecb
Binary files /dev/null and b/HUGS/Objects/bldc.crf differ
diff --git a/HUGS/Objects/bldc.d b/HUGS/Objects/bldc.d
new file mode 100644
index 00000000..81de7077
--- /dev/null
+++ b/HUGS/Objects/bldc.d
@@ -0,0 +1,30 @@
+.\objects\bldc.o: Src\bldc.c
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\bldc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\bldc.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\bldc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\bldc.o: Src\../Inc/setup.h
+.\objects\bldc.o: Src\../Inc/../Inc/config.h
+.\objects\bldc.o: Src\../Inc/defines.h
+.\objects\bldc.o: Src\../Inc/bldc.h
diff --git a/HUGS/Objects/bldc.o b/HUGS/Objects/bldc.o
new file mode 100644
index 00000000..0855881e
Binary files /dev/null and b/HUGS/Objects/bldc.o differ
diff --git a/HUGS/Objects/comms.crf b/HUGS/Objects/comms.crf
new file mode 100644
index 00000000..239bfe2f
Binary files /dev/null and b/HUGS/Objects/comms.crf differ
diff --git a/HUGS/Objects/comms.d b/HUGS/Objects/comms.d
new file mode 100644
index 00000000..ee31a096
--- /dev/null
+++ b/HUGS/Objects/comms.d
@@ -0,0 +1,26 @@
+.\objects\comms.o: Src\comms.c
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\comms.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\comms.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\comms.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/comms.o b/HUGS/Objects/comms.o
new file mode 100644
index 00000000..95d7d2a2
Binary files /dev/null and b/HUGS/Objects/comms.o differ
diff --git a/HUGS/Objects/commshugs.crf b/HUGS/Objects/commshugs.crf
new file mode 100644
index 00000000..68eaad21
Binary files /dev/null and b/HUGS/Objects/commshugs.crf differ
diff --git a/HUGS/Objects/commshugs.d b/HUGS/Objects/commshugs.d
new file mode 100644
index 00000000..d661ec04
--- /dev/null
+++ b/HUGS/Objects/commshugs.d
@@ -0,0 +1,35 @@
+.\objects\commshugs.o: Src\commsHUGS.c
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\commshugs.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\commshugs.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\commshugs.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\commshugs.o: Src\../Inc/it.h
+.\objects\commshugs.o: Src\../Inc/../Inc/config.h
+.\objects\commshugs.o: Src\../Inc/comms.h
+.\objects\commshugs.o: Src\../Inc/commsHUGS.h
+.\objects\commshugs.o: Src\../Inc/setup.h
+.\objects\commshugs.o: Src\../Inc/defines.h
+.\objects\commshugs.o: Src\../Inc/bldc.h
+.\objects\commshugs.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\objects\commshugs.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/HUGS/Objects/commshugs.o b/HUGS/Objects/commshugs.o
new file mode 100644
index 00000000..f6b9ad13
Binary files /dev/null and b/HUGS/Objects/commshugs.o differ
diff --git a/HUGS/Objects/commssteering.crf b/HUGS/Objects/commssteering.crf
new file mode 100644
index 00000000..daade68a
Binary files /dev/null and b/HUGS/Objects/commssteering.crf differ
diff --git a/HUGS/Objects/commssteering.d b/HUGS/Objects/commssteering.d
new file mode 100644
index 00000000..74fce602
--- /dev/null
+++ b/HUGS/Objects/commssteering.d
@@ -0,0 +1,36 @@
+.\objects\commssteering.o: Src\commsSteering.c
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\commssteering.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\commssteering.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\commssteering.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\commssteering.o: Src\../Inc/it.h
+.\objects\commssteering.o: Src\../Inc/../Inc/config.h
+.\objects\commssteering.o: Src\../Inc/comms.h
+.\objects\commssteering.o: Src\../Inc/commsHUGS.h
+.\objects\commssteering.o: Src\../Inc/commsSteering.h
+.\objects\commssteering.o: Src\../Inc/setup.h
+.\objects\commssteering.o: Src\../Inc/defines.h
+.\objects\commssteering.o: Src\../Inc/bldc.h
+.\objects\commssteering.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\objects\commssteering.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/HUGS/Objects/commssteering.o b/HUGS/Objects/commssteering.o
new file mode 100644
index 00000000..c91f5e09
Binary files /dev/null and b/HUGS/Objects/commssteering.o differ
diff --git a/HUGS/Objects/gd32f1x0_adc.crf b/HUGS/Objects/gd32f1x0_adc.crf
new file mode 100644
index 00000000..e7018cc3
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_adc.crf differ
diff --git a/HUGS/Objects/gd32f1x0_adc.d b/HUGS/Objects/gd32f1x0_adc.d
new file mode 100644
index 00000000..5d770b32
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_adc.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_adc.o: RTE\Device\GD32F130C8\gd32f1x0_adc.c
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_adc.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_adc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_adc.o b/HUGS/Objects/gd32f1x0_adc.o
new file mode 100644
index 00000000..8d9ed8e4
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_adc.o differ
diff --git a/HUGS/Objects/gd32f1x0_dbg.crf b/HUGS/Objects/gd32f1x0_dbg.crf
new file mode 100644
index 00000000..5ff3b3ed
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_dbg.crf differ
diff --git a/HUGS/Objects/gd32f1x0_dbg.d b/HUGS/Objects/gd32f1x0_dbg.d
new file mode 100644
index 00000000..000c733b
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_dbg.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_dbg.o: RTE\Device\GD32F130C8\gd32f1x0_dbg.c
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_dbg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_dbg.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_dbg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_dbg.o b/HUGS/Objects/gd32f1x0_dbg.o
new file mode 100644
index 00000000..258b915c
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_dbg.o differ
diff --git a/HUGS/Objects/gd32f1x0_dma.crf b/HUGS/Objects/gd32f1x0_dma.crf
new file mode 100644
index 00000000..4100f2d2
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_dma.crf differ
diff --git a/HUGS/Objects/gd32f1x0_dma.d b/HUGS/Objects/gd32f1x0_dma.d
new file mode 100644
index 00000000..57e1bd12
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_dma.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_dma.o: RTE\Device\GD32F130C8\gd32f1x0_dma.c
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_dma.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_dma.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_dma.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_dma.o b/HUGS/Objects/gd32f1x0_dma.o
new file mode 100644
index 00000000..9a40c66b
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_dma.o differ
diff --git a/HUGS/Objects/gd32f1x0_fwdgt.crf b/HUGS/Objects/gd32f1x0_fwdgt.crf
new file mode 100644
index 00000000..2d503f85
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_fwdgt.crf differ
diff --git a/HUGS/Objects/gd32f1x0_fwdgt.d b/HUGS/Objects/gd32f1x0_fwdgt.d
new file mode 100644
index 00000000..ae789318
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_fwdgt.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_fwdgt.o: RTE\Device\GD32F130C8\gd32f1x0_fwdgt.c
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_fwdgt.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_fwdgt.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_fwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_fwdgt.o b/HUGS/Objects/gd32f1x0_fwdgt.o
new file mode 100644
index 00000000..21157122
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_fwdgt.o differ
diff --git a/HUGS/Objects/gd32f1x0_gpio.crf b/HUGS/Objects/gd32f1x0_gpio.crf
new file mode 100644
index 00000000..381b2c05
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_gpio.crf differ
diff --git a/HUGS/Objects/gd32f1x0_gpio.d b/HUGS/Objects/gd32f1x0_gpio.d
new file mode 100644
index 00000000..614374b1
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_gpio.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_gpio.o: RTE\Device\GD32F130C8\gd32f1x0_gpio.c
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_gpio.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_gpio.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_gpio.o b/HUGS/Objects/gd32f1x0_gpio.o
new file mode 100644
index 00000000..03445ace
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_gpio.o differ
diff --git a/HUGS/Objects/gd32f1x0_i2c.crf b/HUGS/Objects/gd32f1x0_i2c.crf
new file mode 100644
index 00000000..1af64e75
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_i2c.crf differ
diff --git a/HUGS/Objects/gd32f1x0_i2c.d b/HUGS/Objects/gd32f1x0_i2c.d
new file mode 100644
index 00000000..533aaddf
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_i2c.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_i2c.o: RTE\Device\GD32F130C8\gd32f1x0_i2c.c
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_i2c.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_i2c.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_i2c.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_i2c.o b/HUGS/Objects/gd32f1x0_i2c.o
new file mode 100644
index 00000000..30b66590
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_i2c.o differ
diff --git a/HUGS/Objects/gd32f1x0_misc.crf b/HUGS/Objects/gd32f1x0_misc.crf
new file mode 100644
index 00000000..b4880f08
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_misc.crf differ
diff --git a/HUGS/Objects/gd32f1x0_misc.d b/HUGS/Objects/gd32f1x0_misc.d
new file mode 100644
index 00000000..702ff4e3
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_misc.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_misc.o: RTE\Device\GD32F130C8\gd32f1x0_misc.c
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_misc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_misc.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_misc.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_misc.o b/HUGS/Objects/gd32f1x0_misc.o
new file mode 100644
index 00000000..c91d4d00
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_misc.o differ
diff --git a/HUGS/Objects/gd32f1x0_opa.crf b/HUGS/Objects/gd32f1x0_opa.crf
new file mode 100644
index 00000000..81d28216
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_opa.crf differ
diff --git a/HUGS/Objects/gd32f1x0_opa.d b/HUGS/Objects/gd32f1x0_opa.d
new file mode 100644
index 00000000..46570c0a
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_opa.d
@@ -0,0 +1 @@
+.\objects\gd32f1x0_opa.o: RTE\Device\GD32F130C8\gd32f1x0_opa.c
diff --git a/HUGS/Objects/gd32f1x0_opa.o b/HUGS/Objects/gd32f1x0_opa.o
new file mode 100644
index 00000000..c03a4997
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_opa.o differ
diff --git a/HUGS/Objects/gd32f1x0_pmu.crf b/HUGS/Objects/gd32f1x0_pmu.crf
new file mode 100644
index 00000000..10f93b06
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_pmu.crf differ
diff --git a/HUGS/Objects/gd32f1x0_pmu.d b/HUGS/Objects/gd32f1x0_pmu.d
new file mode 100644
index 00000000..730ed3cb
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_pmu.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_pmu.o: RTE\Device\GD32F130C8\gd32f1x0_pmu.c
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_pmu.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_pmu.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_pmu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_pmu.o b/HUGS/Objects/gd32f1x0_pmu.o
new file mode 100644
index 00000000..898f1d18
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_pmu.o differ
diff --git a/HUGS/Objects/gd32f1x0_rcu.crf b/HUGS/Objects/gd32f1x0_rcu.crf
new file mode 100644
index 00000000..48ff942f
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_rcu.crf differ
diff --git a/HUGS/Objects/gd32f1x0_rcu.d b/HUGS/Objects/gd32f1x0_rcu.d
new file mode 100644
index 00000000..1a0f352a
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_rcu.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_rcu.o: RTE\Device\GD32F130C8\gd32f1x0_rcu.c
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_rcu.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_rcu.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_rcu.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_rcu.o b/HUGS/Objects/gd32f1x0_rcu.o
new file mode 100644
index 00000000..213f9673
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_rcu.o differ
diff --git a/HUGS/Objects/gd32f1x0_syscfg.crf b/HUGS/Objects/gd32f1x0_syscfg.crf
new file mode 100644
index 00000000..9e189a22
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_syscfg.crf differ
diff --git a/HUGS/Objects/gd32f1x0_syscfg.d b/HUGS/Objects/gd32f1x0_syscfg.d
new file mode 100644
index 00000000..ddaab139
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_syscfg.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_syscfg.o: RTE\Device\GD32F130C8\gd32f1x0_syscfg.c
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_syscfg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_syscfg.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_syscfg.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_syscfg.o b/HUGS/Objects/gd32f1x0_syscfg.o
new file mode 100644
index 00000000..e9589be9
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_syscfg.o differ
diff --git a/HUGS/Objects/gd32f1x0_timer.crf b/HUGS/Objects/gd32f1x0_timer.crf
new file mode 100644
index 00000000..373573c0
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_timer.crf differ
diff --git a/HUGS/Objects/gd32f1x0_timer.d b/HUGS/Objects/gd32f1x0_timer.d
new file mode 100644
index 00000000..d328de34
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_timer.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_timer.o: RTE\Device\GD32F130C8\gd32f1x0_timer.c
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_timer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_timer.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_timer.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_timer.o b/HUGS/Objects/gd32f1x0_timer.o
new file mode 100644
index 00000000..cca9cb4e
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_timer.o differ
diff --git a/HUGS/Objects/gd32f1x0_usart.crf b/HUGS/Objects/gd32f1x0_usart.crf
new file mode 100644
index 00000000..65ae7e3f
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_usart.crf differ
diff --git a/HUGS/Objects/gd32f1x0_usart.d b/HUGS/Objects/gd32f1x0_usart.d
new file mode 100644
index 00000000..51580bd2
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_usart.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_usart.o: RTE\Device\GD32F130C8\gd32f1x0_usart.c
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_usart.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_usart.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_usart.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_usart.o b/HUGS/Objects/gd32f1x0_usart.o
new file mode 100644
index 00000000..18c9cdf6
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_usart.o differ
diff --git a/HUGS/Objects/gd32f1x0_wwdgt.crf b/HUGS/Objects/gd32f1x0_wwdgt.crf
new file mode 100644
index 00000000..ce4091a3
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_wwdgt.crf differ
diff --git a/HUGS/Objects/gd32f1x0_wwdgt.d b/HUGS/Objects/gd32f1x0_wwdgt.d
new file mode 100644
index 00000000..3ee26b2f
--- /dev/null
+++ b/HUGS/Objects/gd32f1x0_wwdgt.d
@@ -0,0 +1,27 @@
+.\objects\gd32f1x0_wwdgt.o: RTE\Device\GD32F130C8\gd32f1x0_wwdgt.c
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\gd32f1x0_wwdgt.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\gd32f1x0_wwdgt.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\gd32f1x0_wwdgt.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/gd32f1x0_wwdgt.o b/HUGS/Objects/gd32f1x0_wwdgt.o
new file mode 100644
index 00000000..76f62c32
Binary files /dev/null and b/HUGS/Objects/gd32f1x0_wwdgt.o differ
diff --git a/HUGS/Objects/it.crf b/HUGS/Objects/it.crf
new file mode 100644
index 00000000..87c05674
Binary files /dev/null and b/HUGS/Objects/it.crf differ
diff --git a/HUGS/Objects/it.d b/HUGS/Objects/it.d
new file mode 100644
index 00000000..174d5a8e
--- /dev/null
+++ b/HUGS/Objects/it.d
@@ -0,0 +1,33 @@
+.\objects\it.o: Src\it.c
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\it.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\it.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\it.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\it.o: Src\../Inc/it.h
+.\objects\it.o: Src\../Inc/../Inc/config.h
+.\objects\it.o: Src\../Inc/defines.h
+.\objects\it.o: Src\../Inc/bldc.h
+.\objects\it.o: Src\../Inc/led.h
+.\objects\it.o: Src\../Inc/commsHUGS.h
+.\objects\it.o: Src\../Inc/commsSteering.h
diff --git a/HUGS/Objects/it.o b/HUGS/Objects/it.o
new file mode 100644
index 00000000..a36ff650
Binary files /dev/null and b/HUGS/Objects/it.o differ
diff --git a/HUGS/Objects/led.crf b/HUGS/Objects/led.crf
new file mode 100644
index 00000000..4cd952af
Binary files /dev/null and b/HUGS/Objects/led.crf differ
diff --git a/HUGS/Objects/led.d b/HUGS/Objects/led.d
new file mode 100644
index 00000000..654230d8
--- /dev/null
+++ b/HUGS/Objects/led.d
@@ -0,0 +1,29 @@
+.\objects\led.o: Src\led.c
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\led.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\led.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\led.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\led.o: Src\../Inc/led.h
+.\objects\led.o: Src\../Inc/../Inc/config.h
+.\objects\led.o: Src\../Inc/defines.h
diff --git a/HUGS/Objects/led.o b/HUGS/Objects/led.o
new file mode 100644
index 00000000..e20d6a1b
Binary files /dev/null and b/HUGS/Objects/led.o differ
diff --git a/HUGS/Objects/main.crf b/HUGS/Objects/main.crf
new file mode 100644
index 00000000..25e5572c
Binary files /dev/null and b/HUGS/Objects/main.crf differ
diff --git a/HUGS/Objects/main.d b/HUGS/Objects/main.d
new file mode 100644
index 00000000..184c5ca6
--- /dev/null
+++ b/HUGS/Objects/main.d
@@ -0,0 +1,38 @@
+.\objects\main.o: Src\main.c
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\main.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\main.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\main.o: Src\../Inc/setup.h
+.\objects\main.o: Src\../Inc/../Inc/config.h
+.\objects\main.o: Src\../Inc/defines.h
+.\objects\main.o: Src\../Inc/it.h
+.\objects\main.o: Src\../Inc/bldc.h
+.\objects\main.o: Src\../Inc/comms.h
+.\objects\main.o: Src\../Inc/commsHUGS.h
+.\objects\main.o: Src\../Inc/commsSteering.h
+.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
diff --git a/HUGS/Objects/main.o b/HUGS/Objects/main.o
new file mode 100644
index 00000000..6adb2cc3
Binary files /dev/null and b/HUGS/Objects/main.o differ
diff --git a/HUGS/Objects/setup.crf b/HUGS/Objects/setup.crf
new file mode 100644
index 00000000..a7fe5bff
Binary files /dev/null and b/HUGS/Objects/setup.crf differ
diff --git a/HUGS/Objects/setup.d b/HUGS/Objects/setup.d
new file mode 100644
index 00000000..492e8c1e
--- /dev/null
+++ b/HUGS/Objects/setup.d
@@ -0,0 +1,30 @@
+.\objects\setup.o: Src\setup.c
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\setup.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\setup.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\setup.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
+.\objects\setup.o: Src\../Inc/setup.h
+.\objects\setup.o: Src\../Inc/../Inc/config.h
+.\objects\setup.o: Src\../Inc/defines.h
+.\objects\setup.o: Src\../Inc/it.h
diff --git a/HUGS/Objects/setup.o b/HUGS/Objects/setup.o
new file mode 100644
index 00000000..b2df0ff7
Binary files /dev/null and b/HUGS/Objects/setup.o differ
diff --git a/HUGS/Objects/startup_gd32f1x0.d b/HUGS/Objects/startup_gd32f1x0.d
new file mode 100644
index 00000000..d1c2a46f
--- /dev/null
+++ b/HUGS/Objects/startup_gd32f1x0.d
@@ -0,0 +1 @@
+.\objects\startup_gd32f1x0.o: RTE\Device\GD32F130C8\startup_gd32f1x0.s
diff --git a/HUGS/Objects/startup_gd32f1x0.o b/HUGS/Objects/startup_gd32f1x0.o
new file mode 100644
index 00000000..e991f25d
Binary files /dev/null and b/HUGS/Objects/startup_gd32f1x0.o differ
diff --git a/HUGS/Objects/system_gd32f1x0.crf b/HUGS/Objects/system_gd32f1x0.crf
new file mode 100644
index 00000000..52203121
Binary files /dev/null and b/HUGS/Objects/system_gd32f1x0.crf differ
diff --git a/HUGS/Objects/system_gd32f1x0.d b/HUGS/Objects/system_gd32f1x0.d
new file mode 100644
index 00000000..bb99bd10
--- /dev/null
+++ b/HUGS/Objects/system_gd32f1x0.d
@@ -0,0 +1,26 @@
+.\objects\system_gd32f1x0.o: RTE\Device\GD32F130C8\system_gd32f1x0.c
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\core_cm3.h
+.\objects\system_gd32f1x0.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_version.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_compiler.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\cmsis_armcc.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include\mpu_armv7.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\system_gd32f1x0.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0_libopt.h
+.\objects\system_gd32f1x0.o: .\RTE\_Target_1\RTE_Components.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_adc.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Include\gd32f1x0.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dbg.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_dma.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_gpio.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_syscfg.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_i2c.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_fwdgt.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_pmu.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_rcu.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_timer.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_usart.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_wwdgt.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_misc.h
+.\objects\system_gd32f1x0.o: C:\Users\13015\AppData\Local\Arm\Packs\GigaDevice\GD32F1x0_DFP\3.1.0\Device\Firmware\Peripherals\inc\gd32f1x0_opa.h
diff --git a/HUGS/Objects/system_gd32f1x0.o b/HUGS/Objects/system_gd32f1x0.o
new file mode 100644
index 00000000..30076190
Binary files /dev/null and b/HUGS/Objects/system_gd32f1x0.o differ
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_adc.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_adc.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_adc.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_adc.c
index 2f765eb2..c56ab8aa 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_adc.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_adc.c
@@ -1,817 +1,817 @@
-/*!
- \file gd32f1x0_adc.c
- \brief ADC driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_adc.h"
-
-/*!
- \brief ADC reset
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_deinit(void)
-{
- rcu_periph_reset_enable(RCU_ADCRST);
- rcu_periph_reset_disable(RCU_ADCRST);
-}
-
-/*!
- \brief enable ADC interface
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_enable(void)
-{
- if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){
- ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
- }
-}
-
-/*!
- \brief disable ADC interface
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_disable(void)
-{
- ADC_CTL1 &= (uint32_t)~(ADC_CTL1_ADCON);
-}
-
-/*!
- \brief ADC calibration and reset calibration
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_calibration_enable(void)
-{
- /* reset the selected ADC1 calibration registers */
- ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
- /* check the RSTCLB bit state */
- while((ADC_CTL1 & ADC_CTL1_RSTCLB)){
- }
- /* enable ADC calibration process */
- ADC_CTL1 |= ADC_CTL1_CLB;
- /* check the CLB bit state */
- while((ADC_CTL1 & ADC_CTL1_CLB)){
- }
-}
-
-/*!
- \brief enable DMA request
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_dma_mode_enable(void)
-{
- ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
-}
-
-/*!
- \brief disable DMA request
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_dma_mode_disable(void)
-{
- ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
-}
-
-/*!
- \brief enable ADC0 temperature sensor and Vrefint channel
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_tempsensor_vrefint_enable(void)
-{
- /* enable the temperature sensor and Vrefint channel */
- ADC_CTL1 |= ADC_CTL1_TSVREN;
-}
-
-/*!
- \brief disable ADC0 temperature sensor and Vrefint channel
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_tempsensor_vrefint_disable(void)
-{
- /* disable the temperature sensor and Vrefint channel */
- ADC_CTL1 &= ~ADC_CTL1_TSVREN;
-}
-
-/*!
- \brief enable the vbat channel
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_vbat_enable(void)
-{
- /* enable the vbat channel */
- ADC_CTL1 |= ADC_CTL1_VBETEN;
-}
-
-/*!
- \brief disable the vbat channel
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_vbat_disable(void)
-{
- /* disable the vbat channel */
- ADC_CTL1 &= ~ADC_CTL1_VBETEN;
-}
-
-/*!
- \brief adc discontinuous mode config
- \param[in] channel_group: select the channel group
- \arg ADC_REGULAR_CHANNEL: regular channel group
- \arg ADC_INSERTED_CHANNEL: inserted channel group
- \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
- for regular channel ,the number is insignificant for inserted channel
- \param[out] none
- \retval none
-*/
-void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length)
-{
- ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
- switch(channel_group){
- case ADC_REGULAR_CHANNEL:
- /* config the number of conversions in discontinuous mode */
- ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
- ADC_CTL0 |= (uint32_t)(((uint32_t)length - 1U) << 13U);
-
- ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
- break;
- case ADC_INSERTED_CHANNEL:
- ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief enable or disable ADC special function
- \param[in] function: the function to config
- one or more parameters can be selected below
- \arg ADC_SCAN_MODE: scan mode select
- \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
- \arg ADC_CONTINUOUS_MODE: continuous mode select
- \param[in] newvalue: ENABLE or DISABLE
- \param[out] none
- \retval none
-*/
-void adc_special_function_config(uint32_t function, ControlStatus newvalue)
-{
- if(newvalue){
- if(RESET != (function & ADC_SCAN_MODE)){
- ADC_CTL0 |= ADC_SCAN_MODE;
- }
- if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
- ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO;
- }
- if(RESET != (function & ADC_CONTINUOUS_MODE)){
- ADC_CTL1 |= ADC_CONTINUOUS_MODE;
- }
- }else{
- if(RESET != (function & ADC_SCAN_MODE)){
- ADC_CTL0 &= ~ADC_SCAN_MODE;
- }
- if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
- ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO;
- }
- if(RESET != (function & ADC_CONTINUOUS_MODE)){
- ADC_CTL1 &= ~ADC_CONTINUOUS_MODE;
- }
- }
-}
-
-/*!
- \brief adc data alignment config
- \param[in] data_alignment: data alignment select
- only one parameter can be selected
- \arg ADC_DATAALIGN_RIGHT: LSB alignment
- \arg ADC_DATAALIGN_LEFT: MSB alignment
- \param[out] none
- \retval none
-*/
-void adc_data_alignment_config(uint32_t data_alignment)
-{
- if(data_alignment){
- ADC_CTL1 |= ADC_CTL1_DAL;
- }else{
- ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
- }
-}
-
-/*!
- \brief config the length of regular channel group or inserted channel group
- \param[in] channel_group: select the channel group
- only one parameter can be selected
- \arg ADC_REGULAR_CHANNEL: regular channel group
- \arg ADC_INSERTED_CHANNEL: inserted channel group
- \param[in] length: the length of the channel
- regular channel 1-17
- inserted channel 1-4
- \param[out] none
- \retval none
-*/
-void adc_channel_length_config(uint8_t channel_group,uint32_t length)
-{
- switch(channel_group){
- case ADC_REGULAR_CHANNEL:
- ADC_RSQ0 &= ~(((uint32_t)length - 1U) << 20U);
- ADC_RSQ0 |= (((uint32_t)length - 1U) << 20U);
- break;
- case ADC_INSERTED_CHANNEL:
- ADC_ISQ &= ~(((uint32_t)length - 1U) << 20U);
- ADC_ISQ |= (((uint32_t)length - 1U) << 20U);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief ADC regular channel config
- \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15
- \param[in] channel: the selected ADC channel
- \arg ADC_CHANNEL_x(x=0..18): ADC Channelx
- \param[in] sample_time: the sample time value
- \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
- \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
- \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
- \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
- \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
- \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
- \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
- \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
- \param[out] none
- \retval none
-*/
-void adc_regular_channel_config(uint8_t rank, uint8_t channel,uint32_t sample_time)
-{
- uint32_t rsq,sampt;
-
-#ifdef GD32F130_150
- if(ADC_CHANNEL_18 == channel){
- channel = ADC_CHANNEL_0;
- }
-#endif
-
- /* configure ADC regular sequence */
- if(rank < 6U){
- rsq = ADC_RSQ2;
- rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
- rsq |= ((uint32_t)channel << (5U*rank));
- ADC_RSQ2 = rsq;
- }else if(rank < 12U){
- rsq = ADC_RSQ1;
- rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
- rsq |= ((uint32_t)channel << (5U*(rank-6U)));
- ADC_RSQ1 = rsq;
- }else if(rank < 16U){
- rsq = ADC_RSQ0;
- rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
- rsq |= ((uint32_t)channel << (5U*(rank-12U)));
- ADC_RSQ0 = rsq;
- }else{
- /* illegal parameters */
- }
-
- /* configure ADC sampling time */
- if(channel < 10U){
- sampt = ADC_SAMPT1;
- sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
- sampt |= (uint32_t)(sample_time << (3U*channel));
- ADC_SAMPT1 = sampt;
- }else if(channel < 18U){
- sampt = ADC_SAMPT0;
- sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
- sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
- ADC_SAMPT0 = sampt;
- }else{
- /* illegal parameters */
- }
-}
-
-/*!
- \brief ADC inserted channel config
- \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
- \param[in] channel: the selected ADC channel
- \arg ADC_CHANNEL_x(x=0..18): ADC Channelx
- \param[in] sample_time: The sample time value
- \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
- \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
- \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
- \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
- \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
- \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
- \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
- \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
- \param[out] none
- \retval none
-*/
-void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
-{
- uint8_t inserted_length;
- uint32_t isq,sampt;
-
- inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20, 21);
- if(rank < 5U){
- isq = ADC_ISQ;
- isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U)));
- isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U));
- ADC_ISQ = isq;
- }
-
- if(channel < 10U){
- sampt = ADC_SAMPT1;
- sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
- sampt |= (uint32_t) sample_time << (3U*channel);
- ADC_SAMPT1 = sampt;
- }else if(channel < 19U){
- sampt = ADC_SAMPT0;
- sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
- sampt |= ((uint32_t)sample_time << (3U*(channel-10U)));
- ADC_SAMPT0 = sampt;
- }else{
- /* illegal parameters */
- }
-}
-
-/*!
- \brief adc inserted channel offset config
- \param[in] inserted_channel : insert channel select
- \arg ADC_INSERTED_CHANNEL_0: inserted channel0
- \arg ADC_INSERTED_CHANNEL_1: inserted channel1
- \arg ADC_INSERTED_CHANNEL_2: inserted channel2
- \arg ADC_INSERTED_CHANNEL_3: inserted channel3
- \param[in] offset : the offset data
- \param[out] none
- \retval the conversion value
-*/
-void adc_inserted_channel_offset_config(uint8_t inserted_channel,uint16_t offset)
-{
- uint8_t inserted_length;
- uint32_t num = 0U;
-
- inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
- num = 3U - (inserted_length - inserted_channel);
-
- if(num <= 3U){
- /* calculate the offset of the register */
- num = num * 4U;
- /* config the offset of the selected channels */
- REG32((ADC_BASE) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
- }
-}
-
-/*!
- \brief adc external trigger enable
- \param[in] adc_channel_group: select the channel group
- \arg ADC_REGULAR_CHANNEL: regular channel group
- \arg ADC_INSERTED_CHANNEL: inserted channel group
- \param[in] newvalue: ENABLE or DISABLE
- \param[out] none
- \retval none
-*/
-void adc_external_trigger_config(uint8_t channel_group,ControlStatus newvalue)
-{
- if(newvalue){
- if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
- ADC_CTL1 |= ADC_CTL1_ETERC;
- }
- if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
- ADC_CTL1 |= ADC_CTL1_ETEIC;
- }
- }else{
- if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
- ADC_CTL1 &= ~ADC_CTL1_ETERC;
- }
- if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
- ADC_CTL1 &= ~ADC_CTL1_ETEIC;
- }
- }
-}
-
-/*!
- \brief adc external trigger source config
- \param[in] adc_channel_group: select the channel group
- \arg ADC_REGULAR_CHANNEL: regular channel group
- \arg ADC_INSERTED_CHANNEL: inserted channel group
- \param[in] external_trigger_source: regular or inserted group trigger source
- for regular channel:
- \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CH0 event select for regular channel
- \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CH1 event select for regular channel
- \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CH2 event select for regular channel
- \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CH1 event select for regular channel
- \arg ADC_EXTTRIG_REGULAR_T2_TRGO: external trigger timer 2 TRGO event select for regular channel
- \arg ADC_EXTTRIG_REGULAR_T14_CH0: external trigger timer 14 CH0 event select for regular channel
- \arg ADC_EXTTRIG_REGULAR_EXT_IT11: external trigger extiline 11 select for regular channel
- \arg ADC_EXTTRIG_REGULAR_SWRCST: software trigger select for regular channel
- for inserted channel:
- \arg ADC_EXTTRIG_INSERTED_T0_TRGO: external trigger timer0 TRGO event select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_T0_CH3: external trigger timer0 CH3 event select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_T1_TRGO: external trigger timer1 TRGO event select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_T1_CH0: external trigger timer1 CH0 event select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_T2_CH3: external trigger timer2 CH3 event select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_T14_TRGO: external trigger timer14 TRGO event select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_EXT_IT15: external interrupt line 15 select for inserted channel
- \arg ADC_EXTTRIG_INSERTED_SWRCST: software trigger select for inserted channel
- \param[out] none
- \retval none
-*/
-void adc_external_trigger_source_config(uint8_t channel_group,uint32_t external_trigger_source)
-{
- switch(channel_group){
- case ADC_REGULAR_CHANNEL:
- ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
- ADC_CTL1 |= (uint32_t)external_trigger_source;
- break;
- case ADC_INSERTED_CHANNEL:
- ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
- ADC_CTL1 |= (uint32_t)external_trigger_source;
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief adc software trigger enable
- \param[in] adc_channel_group: select the channel group
- \arg ADC_REGULAR_CHANNEL: regular channel group
- \arg ADC_INSERTED_CHANNEL: inserted channel group
- \param[out] none
- \retval none
-*/
-void adc_software_trigger_enable(uint8_t channel_group)
-{
- if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
- ADC_CTL1 |= ADC_CTL1_SWRCST;
- }
- if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
- ADC_CTL1 |= ADC_CTL1_SWICST;
- }
-}
-
-/*!
- \brief adc regular group data register read
- \param[in] none
- \param[out] none
- \retval the conversion value
-*/
-uint16_t adc_regular_data_read(void)
-{
- return (uint16_t)(ADC_RDATA);
-}
-
-/*!
- \brief adc inserted group data register read
- \param[in] inserted_channel : insert channel select
- \arg ADC_INSERTED_CHANNEL_0: inserted channel0
- \arg ADC_INSERTED_CHANNEL_1: inserted channel1
- \arg ADC_INSERTED_CHANNEL_2: inserted channel2
- \arg ADC_INSERTED_CHANNEL_3: inserted channel3
- \param[out] none
- \retval the conversion value
-*/
-uint16_t adc_inserted_data_read(uint8_t inserted_channel)
-{
- uint32_t idata;
- /* read the data of the selected channel */
- switch(inserted_channel){
- case ADC_INSERTED_CHANNEL_0:
- idata = ADC_IDATA0;
- break;
- case ADC_INSERTED_CHANNEL_1:
- idata = ADC_IDATA1;
- break;
- case ADC_INSERTED_CHANNEL_2:
- idata = ADC_IDATA2;
- break;
- case ADC_INSERTED_CHANNEL_3:
- idata = ADC_IDATA3;
- break;
- default:
- idata = 0U;
- break;
- }
- return (uint16_t)idata;
-}
-
-/*!
- \brief get the ADC flag bits
- \param[in] flag: the adc flag bits
- \arg ADC_FLAG_WDE: analog watchdog event flag
- \arg ADC_FLAG_EOC: end of group conversion flag
- \arg ADC_FLAG_EOIC: end of inserted group conversion flag
- \arg ADC_FLAG_STIC: start flag of inserted channel group
- \arg ADC_FLAG_STRC: start flag of regular channel group
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus adc_flag_get(uint32_t flag)
-{
- FlagStatus reval = RESET;
-
- if(ADC_STAT & flag){
- reval = SET;
- }
- return reval;
-
-}
-
-/*!
- \brief clear the ADC status flag
- \param[in] flag: the adc flag bits
- \arg ADC_FLAG_WDE: analog watchdog event flag
- \arg ADC_FLAG_EOC: end of group conversion flag
- \arg ADC_FLAG_EOIC: end of inserted group conversion flag
- \arg ADC_FLAG_STIC: start flag of inserted channel group
- \arg ADC_FLAG_STRC: start flag of regular channel group
- \param[out] none
- \retval none
-*/
-void adc_flag_clear(uint32_t flag)
-{
- ADC_STAT &= ~((uint32_t)flag);
-}
-
-/*!
- \brief get the ADC interrupt bits
- \param[in] flag: the adc interrupt flag
- \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag
- \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
- \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus adc_interrupt_flag_get(uint32_t flag)
-{
- FlagStatus interrupt_flag = RESET;
- uint32_t state;
- /* check the interrupt bits */
- switch(flag){
- case ADC_INT_FLAG_WDE:
- state = ADC_STAT & ADC_STAT_WDE;
- if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
- interrupt_flag = SET;
- }
- break;
- case ADC_INT_FLAG_EOC:
- state = ADC_STAT & ADC_STAT_EOC;
- if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){
- interrupt_flag = SET;
- }
- break;
- case ADC_INT_FLAG_EOIC:
- state = ADC_STAT & ADC_STAT_EOIC;
- if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){
- interrupt_flag = SET;
- }
- break;
- default:
- break;
- }
-
- return interrupt_flag;
-}
-
-/*!
- \brief clear the ADC interrupt bits
- \param[in] adc_interrupt: the adc interrupt bits
- \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag
- \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
- \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
- \param[out] none
- \retval none
-*/
-void adc_interrupt_flag_clear(uint32_t flag)
-{
- ADC_STAT &= ~((uint32_t)flag);
-}
-
-/*!
- \brief enable ADC interrupt
- \param[in] adc_periph: ADCx, x=0,1,2
- only one among these parameters can be selected
- \param[in] interrupt: the adc interrupt
- one or more parameters can be selected
- \arg ADC_INT_WDE: analog watchdog interrupt
- \arg ADC_INT_EOC: end of group conversion interrupt
- \arg ADC_INT_EOIC: end of inserted group conversion interrupt
- \param[out] none
- \retval none
-*/
-void adc_interrupt_enable(uint32_t interrupt)
-{
- if(RESET != (interrupt & ADC_INT_WDE)){
- ADC_CTL0 |= (uint32_t) ADC_CTL0_WDEIE;
- }
-
- if(RESET != (interrupt & ADC_INT_EOC)){
- ADC_CTL0 |= (uint32_t) ADC_CTL0_EOCIE;
- }
-
- if(RESET != (interrupt & ADC_INT_EOIC)){
- ADC_CTL0 |= (uint32_t) ADC_CTL0_EOICIE;
- }
-}
-
-/*!
- \brief disable ADC interrupt
- \param[in] adc_periph: ADCx,x=0,1,2
- only one among these parameters can be selected
- \param[in] interrupt: the adc interrupt flag
- one or more parameters can be selected
- \arg ADC_INT_WDE: analog watchdog interrupt flag
- \arg ADC_INT_EOC: end of group conversion interrupt flag
- \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
- \param[out] none
- \retval none
-*/
-void adc_interrupt_disable(uint32_t interrupt)
-{
- if(RESET != (interrupt & ADC_INT_WDE)){
- ADC_CTL0 &= ~(uint32_t) ADC_CTL0_WDEIE;
- }
-
- if(RESET != (interrupt & ADC_INT_EOC)){
- ADC_CTL0 &= ~(uint32_t) ADC_CTL0_EOCIE;
- }
-
- if(RESET != (interrupt & ADC_INT_EOIC)){
- ADC_CTL0 &= ~(uint32_t) ADC_CTL0_EOICIE;
- }
-}
-
-/*!
- \brief ADC analog watchdog single channel config
- \param[in] channel: the selected ADC channel
- \arg ADC_CHANNEL_x: ADC Channelx(x=0..18)
- \param[out] none
- \retval none
-*/
-void adc_watchdog_single_channel_enable(uint8_t channel)
-{
- ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
-
- ADC_CTL0 |= (uint32_t)channel;
- ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
-}
-
-/*!
- \brief adc analog watchdog group channel config
- \param[in] adc_channel_group: the channel group use analog watchdog
- \arg ADC_REGULAR_CHANNEL: regular channel group
- \arg ADC_INSERTED_CHANNEL: inserted channel group
- \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
- \param[out] none
- \retval none
-*/
-void adc_watchdog_group_channel_enable(uint8_t channel_group)
-{
- ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
- /* select the group */
- switch(channel_group){
- case ADC_REGULAR_CHANNEL:
- ADC_CTL0 |= (uint32_t) ADC_CTL0_RWDEN;
- break;
- case ADC_INSERTED_CHANNEL:
- ADC_CTL0 |= (uint32_t) ADC_CTL0_IWDEN;
- break;
- case ADC_REGULAR_INSERTED_CHANNEL:
- ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
- break;
- default:
- break;
- }
-}
-
-
-
-/*!
- \brief ADC analog watchdog disable
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_watchdog_disable(void)
-{
- ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
-}
-
-/*!
- \brief ADC analog watchdog threshold config
- \param[in] low_threshold: analog watchdog low threshold
- \param[in] high_threshold: analog watchdog high threshold
- \param[out] none
- \retval none
-*/
-void adc_watchdog_threshold_config(uint16_t low_threshold,uint16_t high_threshold)
-{
- ADC_WDLT = (uint32_t)low_threshold;
- ADC_WDHT = (uint32_t)high_threshold;
-}
-
-#ifdef GD32F170_190
-/*!
- \brief adc resolution config
- \param[in] resolution: ADC resolution
- \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
- \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
- \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
- \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
- \param[out] none
- \retval none
-*/
-void adc_resolution_config(uint32_t resolution)
-{
- ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
- ADC_CTL0 |= (uint32_t)resolution;
-}
-
-/*!
- \brief adc oversample mode config
- \param[in] mode: ADC oversampling mode
- \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel
- are done consecutively after a trigger
- \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel
- needs a trigger
- \param[in] shift: ADC oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
- \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
- \param[in] ratio: ADC oversampling ratio
- \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2
- \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4
- \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8
- \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16
- \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32
- \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64
- \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128
- \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256
- \param[out] none
- \retval none
-*/
-void adc_oversample_mode_config(uint8_t mode, uint16_t shift,uint8_t ratio)
-{
- if(mode){
- ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
- }else{
- ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
- }
- /* config the shift and ratio */
- ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
- ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
-}
-
-/*!
- \brief enable ADC oversample mode
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_oversample_mode_enable(void)
-{
- ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
-}
-
-/*!
- \brief disable ADC oversample mode
- \param[in] none
- \param[out] none
- \retval none
-*/
-void adc_oversample_mode_disable(void)
-{
- ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
-}
-#endif /* GD32F170_190 */
+/*!
+ \file gd32f1x0_adc.c
+ \brief ADC driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_adc.h"
+
+/*!
+ \brief ADC reset
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_ADCRST);
+ rcu_periph_reset_disable(RCU_ADCRST);
+}
+
+/*!
+ \brief enable ADC interface
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_enable(void)
+{
+ if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){
+ ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON;
+ }
+}
+
+/*!
+ \brief disable ADC interface
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_disable(void)
+{
+ ADC_CTL1 &= (uint32_t)~(ADC_CTL1_ADCON);
+}
+
+/*!
+ \brief ADC calibration and reset calibration
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_calibration_enable(void)
+{
+ /* reset the selected ADC1 calibration registers */
+ ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB;
+ /* check the RSTCLB bit state */
+ while((ADC_CTL1 & ADC_CTL1_RSTCLB)){
+ }
+ /* enable ADC calibration process */
+ ADC_CTL1 |= ADC_CTL1_CLB;
+ /* check the CLB bit state */
+ while((ADC_CTL1 & ADC_CTL1_CLB)){
+ }
+}
+
+/*!
+ \brief enable DMA request
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_dma_mode_enable(void)
+{
+ ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA);
+}
+
+/*!
+ \brief disable DMA request
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_dma_mode_disable(void)
+{
+ ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA);
+}
+
+/*!
+ \brief enable ADC0 temperature sensor and Vrefint channel
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_tempsensor_vrefint_enable(void)
+{
+ /* enable the temperature sensor and Vrefint channel */
+ ADC_CTL1 |= ADC_CTL1_TSVREN;
+}
+
+/*!
+ \brief disable ADC0 temperature sensor and Vrefint channel
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_tempsensor_vrefint_disable(void)
+{
+ /* disable the temperature sensor and Vrefint channel */
+ ADC_CTL1 &= ~ADC_CTL1_TSVREN;
+}
+
+/*!
+ \brief enable the vbat channel
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_vbat_enable(void)
+{
+ /* enable the vbat channel */
+ ADC_CTL1 |= ADC_CTL1_VBETEN;
+}
+
+/*!
+ \brief disable the vbat channel
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_vbat_disable(void)
+{
+ /* disable the vbat channel */
+ ADC_CTL1 &= ~ADC_CTL1_VBETEN;
+}
+
+/*!
+ \brief adc discontinuous mode config
+ \param[in] channel_group: select the channel group
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
+ for regular channel ,the number is insignificant for inserted channel
+ \param[out] none
+ \retval none
+*/
+void adc_discontinuous_mode_config(uint8_t channel_group,uint8_t length)
+{
+ ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
+ switch(channel_group){
+ case ADC_REGULAR_CHANNEL:
+ /* config the number of conversions in discontinuous mode */
+ ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM);
+ ADC_CTL0 |= (uint32_t)(((uint32_t)length - 1U) << 13U);
+
+ ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC;
+ break;
+ case ADC_INSERTED_CHANNEL:
+ ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief enable or disable ADC special function
+ \param[in] function: the function to config
+ one or more parameters can be selected below
+ \arg ADC_SCAN_MODE: scan mode select
+ \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
+ \arg ADC_CONTINUOUS_MODE: continuous mode select
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void adc_special_function_config(uint32_t function, ControlStatus newvalue)
+{
+ if(newvalue){
+ if(RESET != (function & ADC_SCAN_MODE)){
+ ADC_CTL0 |= ADC_SCAN_MODE;
+ }
+ if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
+ ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO;
+ }
+ if(RESET != (function & ADC_CONTINUOUS_MODE)){
+ ADC_CTL1 |= ADC_CONTINUOUS_MODE;
+ }
+ }else{
+ if(RESET != (function & ADC_SCAN_MODE)){
+ ADC_CTL0 &= ~ADC_SCAN_MODE;
+ }
+ if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){
+ ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO;
+ }
+ if(RESET != (function & ADC_CONTINUOUS_MODE)){
+ ADC_CTL1 &= ~ADC_CONTINUOUS_MODE;
+ }
+ }
+}
+
+/*!
+ \brief adc data alignment config
+ \param[in] data_alignment: data alignment select
+ only one parameter can be selected
+ \arg ADC_DATAALIGN_RIGHT: LSB alignment
+ \arg ADC_DATAALIGN_LEFT: MSB alignment
+ \param[out] none
+ \retval none
+*/
+void adc_data_alignment_config(uint32_t data_alignment)
+{
+ if(data_alignment){
+ ADC_CTL1 |= ADC_CTL1_DAL;
+ }else{
+ ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL);
+ }
+}
+
+/*!
+ \brief config the length of regular channel group or inserted channel group
+ \param[in] channel_group: select the channel group
+ only one parameter can be selected
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] length: the length of the channel
+ regular channel 1-17
+ inserted channel 1-4
+ \param[out] none
+ \retval none
+*/
+void adc_channel_length_config(uint8_t channel_group,uint32_t length)
+{
+ switch(channel_group){
+ case ADC_REGULAR_CHANNEL:
+ ADC_RSQ0 &= ~(((uint32_t)length - 1U) << 20U);
+ ADC_RSQ0 |= (((uint32_t)length - 1U) << 20U);
+ break;
+ case ADC_INSERTED_CHANNEL:
+ ADC_ISQ &= ~(((uint32_t)length - 1U) << 20U);
+ ADC_ISQ |= (((uint32_t)length - 1U) << 20U);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief ADC regular channel config
+ \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15
+ \param[in] channel: the selected ADC channel
+ \arg ADC_CHANNEL_x(x=0..18): ADC Channelx
+ \param[in] sample_time: the sample time value
+ \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
+ \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
+ \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
+ \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
+ \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
+ \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
+ \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
+ \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
+ \param[out] none
+ \retval none
+*/
+void adc_regular_channel_config(uint8_t rank, uint8_t channel,uint32_t sample_time)
+{
+ uint32_t rsq,sampt;
+
+#ifdef GD32F130_150
+ if(ADC_CHANNEL_18 == channel){
+ channel = ADC_CHANNEL_0;
+ }
+#endif
+
+ /* configure ADC regular sequence */
+ if(rank < 6U){
+ rsq = ADC_RSQ2;
+ rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank)));
+ rsq |= ((uint32_t)channel << (5U*rank));
+ ADC_RSQ2 = rsq;
+ }else if(rank < 12U){
+ rsq = ADC_RSQ1;
+ rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U))));
+ rsq |= ((uint32_t)channel << (5U*(rank-6U)));
+ ADC_RSQ1 = rsq;
+ }else if(rank < 16U){
+ rsq = ADC_RSQ0;
+ rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U))));
+ rsq |= ((uint32_t)channel << (5U*(rank-12U)));
+ ADC_RSQ0 = rsq;
+ }else{
+ /* illegal parameters */
+ }
+
+ /* configure ADC sampling time */
+ if(channel < 10U){
+ sampt = ADC_SAMPT1;
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
+ sampt |= (uint32_t)(sample_time << (3U*channel));
+ ADC_SAMPT1 = sampt;
+ }else if(channel < 18U){
+ sampt = ADC_SAMPT0;
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
+ sampt |= (uint32_t)(sample_time << (3U*(channel-10U)));
+ ADC_SAMPT0 = sampt;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief ADC inserted channel config
+ \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
+ \param[in] channel: the selected ADC channel
+ \arg ADC_CHANNEL_x(x=0..18): ADC Channelx
+ \param[in] sample_time: The sample time value
+ \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
+ \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
+ \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
+ \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
+ \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
+ \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
+ \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
+ \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
+ \param[out] none
+ \retval none
+*/
+void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time)
+{
+ uint8_t inserted_length;
+ uint32_t isq,sampt;
+
+ inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20, 21);
+ if(rank < 5U){
+ isq = ADC_ISQ;
+ isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U)));
+ isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U));
+ ADC_ISQ = isq;
+ }
+
+ if(channel < 10U){
+ sampt = ADC_SAMPT1;
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel)));
+ sampt |= (uint32_t) sample_time << (3U*channel);
+ ADC_SAMPT1 = sampt;
+ }else if(channel < 19U){
+ sampt = ADC_SAMPT0;
+ sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U))));
+ sampt |= ((uint32_t)sample_time << (3U*(channel-10U)));
+ ADC_SAMPT0 = sampt;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief adc inserted channel offset config
+ \param[in] inserted_channel : insert channel select
+ \arg ADC_INSERTED_CHANNEL_0: inserted channel0
+ \arg ADC_INSERTED_CHANNEL_1: inserted channel1
+ \arg ADC_INSERTED_CHANNEL_2: inserted channel2
+ \arg ADC_INSERTED_CHANNEL_3: inserted channel3
+ \param[in] offset : the offset data
+ \param[out] none
+ \retval the conversion value
+*/
+void adc_inserted_channel_offset_config(uint8_t inserted_channel,uint16_t offset)
+{
+ uint8_t inserted_length;
+ uint32_t num = 0U;
+
+ inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U);
+ num = 3U - (inserted_length - inserted_channel);
+
+ if(num <= 3U){
+ /* calculate the offset of the register */
+ num = num * 4U;
+ /* config the offset of the selected channels */
+ REG32((ADC_BASE) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
+ }
+}
+
+/*!
+ \brief adc external trigger enable
+ \param[in] adc_channel_group: select the channel group
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void adc_external_trigger_config(uint8_t channel_group,ControlStatus newvalue)
+{
+ if(newvalue){
+ if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
+ ADC_CTL1 |= ADC_CTL1_ETERC;
+ }
+ if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
+ ADC_CTL1 |= ADC_CTL1_ETEIC;
+ }
+ }else{
+ if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
+ ADC_CTL1 &= ~ADC_CTL1_ETERC;
+ }
+ if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
+ ADC_CTL1 &= ~ADC_CTL1_ETEIC;
+ }
+ }
+}
+
+/*!
+ \brief adc external trigger source config
+ \param[in] adc_channel_group: select the channel group
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[in] external_trigger_source: regular or inserted group trigger source
+ for regular channel:
+ \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CH0 event select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CH1 event select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CH2 event select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CH1 event select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_T2_TRGO: external trigger timer 2 TRGO event select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_T14_CH0: external trigger timer 14 CH0 event select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_EXT_IT11: external trigger extiline 11 select for regular channel
+ \arg ADC_EXTTRIG_REGULAR_SWRCST: software trigger select for regular channel
+ for inserted channel:
+ \arg ADC_EXTTRIG_INSERTED_T0_TRGO: external trigger timer0 TRGO event select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_T0_CH3: external trigger timer0 CH3 event select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_T1_TRGO: external trigger timer1 TRGO event select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_T1_CH0: external trigger timer1 CH0 event select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_T2_CH3: external trigger timer2 CH3 event select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_T14_TRGO: external trigger timer14 TRGO event select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_EXT_IT15: external interrupt line 15 select for inserted channel
+ \arg ADC_EXTTRIG_INSERTED_SWRCST: software trigger select for inserted channel
+ \param[out] none
+ \retval none
+*/
+void adc_external_trigger_source_config(uint8_t channel_group,uint32_t external_trigger_source)
+{
+ switch(channel_group){
+ case ADC_REGULAR_CHANNEL:
+ ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC);
+ ADC_CTL1 |= (uint32_t)external_trigger_source;
+ break;
+ case ADC_INSERTED_CHANNEL:
+ ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC);
+ ADC_CTL1 |= (uint32_t)external_trigger_source;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief adc software trigger enable
+ \param[in] adc_channel_group: select the channel group
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \param[out] none
+ \retval none
+*/
+void adc_software_trigger_enable(uint8_t channel_group)
+{
+ if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){
+ ADC_CTL1 |= ADC_CTL1_SWRCST;
+ }
+ if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){
+ ADC_CTL1 |= ADC_CTL1_SWICST;
+ }
+}
+
+/*!
+ \brief adc regular group data register read
+ \param[in] none
+ \param[out] none
+ \retval the conversion value
+*/
+uint16_t adc_regular_data_read(void)
+{
+ return (uint16_t)(ADC_RDATA);
+}
+
+/*!
+ \brief adc inserted group data register read
+ \param[in] inserted_channel : insert channel select
+ \arg ADC_INSERTED_CHANNEL_0: inserted channel0
+ \arg ADC_INSERTED_CHANNEL_1: inserted channel1
+ \arg ADC_INSERTED_CHANNEL_2: inserted channel2
+ \arg ADC_INSERTED_CHANNEL_3: inserted channel3
+ \param[out] none
+ \retval the conversion value
+*/
+uint16_t adc_inserted_data_read(uint8_t inserted_channel)
+{
+ uint32_t idata;
+ /* read the data of the selected channel */
+ switch(inserted_channel){
+ case ADC_INSERTED_CHANNEL_0:
+ idata = ADC_IDATA0;
+ break;
+ case ADC_INSERTED_CHANNEL_1:
+ idata = ADC_IDATA1;
+ break;
+ case ADC_INSERTED_CHANNEL_2:
+ idata = ADC_IDATA2;
+ break;
+ case ADC_INSERTED_CHANNEL_3:
+ idata = ADC_IDATA3;
+ break;
+ default:
+ idata = 0U;
+ break;
+ }
+ return (uint16_t)idata;
+}
+
+/*!
+ \brief get the ADC flag bits
+ \param[in] flag: the adc flag bits
+ \arg ADC_FLAG_WDE: analog watchdog event flag
+ \arg ADC_FLAG_EOC: end of group conversion flag
+ \arg ADC_FLAG_EOIC: end of inserted group conversion flag
+ \arg ADC_FLAG_STIC: start flag of inserted channel group
+ \arg ADC_FLAG_STRC: start flag of regular channel group
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus adc_flag_get(uint32_t flag)
+{
+ FlagStatus reval = RESET;
+
+ if(ADC_STAT & flag){
+ reval = SET;
+ }
+ return reval;
+
+}
+
+/*!
+ \brief clear the ADC status flag
+ \param[in] flag: the adc flag bits
+ \arg ADC_FLAG_WDE: analog watchdog event flag
+ \arg ADC_FLAG_EOC: end of group conversion flag
+ \arg ADC_FLAG_EOIC: end of inserted group conversion flag
+ \arg ADC_FLAG_STIC: start flag of inserted channel group
+ \arg ADC_FLAG_STRC: start flag of regular channel group
+ \param[out] none
+ \retval none
+*/
+void adc_flag_clear(uint32_t flag)
+{
+ ADC_STAT &= ~((uint32_t)flag);
+}
+
+/*!
+ \brief get the ADC interrupt bits
+ \param[in] flag: the adc interrupt flag
+ \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag
+ \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
+ \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus adc_interrupt_flag_get(uint32_t flag)
+{
+ FlagStatus interrupt_flag = RESET;
+ uint32_t state;
+ /* check the interrupt bits */
+ switch(flag){
+ case ADC_INT_FLAG_WDE:
+ state = ADC_STAT & ADC_STAT_WDE;
+ if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){
+ interrupt_flag = SET;
+ }
+ break;
+ case ADC_INT_FLAG_EOC:
+ state = ADC_STAT & ADC_STAT_EOC;
+ if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){
+ interrupt_flag = SET;
+ }
+ break;
+ case ADC_INT_FLAG_EOIC:
+ state = ADC_STAT & ADC_STAT_EOIC;
+ if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){
+ interrupt_flag = SET;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return interrupt_flag;
+}
+
+/*!
+ \brief clear the ADC interrupt bits
+ \param[in] adc_interrupt: the adc interrupt bits
+ \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag
+ \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag
+ \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag
+ \param[out] none
+ \retval none
+*/
+void adc_interrupt_flag_clear(uint32_t flag)
+{
+ ADC_STAT &= ~((uint32_t)flag);
+}
+
+/*!
+ \brief enable ADC interrupt
+ \param[in] adc_periph: ADCx, x=0,1,2
+ only one among these parameters can be selected
+ \param[in] interrupt: the adc interrupt
+ one or more parameters can be selected
+ \arg ADC_INT_WDE: analog watchdog interrupt
+ \arg ADC_INT_EOC: end of group conversion interrupt
+ \arg ADC_INT_EOIC: end of inserted group conversion interrupt
+ \param[out] none
+ \retval none
+*/
+void adc_interrupt_enable(uint32_t interrupt)
+{
+ if(RESET != (interrupt & ADC_INT_WDE)){
+ ADC_CTL0 |= (uint32_t) ADC_CTL0_WDEIE;
+ }
+
+ if(RESET != (interrupt & ADC_INT_EOC)){
+ ADC_CTL0 |= (uint32_t) ADC_CTL0_EOCIE;
+ }
+
+ if(RESET != (interrupt & ADC_INT_EOIC)){
+ ADC_CTL0 |= (uint32_t) ADC_CTL0_EOICIE;
+ }
+}
+
+/*!
+ \brief disable ADC interrupt
+ \param[in] adc_periph: ADCx,x=0,1,2
+ only one among these parameters can be selected
+ \param[in] interrupt: the adc interrupt flag
+ one or more parameters can be selected
+ \arg ADC_INT_WDE: analog watchdog interrupt flag
+ \arg ADC_INT_EOC: end of group conversion interrupt flag
+ \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
+ \param[out] none
+ \retval none
+*/
+void adc_interrupt_disable(uint32_t interrupt)
+{
+ if(RESET != (interrupt & ADC_INT_WDE)){
+ ADC_CTL0 &= ~(uint32_t) ADC_CTL0_WDEIE;
+ }
+
+ if(RESET != (interrupt & ADC_INT_EOC)){
+ ADC_CTL0 &= ~(uint32_t) ADC_CTL0_EOCIE;
+ }
+
+ if(RESET != (interrupt & ADC_INT_EOIC)){
+ ADC_CTL0 &= ~(uint32_t) ADC_CTL0_EOICIE;
+ }
+}
+
+/*!
+ \brief ADC analog watchdog single channel config
+ \param[in] channel: the selected ADC channel
+ \arg ADC_CHANNEL_x: ADC Channelx(x=0..18)
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_single_channel_enable(uint8_t channel)
+{
+ ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+
+ ADC_CTL0 |= (uint32_t)channel;
+ ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+}
+
+/*!
+ \brief adc analog watchdog group channel config
+ \param[in] adc_channel_group: the channel group use analog watchdog
+ \arg ADC_REGULAR_CHANNEL: regular channel group
+ \arg ADC_INSERTED_CHANNEL: inserted channel group
+ \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_group_channel_enable(uint8_t channel_group)
+{
+ ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
+ /* select the group */
+ switch(channel_group){
+ case ADC_REGULAR_CHANNEL:
+ ADC_CTL0 |= (uint32_t) ADC_CTL0_RWDEN;
+ break;
+ case ADC_INSERTED_CHANNEL:
+ ADC_CTL0 |= (uint32_t) ADC_CTL0_IWDEN;
+ break;
+ case ADC_REGULAR_INSERTED_CHANNEL:
+ ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+/*!
+ \brief ADC analog watchdog disable
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_disable(void)
+{
+ ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
+}
+
+/*!
+ \brief ADC analog watchdog threshold config
+ \param[in] low_threshold: analog watchdog low threshold
+ \param[in] high_threshold: analog watchdog high threshold
+ \param[out] none
+ \retval none
+*/
+void adc_watchdog_threshold_config(uint16_t low_threshold,uint16_t high_threshold)
+{
+ ADC_WDLT = (uint32_t)low_threshold;
+ ADC_WDHT = (uint32_t)high_threshold;
+}
+
+#ifdef GD32F170_190
+/*!
+ \brief adc resolution config
+ \param[in] resolution: ADC resolution
+ \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
+ \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
+ \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
+ \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
+ \param[out] none
+ \retval none
+*/
+void adc_resolution_config(uint32_t resolution)
+{
+ ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES);
+ ADC_CTL0 |= (uint32_t)resolution;
+}
+
+/*!
+ \brief adc oversample mode config
+ \param[in] mode: ADC oversampling mode
+ \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel
+ are done consecutively after a trigger
+ \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel
+ needs a trigger
+ \param[in] shift: ADC oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
+ \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
+ \param[in] ratio: ADC oversampling ratio
+ \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2
+ \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4
+ \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8
+ \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16
+ \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32
+ \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64
+ \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128
+ \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256
+ \param[out] none
+ \retval none
+*/
+void adc_oversample_mode_config(uint8_t mode, uint16_t shift,uint8_t ratio)
+{
+ if(mode){
+ ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS;
+ }else{
+ ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
+ }
+ /* config the shift and ratio */
+ ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
+ ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio);
+}
+
+/*!
+ \brief enable ADC oversample mode
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_oversample_mode_enable(void)
+{
+ ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN;
+}
+
+/*!
+ \brief disable ADC oversample mode
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void adc_oversample_mode_disable(void)
+{
+ ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
+}
+#endif /* GD32F170_190 */
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_dbg.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_dbg.c
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_dbg.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_dbg.c
index 8ecb4522..05e649bb 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_dbg.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_dbg.c
@@ -1,106 +1,106 @@
-/*!
- \file gd32f1x0_dbg.c
- \brief DBG driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_dbg.h"
-
-#define DBG_RESET_VAL 0x00000000U
-
-/*!
- \brief deinitialize the DBG
- \param[in] none
- \param[out] none
- \retval none
-*/
-void dbg_deinit(void)
-{
- DBG_CTL0 = DBG_RESET_VAL;
- DBG_CTL1 = DBG_RESET_VAL;
-}
-
-/*!
- \brief read DBG_ID code register
- \param[in] none
- \param[out] none
- \retval DBG_ID code
-*/
-uint32_t dbg_id_get(void)
-{
- return DBG_ID;
-}
-
-/*!
- \brief enable low power behavior when the mcu is in debug mode
- \param[in] dbg_low_power:
- this parameter can be any combination of the following values:
- \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
- \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
- \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
- \param[out] none
- \retval none
-*/
-void dbg_low_power_enable(uint32_t dbg_low_power)
-{
- DBG_CTL0 |= dbg_low_power;
-}
-
-/*!
- \brief disable low power behavior when the mcu is in debug mode
- \param[in] dbg_low_power:
- this parameter can be any combination of the following values:
- \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
- \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
- \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
- \param[out] none
- \retval none
-*/
-void dbg_low_power_disable(uint32_t dbg_low_power)
-{
- DBG_CTL0 &= ~dbg_low_power;
-}
-
-/*!
- \brief enable peripheral behavior when the mcu is in debug mode
- \param[in] dbg_periph: refer to dbg_periph_enum
- only one parameter can be selected which is shown as below:
- \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
- \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
- \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
- \arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
- \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
- \arg DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
- \param[out] none
- \retval none
-*/
-void dbg_periph_enable(dbg_periph_enum dbg_periph)
-{
- DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
-}
-
-/*!
- \brief disable peripheral behavior when the mcu is in debug mode
- \param[in] dbg_periph: refer to dbg_periph_enum
- only one parameter can be selected which is shown as below:
- \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
- \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
- \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
- \arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
- \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
- \arg DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
- \param[out] none
- \retval none
-*/
-void dbg_periph_disable(dbg_periph_enum dbg_periph)
-{
- DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
-}
+/*!
+ \file gd32f1x0_dbg.c
+ \brief DBG driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_dbg.h"
+
+#define DBG_RESET_VAL 0x00000000U
+
+/*!
+ \brief deinitialize the DBG
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void dbg_deinit(void)
+{
+ DBG_CTL0 = DBG_RESET_VAL;
+ DBG_CTL1 = DBG_RESET_VAL;
+}
+
+/*!
+ \brief read DBG_ID code register
+ \param[in] none
+ \param[out] none
+ \retval DBG_ID code
+*/
+uint32_t dbg_id_get(void)
+{
+ return DBG_ID;
+}
+
+/*!
+ \brief enable low power behavior when the mcu is in debug mode
+ \param[in] dbg_low_power:
+ this parameter can be any combination of the following values:
+ \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
+ \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
+ \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
+ \param[out] none
+ \retval none
+*/
+void dbg_low_power_enable(uint32_t dbg_low_power)
+{
+ DBG_CTL0 |= dbg_low_power;
+}
+
+/*!
+ \brief disable low power behavior when the mcu is in debug mode
+ \param[in] dbg_low_power:
+ this parameter can be any combination of the following values:
+ \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
+ \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
+ \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
+ \param[out] none
+ \retval none
+*/
+void dbg_low_power_disable(uint32_t dbg_low_power)
+{
+ DBG_CTL0 &= ~dbg_low_power;
+}
+
+/*!
+ \brief enable peripheral behavior when the mcu is in debug mode
+ \param[in] dbg_periph: refer to dbg_periph_enum
+ only one parameter can be selected which is shown as below:
+ \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+ \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+ \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
+ \arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
+ \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
+ \arg DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
+ \param[out] none
+ \retval none
+*/
+void dbg_periph_enable(dbg_periph_enum dbg_periph)
+{
+ DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
+}
+
+/*!
+ \brief disable peripheral behavior when the mcu is in debug mode
+ \param[in] dbg_periph: refer to dbg_periph_enum
+ only one parameter can be selected which is shown as below:
+ \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
+ \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
+ \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
+ \arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
+ \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
+ \arg DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
+ \param[out] none
+ \retval none
+*/
+void dbg_periph_disable(dbg_periph_enum dbg_periph)
+{
+ DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_dma.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_dma.c
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_dma.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_dma.c
index 43f7321d..4cec0fc8 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_dma.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_dma.c
@@ -1,492 +1,492 @@
-/*!
- \file gd32f1x0_dma.c
- \brief DMA driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_dma.h"
-
-/*!
- \brief deinitialize DMA a channel registers
- \param[in] channelx: specify which DMA channel is deinitialized
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_deinit(dma_channel_enum channelx)
-{
- /* disable DMA a channel */
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
- /* reset DMA channel registers */
- DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
- DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
- DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
- DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
- DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
-}
-
-/*!
- \brief initialize DMA channel
- \param[in] channelx: specify which DMA channel is initialized
- \arg DMA_CHx(x=0..6)
- \param[in] init_struct: the data needed to initialize DMA channel
- periph_addr: peripheral base address
- periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
- periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
- memory_addr: memory base address
- memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
- memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
- direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
- number: the number of remaining data to be transferred by the DMA
- priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
- \param[out] none
- \retval none
-*/
-void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct)
-{
- uint32_t ctl;
- /* configure peripheral base address */
- DMA_CHPADDR(channelx) = init_struct.periph_addr;
-
- /* configure memory base address */
- DMA_CHMADDR(channelx) = init_struct.memory_addr;
-
- /* configure the number of remaining data to be transferred */
- DMA_CHCNT(channelx) = init_struct.number;
-
- /* configure peripheral transfer width,memory transfer width, */
- ctl = DMA_CHCTL(channelx);
- ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
- ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
- DMA_CHCTL(channelx)=ctl;
-
- /* configure peripheral increasing mode */
- if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
- DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
- }else{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
- }
-
- /* configure memory increasing mode */
- if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
- DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
- }else{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
- }
-
- /* configure the direction of data transfer */
- if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
- }else{
- DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
- }
-}
-
-/*!
- \brief enable DMA circulation mode
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_circulation_enable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
-}
-
-/*!
- \brief disable DMA circulation mode
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_circulation_disable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
-}
-
-/*!
- \brief enable memory to memory mode
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_memory_to_memory_enable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
-}
-
-/*!
- \brief disable memory to memory mode
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_memory_to_memory_disable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
-}
-
-/*!
- \brief enable DMA channel
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_channel_enable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
-}
-
-/*!
- \brief disable DMA channel
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_channel_disable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
-}
-
-/*!
- \brief set DMA peripheral base address
- \param[in] channelx: specify which DMA channel to set peripheral base address
- \arg DMA_CHx(x=0..6)
- \param[in] address: peripheral base address
- \param[out] none
- \retval none
-*/
-void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
-{
- DMA_CHPADDR(channelx) = address;
-}
-
-/*!
- \brief set DMA Memory base address
- \param[in] channelx: specify which DMA channel to set Memory base address
- \arg DMA_CHx(x=0..6)
- \param[in] address: Memory base address
- \param[out] none
- \retval none
-*/
-void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
-{
- DMA_CHMADDR(channelx) = address;
-}
-
-/*!
- \brief set the number of remaining data to be transferred by the DMA
- \param[in] channelx: specify which DMA channel to set number
- \arg DMA_CHx(x=0..6)
- \param[in] number: the number of remaining data to be transferred by the DMA
- \param[out] none
- \retval none
-*/
-void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
-{
- DMA_CHCNT(channelx) = number;
-}
-
-/*!
- \brief get the number of remaining data to be transferred by the DMA
- \param[in] channelx: specify which DMA channel to set number
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval uint32_t: the number of remaining data to be transferred by the DMA
-*/
-uint32_t dma_transfer_number_get(dma_channel_enum channelx)
-{
- return (uint32_t)DMA_CHCNT(channelx);
-}
-
-/*!
- \brief configure priority level of DMA channel
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[in] priority: priority Level of this channel
- \arg DMA_PRIORITY_LOW: low priority
- \arg DMA_PRIORITY_MEDIUM: medium priority
- \arg DMA_PRIORITY_HIGH: high priority
- \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
- \param[out] none
- \retval none
-*/
-void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
-{
- uint32_t ctl;
- /* acquire DMA_CHxCTL register */
- ctl = DMA_CHCTL(channelx);
- /* assign regiser */
- ctl &= ~DMA_CHXCTL_PRIO;
- ctl |= priority;
- DMA_CHCTL(channelx) = ctl;
-}
-
-/*!
- \brief configure transfer data size of memory
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[in] msize: transfer data size of memory
- \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
- \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
- \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
- \param[out] none
- \retval none
-*/
-void dma_memory_width_config (dma_channel_enum channelx, uint32_t msize)
-{
- uint32_t ctl;
- /* acquire DMA_CHxCTL register */
- ctl = DMA_CHCTL(channelx);
- /* assign regiser */
- ctl &= ~DMA_CHXCTL_MWIDTH;
- ctl |= msize;
- DMA_CHCTL(channelx) = ctl;
-}
-
-/*!
- \brief configure transfer data size of peripheral
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[in] msize: transfer data size of peripheral
- \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
- \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
- \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
- \param[out] none
- \retval none
-*/
-void dma_periph_width_config (dma_channel_enum channelx, uint32_t psize)
-{
- uint32_t ctl;
- /* acquire DMA_CHxCTL register */
- ctl = DMA_CHCTL(channelx);
- /* assign regiser */
- ctl &= ~DMA_CHXCTL_PWIDTH;
- ctl |= psize;
- DMA_CHCTL(channelx) = ctl;
-}
-
-/*!
- \brief enable next address increasement algorithm of memory
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_memory_increase_enable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
-}
-
-/*!
- \brief disable next address increasement algorithm of memory
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_memory_increase_disable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
-}
-
-/*!
- \brief enable next address increasement algorithm of peripheral
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_periph_increase_enable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
-}
-
-/*!
- \brief disable next address increasement algorithm of peripheral
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[out] none
- \retval none
-*/
-void dma_periph_increase_disable(dma_channel_enum channelx)
-{
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
-}
-
-/*!
- \brief configure the direction of data transfer on the channel
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[in] direction: specify the direction of data transfer
- \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
- \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
- \param[out] none
- \retval none
-*/
-void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction)
-{
- if(DMA_PERIPHERAL_TO_MEMORY == direction){
- DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
- } else {
- DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
- }
-}
-
-/*!
- \brief check DMA flag and interrupt enable bit is set or not
- \param[in] channelx: specify which DMA channel to get flag
- \arg DMA_CHx(x=0..6)
- \param[in] flag: specify get which flag
- only one parameter can be selected which is shown as below:
- \arg DMA_INT_FLAG_G: global interrupt flag of channel
- \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
- \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
- \arg DMA_INT_FLAG_ERR: error interrupt flag of channel
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
-{
- uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
- uint32_t gif_check = 0x0FU, gif_enable = 0x0EU;
-
- switch(flag){
- case DMA_INT_FLAG_FTF:
- interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
- interrupt_flag = interrupt_flag >> ((channelx) * 4U);
- interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
- break;
- case DMA_INT_FLAG_HTF:
- interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
- interrupt_flag = interrupt_flag >> ((channelx) * 4U);
- interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
- break;
- case DMA_INT_FLAG_ERR:
- interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
- interrupt_flag = interrupt_flag >> ((channelx) * 4U);
- interrupt_enable = DMA_CHCTL( channelx) & DMA_CHXCTL_ERRIE;
- break;
- case DMA_INT_FLAG_G:
- interrupt_flag = DMA_INTF & DMA_FLAG_ADD(gif_check, channelx);
- interrupt_flag = interrupt_flag >> ((channelx) * 4U);
- interrupt_enable = DMA_CHCTL(channelx) & gif_enable;
- break;
- default:
- break;
- }
-
- if(interrupt_flag & interrupt_enable){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear DMA a channel flag
- \param[in] channelx: specify which DMA channel to clear flag
- \arg DMA_CHx(x=0..6)
- \param[in] flag: specify get which flag
- only one parameter can be selected which is shown as below:
- \arg DMA_INT_FLAG_G: global interrupt flag of channel
- \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
- \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
- \arg DMA_INT_FLAG_ERR: error interrupt flag of channel
- \param[out] none
- \retval none
-*/
-void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
-{
- DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
-}
-
-/*!
- \brief enable DMA interrupt
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[in] source: specify which interrupt to enbale
- \arg DMA_INT_ERR: channel error interrupt
- \arg DMA_INT_HTF: channel transfer half complete interrupt
- \arg DMA_INT_FTF: channel transfer complete interrupt
- \param[out] none
- \retval none
-*/
-void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
-{
- DMA_CHCTL(channelx) |= source;
-}
-
-/*!
- \brief disable DMA interrupt
- \param[in] channelx: specify which DMA channel
- \arg DMA_CHx(x=0..6)
- \param[in] source: specify which interrupt to disbale
- \arg DMA_INT_ERR: channel error interrupt
- \arg DMA_INT_HTF: channel transfer half complete interrupt
- \arg DMA_INT_FTF: for channel transfer complete interrupt
- \param[out] none
- \retval none
-*/
-void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
-{
- DMA_CHCTL(channelx) &= ~source;
-}
-
-/*!
- \brief check DMA flag is set or not
- \param[in] channelx: specify which DMA channel to get flag
- \arg DMA_CHx(x=0..6)
- \param[in] flag: specify get which flag
- only one parameter can be selected which is shown as below:
- \arg DMA_FLAG_G: global interrupt flag of channel
- \arg DMA_FLAG_FTF: full transfer finish flag of channel
- \arg DMA_FLAG_HTF: half transfer finish flag of channel
- \arg DMA_FLAG_ERR: error flag of channel
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
-{
- FlagStatus reval;
-
- if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
- reval = SET;
- }else{
- reval = RESET;
- }
-
- return reval;
-}
-
-/*!
- \brief clear DMA a channel flag
- \param[in] channelx: specify which DMA channel to clear flag
- \arg DMA_CHx(x=0..6)
- \param[in] flag: specify get which flag
- only one parameter can be selected which is shown as below:
- \arg DMA_FLAG_G: global interrupt flag of channel
- \arg DMA_FLAG_FTF: full transfer finish flag of channel
- \arg DMA_FLAG_HTF: half transfer finish flag of channel
- \arg DMA_FLAG_ERR: error flag of channel
- \param[out] none
- \retval none
-*/
-void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
-{
- DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
-}
+/*!
+ \file gd32f1x0_dma.c
+ \brief DMA driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_dma.h"
+
+/*!
+ \brief deinitialize DMA a channel registers
+ \param[in] channelx: specify which DMA channel is deinitialized
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_deinit(dma_channel_enum channelx)
+{
+ /* disable DMA a channel */
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
+ /* reset DMA channel registers */
+ DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
+ DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
+ DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
+ DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
+ DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
+}
+
+/*!
+ \brief initialize DMA channel
+ \param[in] channelx: specify which DMA channel is initialized
+ \arg DMA_CHx(x=0..6)
+ \param[in] init_struct: the data needed to initialize DMA channel
+ periph_addr: peripheral base address
+ periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
+ periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
+ memory_addr: memory base address
+ memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
+ memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
+ direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
+ number: the number of remaining data to be transferred by the DMA
+ priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
+ \param[out] none
+ \retval none
+*/
+void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct)
+{
+ uint32_t ctl;
+ /* configure peripheral base address */
+ DMA_CHPADDR(channelx) = init_struct.periph_addr;
+
+ /* configure memory base address */
+ DMA_CHMADDR(channelx) = init_struct.memory_addr;
+
+ /* configure the number of remaining data to be transferred */
+ DMA_CHCNT(channelx) = init_struct.number;
+
+ /* configure peripheral transfer width,memory transfer width, */
+ ctl = DMA_CHCTL(channelx);
+ ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
+ ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
+ DMA_CHCTL(channelx)=ctl;
+
+ /* configure peripheral increasing mode */
+ if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
+ }else{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
+ }
+
+ /* configure memory increasing mode */
+ if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
+ }else{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
+ }
+
+ /* configure the direction of data transfer */
+ if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
+ }else{
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
+ }
+}
+
+/*!
+ \brief enable DMA circulation mode
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_circulation_enable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
+}
+
+/*!
+ \brief disable DMA circulation mode
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_circulation_disable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
+}
+
+/*!
+ \brief enable memory to memory mode
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_to_memory_enable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
+}
+
+/*!
+ \brief disable memory to memory mode
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_to_memory_disable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
+}
+
+/*!
+ \brief enable DMA channel
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_channel_enable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
+}
+
+/*!
+ \brief disable DMA channel
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_channel_disable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
+}
+
+/*!
+ \brief set DMA peripheral base address
+ \param[in] channelx: specify which DMA channel to set peripheral base address
+ \arg DMA_CHx(x=0..6)
+ \param[in] address: peripheral base address
+ \param[out] none
+ \retval none
+*/
+void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
+{
+ DMA_CHPADDR(channelx) = address;
+}
+
+/*!
+ \brief set DMA Memory base address
+ \param[in] channelx: specify which DMA channel to set Memory base address
+ \arg DMA_CHx(x=0..6)
+ \param[in] address: Memory base address
+ \param[out] none
+ \retval none
+*/
+void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
+{
+ DMA_CHMADDR(channelx) = address;
+}
+
+/*!
+ \brief set the number of remaining data to be transferred by the DMA
+ \param[in] channelx: specify which DMA channel to set number
+ \arg DMA_CHx(x=0..6)
+ \param[in] number: the number of remaining data to be transferred by the DMA
+ \param[out] none
+ \retval none
+*/
+void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
+{
+ DMA_CHCNT(channelx) = number;
+}
+
+/*!
+ \brief get the number of remaining data to be transferred by the DMA
+ \param[in] channelx: specify which DMA channel to set number
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval uint32_t: the number of remaining data to be transferred by the DMA
+*/
+uint32_t dma_transfer_number_get(dma_channel_enum channelx)
+{
+ return (uint32_t)DMA_CHCNT(channelx);
+}
+
+/*!
+ \brief configure priority level of DMA channel
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[in] priority: priority Level of this channel
+ \arg DMA_PRIORITY_LOW: low priority
+ \arg DMA_PRIORITY_MEDIUM: medium priority
+ \arg DMA_PRIORITY_HIGH: high priority
+ \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
+ \param[out] none
+ \retval none
+*/
+void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
+{
+ uint32_t ctl;
+ /* acquire DMA_CHxCTL register */
+ ctl = DMA_CHCTL(channelx);
+ /* assign regiser */
+ ctl &= ~DMA_CHXCTL_PRIO;
+ ctl |= priority;
+ DMA_CHCTL(channelx) = ctl;
+}
+
+/*!
+ \brief configure transfer data size of memory
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[in] msize: transfer data size of memory
+ \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
+ \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
+ \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
+ \param[out] none
+ \retval none
+*/
+void dma_memory_width_config (dma_channel_enum channelx, uint32_t msize)
+{
+ uint32_t ctl;
+ /* acquire DMA_CHxCTL register */
+ ctl = DMA_CHCTL(channelx);
+ /* assign regiser */
+ ctl &= ~DMA_CHXCTL_MWIDTH;
+ ctl |= msize;
+ DMA_CHCTL(channelx) = ctl;
+}
+
+/*!
+ \brief configure transfer data size of peripheral
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[in] msize: transfer data size of peripheral
+ \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
+ \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
+ \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
+ \param[out] none
+ \retval none
+*/
+void dma_periph_width_config (dma_channel_enum channelx, uint32_t psize)
+{
+ uint32_t ctl;
+ /* acquire DMA_CHxCTL register */
+ ctl = DMA_CHCTL(channelx);
+ /* assign regiser */
+ ctl &= ~DMA_CHXCTL_PWIDTH;
+ ctl |= psize;
+ DMA_CHCTL(channelx) = ctl;
+}
+
+/*!
+ \brief enable next address increasement algorithm of memory
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_increase_enable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
+}
+
+/*!
+ \brief disable next address increasement algorithm of memory
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_memory_increase_disable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
+}
+
+/*!
+ \brief enable next address increasement algorithm of peripheral
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_periph_increase_enable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
+}
+
+/*!
+ \brief disable next address increasement algorithm of peripheral
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[out] none
+ \retval none
+*/
+void dma_periph_increase_disable(dma_channel_enum channelx)
+{
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
+}
+
+/*!
+ \brief configure the direction of data transfer on the channel
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[in] direction: specify the direction of data transfer
+ \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
+ \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
+ \param[out] none
+ \retval none
+*/
+void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction)
+{
+ if(DMA_PERIPHERAL_TO_MEMORY == direction){
+ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
+ } else {
+ DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
+ }
+}
+
+/*!
+ \brief check DMA flag and interrupt enable bit is set or not
+ \param[in] channelx: specify which DMA channel to get flag
+ \arg DMA_CHx(x=0..6)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_INT_FLAG_G: global interrupt flag of channel
+ \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_ERR: error interrupt flag of channel
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
+{
+ uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
+ uint32_t gif_check = 0x0FU, gif_enable = 0x0EU;
+
+ switch(flag){
+ case DMA_INT_FLAG_FTF:
+ interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
+ interrupt_flag = interrupt_flag >> ((channelx) * 4U);
+ interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
+ break;
+ case DMA_INT_FLAG_HTF:
+ interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
+ interrupt_flag = interrupt_flag >> ((channelx) * 4U);
+ interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
+ break;
+ case DMA_INT_FLAG_ERR:
+ interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
+ interrupt_flag = interrupt_flag >> ((channelx) * 4U);
+ interrupt_enable = DMA_CHCTL( channelx) & DMA_CHXCTL_ERRIE;
+ break;
+ case DMA_INT_FLAG_G:
+ interrupt_flag = DMA_INTF & DMA_FLAG_ADD(gif_check, channelx);
+ interrupt_flag = interrupt_flag >> ((channelx) * 4U);
+ interrupt_enable = DMA_CHCTL(channelx) & gif_enable;
+ break;
+ default:
+ break;
+ }
+
+ if(interrupt_flag & interrupt_enable){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear DMA a channel flag
+ \param[in] channelx: specify which DMA channel to clear flag
+ \arg DMA_CHx(x=0..6)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_INT_FLAG_G: global interrupt flag of channel
+ \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
+ \arg DMA_INT_FLAG_ERR: error interrupt flag of channel
+ \param[out] none
+ \retval none
+*/
+void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
+{
+ DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
+}
+
+/*!
+ \brief enable DMA interrupt
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[in] source: specify which interrupt to enbale
+ \arg DMA_INT_ERR: channel error interrupt
+ \arg DMA_INT_HTF: channel transfer half complete interrupt
+ \arg DMA_INT_FTF: channel transfer complete interrupt
+ \param[out] none
+ \retval none
+*/
+void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
+{
+ DMA_CHCTL(channelx) |= source;
+}
+
+/*!
+ \brief disable DMA interrupt
+ \param[in] channelx: specify which DMA channel
+ \arg DMA_CHx(x=0..6)
+ \param[in] source: specify which interrupt to disbale
+ \arg DMA_INT_ERR: channel error interrupt
+ \arg DMA_INT_HTF: channel transfer half complete interrupt
+ \arg DMA_INT_FTF: for channel transfer complete interrupt
+ \param[out] none
+ \retval none
+*/
+void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
+{
+ DMA_CHCTL(channelx) &= ~source;
+}
+
+/*!
+ \brief check DMA flag is set or not
+ \param[in] channelx: specify which DMA channel to get flag
+ \arg DMA_CHx(x=0..6)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_FLAG_G: global interrupt flag of channel
+ \arg DMA_FLAG_FTF: full transfer finish flag of channel
+ \arg DMA_FLAG_HTF: half transfer finish flag of channel
+ \arg DMA_FLAG_ERR: error flag of channel
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
+{
+ FlagStatus reval;
+
+ if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
+ reval = SET;
+ }else{
+ reval = RESET;
+ }
+
+ return reval;
+}
+
+/*!
+ \brief clear DMA a channel flag
+ \param[in] channelx: specify which DMA channel to clear flag
+ \arg DMA_CHx(x=0..6)
+ \param[in] flag: specify get which flag
+ only one parameter can be selected which is shown as below:
+ \arg DMA_FLAG_G: global interrupt flag of channel
+ \arg DMA_FLAG_FTF: full transfer finish flag of channel
+ \arg DMA_FLAG_HTF: half transfer finish flag of channel
+ \arg DMA_FLAG_ERR: error flag of channel
+ \param[out] none
+ \retval none
+*/
+void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
+{
+ DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_fwdgt.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_fwdgt.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_fwdgt.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_fwdgt.c
index 624c0976..0c403faf 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_fwdgt.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_fwdgt.c
@@ -1,146 +1,146 @@
-/*!
- \file gd32f1x0_fwdgt.c
- \brief FWDGT driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_fwdgt.h"
-
-/*!
- \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
- \param[in] none
- \param[out] none
- \retval none
-*/
-void fwdgt_write_disable(void)
-{
- FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
-}
-
-/*!
- \brief reload the counter of FWDGT
- \param[in] none
- \param[out] none
- \retval none
-*/
-void fwdgt_counter_reload(void)
-{
- FWDGT_CTL = FWDGT_KEY_RELOAD;
-}
-
-/*!
- \brief start the free watchdog timer counter
- \param[in] none
- \param[out] none
- \retval none
-*/
-void fwdgt_enable(void)
-{
- FWDGT_CTL = FWDGT_KEY_ENABLE;
-}
-
-/*!
- \brief configure the free watchdog timer counter window value
- \param[in] window_value: specify window value(0x0000 - 0x0FFF)
- \param[out] none
- \retval ErrStatus: ERROR or SUCCESS
-*/
-ErrStatus fwdgt_window_value_config(uint16_t window_value)
-{
- uint32_t time_index = FWDGT_WND_TIMEOUT;
- uint32_t flag_status = RESET;
-
- /* enable write access to FWDGT_WND */
- FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
-
- /* wait until the WUD flag to be reset */
- do{
- flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
- }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
-
- if ((uint32_t)RESET != flag_status){
- return ERROR;
- }
-
- FWDGT_WND = WND_WND(window_value);
-
- return SUCCESS;
-}
-
-/*!
- \brief configure counter reload value, and prescaler divider value
- \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
- \param[in] prescaler_div: FWDGT prescaler value
- \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
- \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
- \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
- \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
- \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
- \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
- \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
- \param[out] none
- \retval ErrStatus: ERROR or SUCCESS
-*/
-ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
-{
- uint32_t timeout = FWDGT_PSC_TIMEOUT;
- uint32_t flag_status = RESET;
-
- /* enable write access to FWDGT_PSC,and FWDGT_RLD */
- FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
-
- /* wait until the PUD flag to be reset */
- do{
- flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
- }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
-
- if ((uint32_t)RESET != flag_status){
- return ERROR;
- }
-
- /* configure FWDGT */
- FWDGT_PSC = (uint32_t)prescaler_div;
-
- timeout = FWDGT_RLD_TIMEOUT;
- /* wait until the RUD flag to be reset */
- do{
- flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
- }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
-
- if ((uint32_t)RESET != flag_status){
- return ERROR;
- }
-
- FWDGT_RLD = RLD_RLD(reload_value);
-
- /* reload the counter */
- FWDGT_CTL = FWDGT_KEY_RELOAD;
-
- return SUCCESS;
-}
-
-/*!
- \brief get flag state of FWDGT
- \param[in] flag: flag to get
- \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
- \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
- \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus fwdgt_flag_get(uint16_t flag)
-{
- if(FWDGT_STAT & flag){
- return SET;
- }
-
- return RESET;
-}
+/*!
+ \file gd32f1x0_fwdgt.c
+ \brief FWDGT driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_fwdgt.h"
+
+/*!
+ \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_write_disable(void)
+{
+ FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
+}
+
+/*!
+ \brief reload the counter of FWDGT
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_counter_reload(void)
+{
+ FWDGT_CTL = FWDGT_KEY_RELOAD;
+}
+
+/*!
+ \brief start the free watchdog timer counter
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void fwdgt_enable(void)
+{
+ FWDGT_CTL = FWDGT_KEY_ENABLE;
+}
+
+/*!
+ \brief configure the free watchdog timer counter window value
+ \param[in] window_value: specify window value(0x0000 - 0x0FFF)
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_window_value_config(uint16_t window_value)
+{
+ uint32_t time_index = FWDGT_WND_TIMEOUT;
+ uint32_t flag_status = RESET;
+
+ /* enable write access to FWDGT_WND */
+ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+
+ /* wait until the WUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
+ }while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
+
+ if ((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+
+ FWDGT_WND = WND_WND(window_value);
+
+ return SUCCESS;
+}
+
+/*!
+ \brief configure counter reload value, and prescaler divider value
+ \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
+ \param[in] prescaler_div: FWDGT prescaler value
+ \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
+ \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
+ \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
+ \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
+ \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
+ \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
+ \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
+ \param[out] none
+ \retval ErrStatus: ERROR or SUCCESS
+*/
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
+{
+ uint32_t timeout = FWDGT_PSC_TIMEOUT;
+ uint32_t flag_status = RESET;
+
+ /* enable write access to FWDGT_PSC,and FWDGT_RLD */
+ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
+
+ /* wait until the PUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
+ }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+
+ if ((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+
+ /* configure FWDGT */
+ FWDGT_PSC = (uint32_t)prescaler_div;
+
+ timeout = FWDGT_RLD_TIMEOUT;
+ /* wait until the RUD flag to be reset */
+ do{
+ flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
+ }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
+
+ if ((uint32_t)RESET != flag_status){
+ return ERROR;
+ }
+
+ FWDGT_RLD = RLD_RLD(reload_value);
+
+ /* reload the counter */
+ FWDGT_CTL = FWDGT_KEY_RELOAD;
+
+ return SUCCESS;
+}
+
+/*!
+ \brief get flag state of FWDGT
+ \param[in] flag: flag to get
+ \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
+ \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
+ \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus fwdgt_flag_get(uint16_t flag)
+{
+ if(FWDGT_STAT & flag){
+ return SET;
+ }
+
+ return RESET;
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_gpio.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_gpio.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_gpio.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_gpio.c
index 61960872..0cb86839 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_gpio.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_gpio.c
@@ -1,337 +1,337 @@
-/*!
- \file gd32f1x0_gpio.c
- \brief GPIO driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform for GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform for GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_gpio.h"
-
-/*!
- \brief reset GPIO port
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[out] none
- \retval none
-*/
-void gpio_deinit(uint32_t gpio_periph)
-{
- switch(gpio_periph){
- case GPIOA:
- /* reset GPIOA */
- rcu_periph_reset_enable(RCU_GPIOARST);
- rcu_periph_reset_disable(RCU_GPIOARST);
- break;
- case GPIOB:
- /* reset GPIOB */
- rcu_periph_reset_enable(RCU_GPIOBRST);
- rcu_periph_reset_disable(RCU_GPIOBRST);
- break;
- case GPIOC:
- /* reset GPIOC */
- rcu_periph_reset_enable(RCU_GPIOCRST);
- rcu_periph_reset_disable(RCU_GPIOCRST);
- break;
- case GPIOD:
- /* reset GPIOD */
- rcu_periph_reset_enable(RCU_GPIODRST);
- rcu_periph_reset_disable(RCU_GPIODRST);
- break;
- case GPIOF:
- /* reset GPIOF */
- rcu_periph_reset_enable(RCU_GPIOFRST);
- rcu_periph_reset_disable(RCU_GPIOFRST);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief set GPIO output mode
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] mode: gpio pin mode
- \arg GPIO_MODE_INPUT: input mode
- \arg GPIO_MODE_OUTPUT: output mode
- \arg GPIO_MODE_AF: alternate function mode
- \arg GPIO_MODE_ANALOG: analog mode
- \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor
- \arg GPIO_PUPD_NONE: without weak pull-up and pull-down resistors
- \arg GPIO_PUPD_PULLUP: with weak pull-up resistor
- \arg GPIO_PUPD_PULLDOWN:with weak pull-down resistor
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin)
-{
- uint16_t i;
- uint32_t ctl, pupd;
-
- ctl = GPIO_CTL(gpio_periph);
- pupd = GPIO_PUD(gpio_periph);
-
- for (i = 0U; i < 16U; i++){
- if((1U << i) & pin){
- /* clear the specified pin mode bits */
- ctl &= ~GPIO_MODE_MASK(i);
- /* set the specified pin mode bits */
- ctl |= GPIO_MODE_SET(i, mode);
-
- /* clear the specified pin pupd bits */
- pupd &= ~GPIO_PUPD_MASK(i);
- /* set the specified pin pupd bits */
- pupd |= GPIO_PUPD_SET(i, pull_up_down);
- }
- }
-
- GPIO_CTL(gpio_periph) = ctl;
- GPIO_PUD(gpio_periph) = pupd;
-}
-
-/*!
- \brief set GPIO output type and speed
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] otype: gpio pin output mode
- \arg GPIO_OTYPE_PP: push pull mode
- \arg GPIO_OTYPE_OD: open drain mode
- \param[in] speed
- \arg GPIO_OSPEED_2MHZ: output max speed 2M
- \arg GPIO_OSPEED_10MHZ: output max speed 10M
- \arg GPIO_OSPEED_50MHZ: output max speed 50M
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin)
-{
- uint16_t i;
- uint32_t ospeedr;
-
- if(0x1U == otype){
- GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
- }else{
- GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
- }
-
- /* get the specified pin output speed bits value */
- ospeedr = GPIO_OSPD(gpio_periph);
-
- for(i = 0U;i < 16U;i++){
- if((1U << i) & pin){
- /* clear the specified pin output speed bits */
- ospeedr &= ~GPIO_OSPEED_MASK(i);
- /* set the specified pin output speed bits */
- ospeedr |= GPIO_OSPEED_SET(i,speed);
- }
- }
- GPIO_OSPD(gpio_periph) = ospeedr;
-}
-
-/*!
- \brief set GPIO pin
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_bit_set(uint32_t gpio_periph,uint32_t pin)
-{
- GPIO_BOP(gpio_periph) = (uint32_t)pin;
-}
-
-/*!
- \brief reset GPIO pin
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin)
-{
- GPIO_BC(gpio_periph) = (uint32_t)pin;
-}
-
-/*!
- \brief write data to the specified GPIO pin
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[in] bit_value: SET or RESET
- \arg RESET: clear the port pin
- \arg SET: set the port pin
- \param[out] none
- \retval none
-*/
-void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value)
-{
- if(RESET != bit_value){
- GPIO_BOP(gpio_periph) = (uint32_t)pin;
- }else{
- GPIO_BC(gpio_periph) = (uint32_t)pin;
- }
-}
-
-/*!
- \brief write data to the specified GPIO port
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] data: specify the value to be written to the port output control register
- \param[out] none
- \retval none
-*/
-void gpio_port_write(uint32_t gpio_periph,uint16_t data)
-{
- GPIO_OCTL(gpio_periph) = (uint32_t)data;
-}
-
-/*!
- \brief get GPIO pin input status
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval input state of gpio pin: SET or RESET
-*/
-FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin)
-{
- if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief get GPIO all pins input status
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[out] none
- \retval input state of gpio all pins
-*/
-uint16_t gpio_input_port_get(uint32_t gpio_periph)
-{
- return (uint16_t)(GPIO_ISTAT(gpio_periph));
-}
-
-/*!
- \brief get GPIO pin output status
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval output state of gpio pin: SET or RESET
-*/
-FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin)
-{
- if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief get GPIO all pins output status
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[out] none
- \retval output state of gpio all pins
-*/
-uint16_t gpio_output_port_get(uint32_t gpio_periph)
-{
- return ((uint16_t)GPIO_OCTL(gpio_periph));
-}
-
-/*!
- \brief set GPIO alternate function
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] alt_func_num: gpio pin af function, please refer to specific device datasheet
- \arg GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, I2S0, SPI1, SPI2, I2S2, CK_OUT,
- SWDIO, SWCLK, USART0, CEC, IFRP, I2C0, I2C1, TSI, EVENTOUT
- \arg GPIO_AF_1: USART0, USART1, IFRP, CEC, TIMER2, TIMER14, I2C0, I2C1, I2C2, EVENTOUT
- \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, EVENTOUT
- \arg GPIO_AF_3: TSI, I2C0, TIMER14, EVENTOUT
- \arg GPIO_AF_4(port A,B only): TIMER13, I2C0, I2C1, I2C2, USART1
- \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, SPI2, I2S2, I2C0, I2C1
- \arg GPIO_AF_6(port A,B only): SPI1, EVENTOUT
- \arg GPIO_AF_7(port A,B only): CMP0, CMP1
- \arg GPIO_AF_9(port A,B only): CAN0, CAN1 (for GD32F170xx and GD32F190xx devices)
- \arg GPIO_AF_11: SLCD (for GD32F170xx and GD32F190xx devices)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin)
-{
- uint16_t i;
- uint32_t afrl, afrh;
-
- afrl = GPIO_AFSEL0(gpio_periph);
- afrh = GPIO_AFSEL1(gpio_periph);
-
- for (i = 0U; i < 8U; i++){
- if((1U << i) & pin){
- /* clear the specified pin alternate function bits */
- afrl &= ~GPIO_AFR_MASK(i);
- afrl |= GPIO_AFR_SET(i,alt_func_num);
- }
- }
-
- for (i = 8U; i < 16U; i++){
- if((1U << i) & pin){
- /* clear the specified pin alternate function bits */
- afrh &= ~GPIO_AFR_MASK(i - 8U);
- afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
- }
- }
-
- GPIO_AFSEL0(gpio_periph) = afrl;
- GPIO_AFSEL1(gpio_periph) = afrh;
-}
-
-/*!
- \brief lock GPIO pin
- \param[in] gpio_periph: GPIOx(x = A,B)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin)
-{
- uint32_t lock = 0x00010000U;
- lock |= pin;
-
- /* lock key writing sequence: write 1->write 0->write 1-> read 0-> read 1 */
- GPIO_LOCK(gpio_periph) = (uint32_t)lock;
- GPIO_LOCK(gpio_periph) = (uint32_t)pin;
- GPIO_LOCK(gpio_periph) = (uint32_t)lock;
- lock = GPIO_LOCK(gpio_periph);
- lock = GPIO_LOCK(gpio_periph);
-}
-
-#ifdef GD32F170_190
-/*!
- \brief toggle GPIO pin
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
- \param[out] none
- \retval none
-*/
-void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin)
-{
- GPIO_TG(gpio_periph) = (uint32_t)pin;
-}
-
-/*!
- \brief toggle GPIO port
- \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
- \param[out] none
- \retval none
-*/
-void gpio_port_toggle(uint32_t gpio_periph)
-{
- GPIO_TG(gpio_periph) = 0x0000FFFFU;
-}
-
-#endif /* GD32F170_190 */
+/*!
+ \file gd32f1x0_gpio.c
+ \brief GPIO driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform for GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform for GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_gpio.h"
+
+/*!
+ \brief reset GPIO port
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[out] none
+ \retval none
+*/
+void gpio_deinit(uint32_t gpio_periph)
+{
+ switch(gpio_periph){
+ case GPIOA:
+ /* reset GPIOA */
+ rcu_periph_reset_enable(RCU_GPIOARST);
+ rcu_periph_reset_disable(RCU_GPIOARST);
+ break;
+ case GPIOB:
+ /* reset GPIOB */
+ rcu_periph_reset_enable(RCU_GPIOBRST);
+ rcu_periph_reset_disable(RCU_GPIOBRST);
+ break;
+ case GPIOC:
+ /* reset GPIOC */
+ rcu_periph_reset_enable(RCU_GPIOCRST);
+ rcu_periph_reset_disable(RCU_GPIOCRST);
+ break;
+ case GPIOD:
+ /* reset GPIOD */
+ rcu_periph_reset_enable(RCU_GPIODRST);
+ rcu_periph_reset_disable(RCU_GPIODRST);
+ break;
+ case GPIOF:
+ /* reset GPIOF */
+ rcu_periph_reset_enable(RCU_GPIOFRST);
+ rcu_periph_reset_disable(RCU_GPIOFRST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief set GPIO output mode
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] mode: gpio pin mode
+ \arg GPIO_MODE_INPUT: input mode
+ \arg GPIO_MODE_OUTPUT: output mode
+ \arg GPIO_MODE_AF: alternate function mode
+ \arg GPIO_MODE_ANALOG: analog mode
+ \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor
+ \arg GPIO_PUPD_NONE: without weak pull-up and pull-down resistors
+ \arg GPIO_PUPD_PULLUP: with weak pull-up resistor
+ \arg GPIO_PUPD_PULLDOWN:with weak pull-down resistor
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin)
+{
+ uint16_t i;
+ uint32_t ctl, pupd;
+
+ ctl = GPIO_CTL(gpio_periph);
+ pupd = GPIO_PUD(gpio_periph);
+
+ for (i = 0U; i < 16U; i++){
+ if((1U << i) & pin){
+ /* clear the specified pin mode bits */
+ ctl &= ~GPIO_MODE_MASK(i);
+ /* set the specified pin mode bits */
+ ctl |= GPIO_MODE_SET(i, mode);
+
+ /* clear the specified pin pupd bits */
+ pupd &= ~GPIO_PUPD_MASK(i);
+ /* set the specified pin pupd bits */
+ pupd |= GPIO_PUPD_SET(i, pull_up_down);
+ }
+ }
+
+ GPIO_CTL(gpio_periph) = ctl;
+ GPIO_PUD(gpio_periph) = pupd;
+}
+
+/*!
+ \brief set GPIO output type and speed
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] otype: gpio pin output mode
+ \arg GPIO_OTYPE_PP: push pull mode
+ \arg GPIO_OTYPE_OD: open drain mode
+ \param[in] speed
+ \arg GPIO_OSPEED_2MHZ: output max speed 2M
+ \arg GPIO_OSPEED_10MHZ: output max speed 10M
+ \arg GPIO_OSPEED_50MHZ: output max speed 50M
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin)
+{
+ uint16_t i;
+ uint32_t ospeedr;
+
+ if(0x1U == otype){
+ GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
+ }else{
+ GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
+ }
+
+ /* get the specified pin output speed bits value */
+ ospeedr = GPIO_OSPD(gpio_periph);
+
+ for(i = 0U;i < 16U;i++){
+ if((1U << i) & pin){
+ /* clear the specified pin output speed bits */
+ ospeedr &= ~GPIO_OSPEED_MASK(i);
+ /* set the specified pin output speed bits */
+ ospeedr |= GPIO_OSPEED_SET(i,speed);
+ }
+ }
+ GPIO_OSPD(gpio_periph) = ospeedr;
+}
+
+/*!
+ \brief set GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_set(uint32_t gpio_periph,uint32_t pin)
+{
+ GPIO_BOP(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+ \brief reset GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin)
+{
+ GPIO_BC(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+ \brief write data to the specified GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[in] bit_value: SET or RESET
+ \arg RESET: clear the port pin
+ \arg SET: set the port pin
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value)
+{
+ if(RESET != bit_value){
+ GPIO_BOP(gpio_periph) = (uint32_t)pin;
+ }else{
+ GPIO_BC(gpio_periph) = (uint32_t)pin;
+ }
+}
+
+/*!
+ \brief write data to the specified GPIO port
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] data: specify the value to be written to the port output control register
+ \param[out] none
+ \retval none
+*/
+void gpio_port_write(uint32_t gpio_periph,uint16_t data)
+{
+ GPIO_OCTL(gpio_periph) = (uint32_t)data;
+}
+
+/*!
+ \brief get GPIO pin input status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval input state of gpio pin: SET or RESET
+*/
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin)
+{
+ if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief get GPIO all pins input status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[out] none
+ \retval input state of gpio all pins
+*/
+uint16_t gpio_input_port_get(uint32_t gpio_periph)
+{
+ return (uint16_t)(GPIO_ISTAT(gpio_periph));
+}
+
+/*!
+ \brief get GPIO pin output status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval output state of gpio pin: SET or RESET
+*/
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin)
+{
+ if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief get GPIO all pins output status
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[out] none
+ \retval output state of gpio all pins
+*/
+uint16_t gpio_output_port_get(uint32_t gpio_periph)
+{
+ return ((uint16_t)GPIO_OCTL(gpio_periph));
+}
+
+/*!
+ \brief set GPIO alternate function
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] alt_func_num: gpio pin af function, please refer to specific device datasheet
+ \arg GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, I2S0, SPI1, SPI2, I2S2, CK_OUT,
+ SWDIO, SWCLK, USART0, CEC, IFRP, I2C0, I2C1, TSI, EVENTOUT
+ \arg GPIO_AF_1: USART0, USART1, IFRP, CEC, TIMER2, TIMER14, I2C0, I2C1, I2C2, EVENTOUT
+ \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, EVENTOUT
+ \arg GPIO_AF_3: TSI, I2C0, TIMER14, EVENTOUT
+ \arg GPIO_AF_4(port A,B only): TIMER13, I2C0, I2C1, I2C2, USART1
+ \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, SPI2, I2S2, I2C0, I2C1
+ \arg GPIO_AF_6(port A,B only): SPI1, EVENTOUT
+ \arg GPIO_AF_7(port A,B only): CMP0, CMP1
+ \arg GPIO_AF_9(port A,B only): CAN0, CAN1 (for GD32F170xx and GD32F190xx devices)
+ \arg GPIO_AF_11: SLCD (for GD32F170xx and GD32F190xx devices)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin)
+{
+ uint16_t i;
+ uint32_t afrl, afrh;
+
+ afrl = GPIO_AFSEL0(gpio_periph);
+ afrh = GPIO_AFSEL1(gpio_periph);
+
+ for (i = 0U; i < 8U; i++){
+ if((1U << i) & pin){
+ /* clear the specified pin alternate function bits */
+ afrl &= ~GPIO_AFR_MASK(i);
+ afrl |= GPIO_AFR_SET(i,alt_func_num);
+ }
+ }
+
+ for (i = 8U; i < 16U; i++){
+ if((1U << i) & pin){
+ /* clear the specified pin alternate function bits */
+ afrh &= ~GPIO_AFR_MASK(i - 8U);
+ afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
+ }
+ }
+
+ GPIO_AFSEL0(gpio_periph) = afrl;
+ GPIO_AFSEL1(gpio_periph) = afrh;
+}
+
+/*!
+ \brief lock GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin)
+{
+ uint32_t lock = 0x00010000U;
+ lock |= pin;
+
+ /* lock key writing sequence: write 1->write 0->write 1-> read 0-> read 1 */
+ GPIO_LOCK(gpio_periph) = (uint32_t)lock;
+ GPIO_LOCK(gpio_periph) = (uint32_t)pin;
+ GPIO_LOCK(gpio_periph) = (uint32_t)lock;
+ lock = GPIO_LOCK(gpio_periph);
+ lock = GPIO_LOCK(gpio_periph);
+}
+
+#ifdef GD32F170_190
+/*!
+ \brief toggle GPIO pin
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
+ \param[out] none
+ \retval none
+*/
+void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin)
+{
+ GPIO_TG(gpio_periph) = (uint32_t)pin;
+}
+
+/*!
+ \brief toggle GPIO port
+ \param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
+ \param[out] none
+ \retval none
+*/
+void gpio_port_toggle(uint32_t gpio_periph)
+{
+ GPIO_TG(gpio_periph) = 0x0000FFFFU;
+}
+
+#endif /* GD32F170_190 */
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_i2c.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_i2c.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_i2c.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_i2c.c
index 54e33eba..8b6c9942 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_i2c.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_i2c.c
@@ -1,795 +1,795 @@
-/*!
- \file gd32f1x0_i2c.c
- \brief I2C driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_i2c.h"
-
-#define I2CCLK_MAX 0x3fU /*!< i2cclk max value */
-#define I2C_FLAG_MASK 0x0000FFFFU /*!< i2c flag mask */
-
-/*!
- \brief reset I2C
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_deinit(uint32_t i2c_periph)
-{
- switch(i2c_periph){
- case I2C0:
- /* reset I2C0 */
- rcu_periph_reset_enable(RCU_I2C0RST);
- rcu_periph_reset_disable(RCU_I2C0RST);
- break;
- case I2C1:
- /* reset I2C1 */
- rcu_periph_reset_enable(RCU_I2C1RST);
- rcu_periph_reset_disable(RCU_I2C1RST);
- break;
-#ifdef GD32F170_190
- case I2C2:
- /* reset I2C2 */
- rcu_periph_reset_enable(RCU_I2C2RST);
- rcu_periph_reset_disable(RCU_I2C2RST);
- break;
-#endif /* GD32F170_190 */
- default:
- break;
- }
-}
-
-/*!
- \brief configure I2C clock
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
- and fast mode plus (up to 1MHz)
- \param[in] dutycyc: duty cycle in fast mode or fast mode plus
- \arg I2C_DTCY_2: T_low/T_high=2
- \arg I2C_DTCY_16_9: T_low/T_high=16/9
- \param[out] none
- \retval none
-*/
-void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
-{
- uint32_t pclk1,clkc,freq,risetime;
- uint32_t temp;
-
- pclk1 = rcu_clock_freq_get(CK_APB1);
- /* I2C peripheral clock frequency */
- freq = (uint32_t)(pclk1/1000000U);
- if(freq >= I2CCLK_MAX){
- freq = I2CCLK_MAX;
- }
- temp = I2C_CTL1(i2c_periph);
- temp &= ~I2C_CTL1_I2CCLK;
- temp |= freq;
-
- I2C_CTL1(i2c_periph) = temp;
-
- if(100000U >= clkspeed){
- /* the maximum SCL rise time is 1000ns in standard mode */
- risetime = (uint32_t)((pclk1/1000000U)+1U);
- if(risetime >= I2CCLK_MAX){
- I2C_RT(i2c_periph) = I2CCLK_MAX;
- }else{
- I2C_RT(i2c_periph) = risetime;
- }
- clkc = (uint32_t)(pclk1/(clkspeed*2U));
- if(clkc < 0x04U){
- /* the CLKC in standard mode minmum value is 4 */
- clkc = 0x04U;
- }
- I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
-
- }else if(400000U >= clkspeed){
- /* the maximum SCL rise time is 300ns in fast mode */
- I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
- if(I2C_DTCY_2 == dutycyc){
- /* I2C duty cycle is 2 */
- clkc = (uint32_t)(pclk1/(clkspeed*3U));
- I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
- }else{
- /* I2C duty cycle is 16/9 */
- clkc = (uint32_t)(pclk1/(clkspeed*25U));
- I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
- }
- if(0U == (clkc & I2C_CKCFG_CLKC)){
- /* the CLKC in fast mode minmum value is 1 */
- clkc |= 0x0001U;
- }
- I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
- I2C_CKCFG(i2c_periph) |= clkc;
- }else{
- /* illegal parameters */
- }
-}
-
-/*!
- \brief configure I2C address
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] mode:
- \arg I2C_I2CMODE_ENABLE: I2C mode
- \arg I2C_SMBUSMODE_ENABLE: SMBus mode
- \param[in] addformat: 7bits or 10bits
- \arg I2C_ADDFORMAT_7BITS: 7bits
- \arg I2C_ADDFORMAT_10BITS: 10bits
- \param[in] addr: I2C address
- \param[out] none
- \retval none
-*/
-void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
-{
- /* SMBus/I2C mode selected */
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_SMBEN);
- ctl |= mode;
- I2C_CTL0(i2c_periph) = ctl;
- /* configure address */
- I2C_SADDR0(i2c_periph) = (addformat | addr);
-}
-
-/*!
- \brief SMBus type selection
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] ack:
- \arg I2C_SMBUS_DEVICE: device
- \arg I2C_SMBUS_HOST: host
- \param[out] none
- \retval none
-*/
-void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
-{
- if(I2C_SMBUS_HOST == type){
- I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
- }else{
- I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
- }
-}
-
-/*!
- \brief whether or not to send an ACK
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] ack:
- \arg I2C_ACK_ENABLE: ACK will be sent
- \arg I2C_ACK_DISABLE: ACK will not be sent
- \param[out] none
- \retval none
-*/
-void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
-{
- if(I2C_ACK_ENABLE == ack){
- I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
- }else{
- I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
- }
-}
-
-/*!
- \brief I2C POAP position configure
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] pos:
- \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
- \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
- \param[out] none
- \retval none
-*/
-void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
-{
- /* configure I2C POAP position */
- if(I2C_ACKPOS_NEXT == pos){
- I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
- }else{
- I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
- }
-}
-
-/*!
- \brief master send slave address
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] addr: slave address
- \param[in] trandirection: transmitter or receiver
- \arg I2C_TRANSMITTER: transmitter
- \arg I2C_RECEIVER: receiver
- \param[out] none
- \retval none
-*/
-void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
-{
- if(I2C_TRANSMITTER == trandirection){
- addr = addr & I2C_TRANSMITTER;
- }else{
- addr = addr | I2C_RECEIVER;
- }
- I2C_DATA(i2c_periph) = addr;
-}
-
-/*!
- \brief dual-address mode switch
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] dualaddr:
- \arg I2C_DUADEN_DISABLE: disable dual-address mode
- \arg I2C_DUADEN_ENABLE: enable dual-address mode
- \param[out] none
- \retval none
-*/
-void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
-{
- if(I2C_DUADEN_ENABLE == dualaddr){
- I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
- }else{
- I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
- }
-}
-
-/*!
- \brief enable I2C
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_enable(uint32_t i2c_periph)
-{
- I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
-}
-
-/*!
- \brief disable I2C
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_disable(uint32_t i2c_periph)
-{
- I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
-}
-
-/*!
- \brief generate a START condition on I2C bus
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_start_on_bus(uint32_t i2c_periph)
-{
- I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
-}
-
-/*!
- \brief generate a STOP condition on I2C bus
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_stop_on_bus(uint32_t i2c_periph)
-{
- I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
-}
-
-/*!
- \brief I2C transmit data function
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] data: data of transmission
- \param[out] none
- \retval none
-*/
-void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
-{
- I2C_DATA(i2c_periph) = DATA_TRANS(data);
-}
-
-/*!
- \brief I2C receive data function
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval data of received
-*/
-uint8_t i2c_data_receive(uint32_t i2c_periph)
-{
- return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
-}
-
-/*!
- \brief enable I2C DMA mode
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] dmastate:
- \arg I2C_DMA_ON: DMA mode enable
- \arg I2C_DMA_OFF: DMA mode disable
- \param[out] none
- \retval none
-*/
-void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
-{
- /* configure I2C DMA function */
- uint32_t ctl = 0U;
- ctl = I2C_CTL1(i2c_periph);
- ctl &= ~(I2C_CTL1_DMAON);
- ctl |= dmastate;
- I2C_CTL1(i2c_periph) = ctl;
-}
-
-/*!
- \brief flag indicating DMA last transfer
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] dmalast:
- \arg I2C_DMALST_ON: next DMA EOT is the last transfer
- \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer
- \param[out] none
- \retval none
-*/
-void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
-{
- /* configure DMA last transfer */
- uint32_t ctl = 0U;
- ctl = I2C_CTL1(i2c_periph);
- ctl &= ~(I2C_CTL1_DMALST);
- ctl |= dmalast;
- I2C_CTL1(i2c_periph) = ctl;
-}
-
-/*!
- \brief whether to stretch SCL low when data is not ready in slave mode
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] stretchpara:
- \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
- \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
- \param[out] none
- \retval none
-*/
-void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
-{
- /* configure I2C SCL strerching enable or disable */
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_DISSTRC);
- ctl |= stretchpara;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-/*!
- \brief whether or not to response to a general call
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] gcallpara:
- \arg I2C_GCEN_ENABLE: slave will response to a general call
- \arg I2C_GCEN_DISABLE: slave will not response to a general call
- \param[out] none
- \retval none
-*/
-void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
-{
- /* configure slave response to a general call enable or disable */
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_GCEN);
- ctl |= gcallpara;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-/*!
- \brief software reset I2C
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] sreset:
- \arg I2C_SRESET_SET: I2C is under reset
- \arg I2C_SRESET_RESET: I2C is not under reset
- \param[out] none
- \retval none
-*/
-void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
-{
- /* modify CTL0 and configure software reset I2C state */
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_SRESET);
- ctl |= sreset;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-/*!
- \brief check I2C flag is set or not
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] flag:
- \arg I2C_FLAG_SBSEND: start condition send out
- \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
- \arg I2C_FLAG_BTC: byte transmission finishes
- \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
- \arg I2C_FLAG_STPDET: stop condition detected in slave mode
- \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
- \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting
- \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
- \arg I2C_FLAG_LOSTARB: arbitration lost in master mode
- \arg I2C_FLAG_AERR: acknowledge error
- \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
- \arg I2C_FLAG_PECERR: PEC error when receiving data
- \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
- \arg I2C_FLAG_SMBALT: SMBus alert status
- \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
- \arg I2C_FLAG_I2CBSY: busy flag
- \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
- \arg I2C_FLAG_RXGC: general call address (00h) received
- \arg I2C_FLAG_DEFSMB: default address of SMBus device
- \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
- \arg I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
-{
- uint32_t reg = 0U;
- FlagStatus reval = RESET;
- /* get the flag in which register */
- reg = (BIT(31) & flag);
- if((BIT(31) == reg)){
- if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
- reval = SET;
- }else{
- reval = RESET;
- }
- }else{
- if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
- reval = SET;
- }else{
- reval = RESET;
- }
- }
- /* return the flag status */
- return reval;
-}
-
-/*!
- \brief clear I2C flag
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] flag: flag type
- \arg I2C_FLAG_SMBALT: SMBus Alert status
- \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
- \arg I2C_FLAG_PECERR: PEC error when receiving data
- \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
- \arg I2C_FLAG_AERR: acknowledge error
- \arg I2C_FLAG_LOSTARB: arbitration lost in master mode
- \arg I2C_FLAG_BERR: a bus error
- \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
- \param[out] none
- \retval none
-*/
-void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
-{
- if(I2C_FLAG_ADDSEND == flag){
- /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
- I2C_STAT0(i2c_periph);
- I2C_STAT1(i2c_periph);
- }else{
- I2C_STAT0(i2c_periph) &= ~(flag);
- }
-}
-
-/*!
- \brief enable I2C interrupt
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] inttype: interrupt type
- \arg I2C_INT_ERR: error interrupt enable
- \arg I2C_INT_EV: event interrupt enable
- \arg I2C_INT_BUF: buffer interrupt enable
- \param[out] none
- \retval none
-*/
-void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
-{
- I2C_CTL1(i2c_periph) |= (inttype);
-}
-
-/*!
- \brief disable I2C interrupt
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] inttype: interrupt type
- \arg I2C_INT_ERR: error interrupt enable
- \arg I2C_INT_EV: event interrupt enable
- \arg I2C_INT_BUF: buffer interrupt enable
- \param[out] none
- \retval none
-*/
-void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
-{
- I2C_CTL1(i2c_periph) &= ~(inttype);
-}
-
-/*!
- \brief check I2C interrupt flag
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] int_flag: interrupt flag
- \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
- \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
- \arg I2C_INT_FLAG_BTC: byte transmission finishes
- \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
- \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
- \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
- \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
- \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
- \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
- \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
- \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
- \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
- \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
- \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
- \param[out] none
- \retval none
-*/
-FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
-{
- uint32_t evie, errie, bufie;
-
- evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
- errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
- /* check I2C event interrupt enable bit */
- if((intflag&0x00ffU) && evie){
- if(intflag&0x001fU){
- /* check I2C event flags except TBE and RBNE */
- if(intflag & I2C_STAT0(i2c_periph)){
- return SET;
- }else{
- return RESET;
- }
- }else{
- /* check I2C event flags TBE and RBNE */
- bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
- if(bufie){
- if(intflag & I2C_STAT0(i2c_periph)){
- return SET;
- }else{
- return RESET;
- }
- }else{
- return RESET;
- }
- }
- /* check I2C error interrupt enable bit */
- }else if((intflag&0xff00U) && errie){
- /* check I2C error flags */
- if(intflag & I2C_STAT0(i2c_periph)){
- return SET;
- }else{
- return RESET;
- }
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear I2C interrupt flag
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] intflag: interrupt flag
- \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
- \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
- \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
- \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
- \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
- \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
- \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
- \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
- \param[out] none
- \retval none
-*/
-void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
-{
- if(I2C_INT_FLAG_ADDSEND == intflag){
- /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
- I2C_STAT0(i2c_periph);
- I2C_STAT1(i2c_periph);
- }else{
- I2C_STAT0(i2c_periph) &= ~(intflag);
- }
-}
-
-/*!
- \brief I2C PEC calculation on or off
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] pecpara:
- \arg I2C_PEC_ENABLE: PEC calculation on
- \arg I2C_PEC_DISABLE: PEC calculation off
- \param[out] none
- \retval none
-*/
-void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
-{
- /* on/off PEC calculation */
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_PECEN);
- ctl |= pecstate;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-/*!
- \brief I2C whether to transfer PEC value
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] pecpara:
- \arg I2C_PECTRANS_ENABLE: transfer PEC
- \arg I2C_PECTRANS_DISABLE: not transfer PEC
- \param[out] none
- \retval none
-*/
-void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
-{
- /* whether to transfer PEC */
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_PECTRANS);
- ctl |= pecpara;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-/*!
- \brief get packet error checking value
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval PEC value
-*/
-uint8_t i2c_pec_value_get(uint32_t i2c_periph)
-{
- return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8);
-}
-
-/*!
- \brief I2C issue alert through SMBA pin
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] smbuspara:
- \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin
- \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
- \param[out] none
- \retval none
-*/
-void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
-{
- /* issue alert through SMBA pin configure*/
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_SALT);
- ctl |= smbuspara;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-/*!
- \brief enable or disable I2C ARP protocol in SMBus switch
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] smbuspara:
- \arg I2C_ARP_ENABLE: enable ARP
- \arg I2C_ARP_DISABLE: disable ARP
- \param[out] none
- \retval none
-*/
-void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
-{
- /* enable or disable I2C ARP protocol*/
- uint32_t ctl = 0U;
- ctl = I2C_CTL0(i2c_periph);
- ctl &= ~(I2C_CTL0_ARPEN);
- ctl |= arpstate;
- I2C_CTL0(i2c_periph) = ctl;
-}
-
-#ifdef GD32F170_190
-
-/*!
- \brief enable SAM_V interface
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_sam_enable(uint32_t i2c_periph)
-{
- I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN;
-}
-
-/*!
- \brief disable SAM_V interface
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_sam_disable(uint32_t i2c_periph)
-{
- I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN);
-}
-
-/*!
- \brief enable SAM_V interface timeout detect
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_sam_timeout_enable(uint32_t i2c_periph)
-{
- I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN;
-}
-
-/*!
- \brief disable SAM_V interface timeout detect
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void i2c_sam_timeout_disable(uint32_t i2c_periph)
-{
- I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN);
-}
-
-/*!
- \brief enable the specified I2C SAM interrupt
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] inttype: interrupt type
- \@arg I2C_SAMCS_TFFIE: txframe fall interrupt
- \@arg I2C_SAMCS_TFRIE: txframe rise interrupt
- \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt
- \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt
- \param[out] none
- \retval none
-*/
-void i2c_sam_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
-{
- I2C_SAMCS(i2c_periph) |= (inttype);
-}
-
-/*!
- \brief disable i2c interrupt
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] inttype: interrupt type
- \@arg I2C_SAMCS_TFFIE: txframe fall interrupt
- \@arg I2C_SAMCS_TFRIE: txframe rise interrupt
- \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt
- \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt
- \param[out] none
- \retval none
-*/
-void i2c_sam_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
-{
- I2C_SAMCS(i2c_periph) &= ~(inttype);
-}
-
-/*!
- \brief check i2c SAM state
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] samstate: state type
- \@arg I2C_SAMCS_TXF: level of txframe signal
- \@arg I2C_SAMCS_RXF: level of rxframe signal
- \@arg I2C_SAMCS_TFF: txframe fall flag
- \@arg I2C_SAMCS_TFR: txframe rise flag
- \@arg I2C_SAMCS_RFF: rxframe fall flag
- \@arg I2C_SAMCS_RFR: rxframe rise flag
- \param[out] none
- \retval state of i2c SAM
-*/
-FlagStatus i2c_sam_flag_get(uint32_t i2c_periph, uint32_t samstate)
-{
- if(I2C_SAMCS(i2c_periph) & samstate){
- return SET;
- }
-
- return RESET;
-}
-/*!
- \brief clear i2c SAM state
- \param[in] i2c_periph: I2Cx(x=0,1,2)
- \param[in] samstate: state type
- \@arg I2C_SAMCS_TFF: txframe fall flag
- \@arg I2C_SAMCS_TFR: txframe rise flag
- \@arg I2C_SAMCS_RFF: rxframe fall flag
- \@arg I2C_SAMCS_RFR: rxframe rise flag
- \param[out] none
- \retval none
-*/
-void i2c_sam_flag_clear(uint32_t i2c_periph, uint32_t samstate)
-{
- I2C_SAMCS(i2c_periph) &= ~(samstate);
-
-}
-
-#endif /* GD32F170_190 */
+/*!
+ \file gd32f1x0_i2c.c
+ \brief I2C driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_i2c.h"
+
+#define I2CCLK_MAX 0x3fU /*!< i2cclk max value */
+#define I2C_FLAG_MASK 0x0000FFFFU /*!< i2c flag mask */
+
+/*!
+ \brief reset I2C
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_deinit(uint32_t i2c_periph)
+{
+ switch(i2c_periph){
+ case I2C0:
+ /* reset I2C0 */
+ rcu_periph_reset_enable(RCU_I2C0RST);
+ rcu_periph_reset_disable(RCU_I2C0RST);
+ break;
+ case I2C1:
+ /* reset I2C1 */
+ rcu_periph_reset_enable(RCU_I2C1RST);
+ rcu_periph_reset_disable(RCU_I2C1RST);
+ break;
+#ifdef GD32F170_190
+ case I2C2:
+ /* reset I2C2 */
+ rcu_periph_reset_enable(RCU_I2C2RST);
+ rcu_periph_reset_disable(RCU_I2C2RST);
+ break;
+#endif /* GD32F170_190 */
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure I2C clock
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
+ and fast mode plus (up to 1MHz)
+ \param[in] dutycyc: duty cycle in fast mode or fast mode plus
+ \arg I2C_DTCY_2: T_low/T_high=2
+ \arg I2C_DTCY_16_9: T_low/T_high=16/9
+ \param[out] none
+ \retval none
+*/
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
+{
+ uint32_t pclk1,clkc,freq,risetime;
+ uint32_t temp;
+
+ pclk1 = rcu_clock_freq_get(CK_APB1);
+ /* I2C peripheral clock frequency */
+ freq = (uint32_t)(pclk1/1000000U);
+ if(freq >= I2CCLK_MAX){
+ freq = I2CCLK_MAX;
+ }
+ temp = I2C_CTL1(i2c_periph);
+ temp &= ~I2C_CTL1_I2CCLK;
+ temp |= freq;
+
+ I2C_CTL1(i2c_periph) = temp;
+
+ if(100000U >= clkspeed){
+ /* the maximum SCL rise time is 1000ns in standard mode */
+ risetime = (uint32_t)((pclk1/1000000U)+1U);
+ if(risetime >= I2CCLK_MAX){
+ I2C_RT(i2c_periph) = I2CCLK_MAX;
+ }else{
+ I2C_RT(i2c_periph) = risetime;
+ }
+ clkc = (uint32_t)(pclk1/(clkspeed*2U));
+ if(clkc < 0x04U){
+ /* the CLKC in standard mode minmum value is 4 */
+ clkc = 0x04U;
+ }
+ I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
+
+ }else if(400000U >= clkspeed){
+ /* the maximum SCL rise time is 300ns in fast mode */
+ I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
+ if(I2C_DTCY_2 == dutycyc){
+ /* I2C duty cycle is 2 */
+ clkc = (uint32_t)(pclk1/(clkspeed*3U));
+ I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
+ }else{
+ /* I2C duty cycle is 16/9 */
+ clkc = (uint32_t)(pclk1/(clkspeed*25U));
+ I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
+ }
+ if(0U == (clkc & I2C_CKCFG_CLKC)){
+ /* the CLKC in fast mode minmum value is 1 */
+ clkc |= 0x0001U;
+ }
+ I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
+ I2C_CKCFG(i2c_periph) |= clkc;
+ }else{
+ /* illegal parameters */
+ }
+}
+
+/*!
+ \brief configure I2C address
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] mode:
+ \arg I2C_I2CMODE_ENABLE: I2C mode
+ \arg I2C_SMBUSMODE_ENABLE: SMBus mode
+ \param[in] addformat: 7bits or 10bits
+ \arg I2C_ADDFORMAT_7BITS: 7bits
+ \arg I2C_ADDFORMAT_10BITS: 10bits
+ \param[in] addr: I2C address
+ \param[out] none
+ \retval none
+*/
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
+{
+ /* SMBus/I2C mode selected */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SMBEN);
+ ctl |= mode;
+ I2C_CTL0(i2c_periph) = ctl;
+ /* configure address */
+ I2C_SADDR0(i2c_periph) = (addformat | addr);
+}
+
+/*!
+ \brief SMBus type selection
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] ack:
+ \arg I2C_SMBUS_DEVICE: device
+ \arg I2C_SMBUS_HOST: host
+ \param[out] none
+ \retval none
+*/
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
+{
+ if(I2C_SMBUS_HOST == type){
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
+ }else{
+ I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
+ }
+}
+
+/*!
+ \brief whether or not to send an ACK
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] ack:
+ \arg I2C_ACK_ENABLE: ACK will be sent
+ \arg I2C_ACK_DISABLE: ACK will not be sent
+ \param[out] none
+ \retval none
+*/
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
+{
+ if(I2C_ACK_ENABLE == ack){
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
+ }else{
+ I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
+ }
+}
+
+/*!
+ \brief I2C POAP position configure
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] pos:
+ \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
+ \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
+ \param[out] none
+ \retval none
+*/
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
+{
+ /* configure I2C POAP position */
+ if(I2C_ACKPOS_NEXT == pos){
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
+ }else{
+ I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
+ }
+}
+
+/*!
+ \brief master send slave address
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] addr: slave address
+ \param[in] trandirection: transmitter or receiver
+ \arg I2C_TRANSMITTER: transmitter
+ \arg I2C_RECEIVER: receiver
+ \param[out] none
+ \retval none
+*/
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
+{
+ if(I2C_TRANSMITTER == trandirection){
+ addr = addr & I2C_TRANSMITTER;
+ }else{
+ addr = addr | I2C_RECEIVER;
+ }
+ I2C_DATA(i2c_periph) = addr;
+}
+
+/*!
+ \brief dual-address mode switch
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] dualaddr:
+ \arg I2C_DUADEN_DISABLE: disable dual-address mode
+ \arg I2C_DUADEN_ENABLE: enable dual-address mode
+ \param[out] none
+ \retval none
+*/
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr)
+{
+ if(I2C_DUADEN_ENABLE == dualaddr){
+ I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN;
+ }else{
+ I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
+ }
+}
+
+/*!
+ \brief enable I2C
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_enable(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
+}
+
+/*!
+ \brief disable I2C
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_disable(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
+}
+
+/*!
+ \brief generate a START condition on I2C bus
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_start_on_bus(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
+}
+
+/*!
+ \brief generate a STOP condition on I2C bus
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_stop_on_bus(uint32_t i2c_periph)
+{
+ I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
+}
+
+/*!
+ \brief I2C transmit data function
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] data: data of transmission
+ \param[out] none
+ \retval none
+*/
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
+{
+ I2C_DATA(i2c_periph) = DATA_TRANS(data);
+}
+
+/*!
+ \brief I2C receive data function
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval data of received
+*/
+uint8_t i2c_data_receive(uint32_t i2c_periph)
+{
+ return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
+}
+
+/*!
+ \brief enable I2C DMA mode
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] dmastate:
+ \arg I2C_DMA_ON: DMA mode enable
+ \arg I2C_DMA_OFF: DMA mode disable
+ \param[out] none
+ \retval none
+*/
+void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
+{
+ /* configure I2C DMA function */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL1(i2c_periph);
+ ctl &= ~(I2C_CTL1_DMAON);
+ ctl |= dmastate;
+ I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+ \brief flag indicating DMA last transfer
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] dmalast:
+ \arg I2C_DMALST_ON: next DMA EOT is the last transfer
+ \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer
+ \param[out] none
+ \retval none
+*/
+void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast)
+{
+ /* configure DMA last transfer */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL1(i2c_periph);
+ ctl &= ~(I2C_CTL1_DMALST);
+ ctl |= dmalast;
+ I2C_CTL1(i2c_periph) = ctl;
+}
+
+/*!
+ \brief whether to stretch SCL low when data is not ready in slave mode
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] stretchpara:
+ \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
+ \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
+ \param[out] none
+ \retval none
+*/
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
+{
+ /* configure I2C SCL strerching enable or disable */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_DISSTRC);
+ ctl |= stretchpara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief whether or not to response to a general call
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] gcallpara:
+ \arg I2C_GCEN_ENABLE: slave will response to a general call
+ \arg I2C_GCEN_DISABLE: slave will not response to a general call
+ \param[out] none
+ \retval none
+*/
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
+{
+ /* configure slave response to a general call enable or disable */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_GCEN);
+ ctl |= gcallpara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief software reset I2C
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] sreset:
+ \arg I2C_SRESET_SET: I2C is under reset
+ \arg I2C_SRESET_RESET: I2C is not under reset
+ \param[out] none
+ \retval none
+*/
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
+{
+ /* modify CTL0 and configure software reset I2C state */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SRESET);
+ ctl |= sreset;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief check I2C flag is set or not
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] flag:
+ \arg I2C_FLAG_SBSEND: start condition send out
+ \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
+ \arg I2C_FLAG_BTC: byte transmission finishes
+ \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
+ \arg I2C_FLAG_STPDET: stop condition detected in slave mode
+ \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
+ \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting
+ \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
+ \arg I2C_FLAG_LOSTARB: arbitration lost in master mode
+ \arg I2C_FLAG_AERR: acknowledge error
+ \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
+ \arg I2C_FLAG_PECERR: PEC error when receiving data
+ \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
+ \arg I2C_FLAG_SMBALT: SMBus alert status
+ \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
+ \arg I2C_FLAG_I2CBSY: busy flag
+ \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
+ \arg I2C_FLAG_RXGC: general call address (00h) received
+ \arg I2C_FLAG_DEFSMB: default address of SMBus device
+ \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
+ \arg I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag)
+{
+ uint32_t reg = 0U;
+ FlagStatus reval = RESET;
+ /* get the flag in which register */
+ reg = (BIT(31) & flag);
+ if((BIT(31) == reg)){
+ if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){
+ reval = SET;
+ }else{
+ reval = RESET;
+ }
+ }else{
+ if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){
+ reval = SET;
+ }else{
+ reval = RESET;
+ }
+ }
+ /* return the flag status */
+ return reval;
+}
+
+/*!
+ \brief clear I2C flag
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] flag: flag type
+ \arg I2C_FLAG_SMBALT: SMBus Alert status
+ \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
+ \arg I2C_FLAG_PECERR: PEC error when receiving data
+ \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
+ \arg I2C_FLAG_AERR: acknowledge error
+ \arg I2C_FLAG_LOSTARB: arbitration lost in master mode
+ \arg I2C_FLAG_BERR: a bus error
+ \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
+ \param[out] none
+ \retval none
+*/
+void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag)
+{
+ if(I2C_FLAG_ADDSEND == flag){
+ /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+ I2C_STAT0(i2c_periph);
+ I2C_STAT1(i2c_periph);
+ }else{
+ I2C_STAT0(i2c_periph) &= ~(flag);
+ }
+}
+
+/*!
+ \brief enable I2C interrupt
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] inttype: interrupt type
+ \arg I2C_INT_ERR: error interrupt enable
+ \arg I2C_INT_EV: event interrupt enable
+ \arg I2C_INT_BUF: buffer interrupt enable
+ \param[out] none
+ \retval none
+*/
+void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
+{
+ I2C_CTL1(i2c_periph) |= (inttype);
+}
+
+/*!
+ \brief disable I2C interrupt
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] inttype: interrupt type
+ \arg I2C_INT_ERR: error interrupt enable
+ \arg I2C_INT_EV: event interrupt enable
+ \arg I2C_INT_BUF: buffer interrupt enable
+ \param[out] none
+ \retval none
+*/
+void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
+{
+ I2C_CTL1(i2c_periph) &= ~(inttype);
+}
+
+/*!
+ \brief check I2C interrupt flag
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] int_flag: interrupt flag
+ \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
+ \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+ \arg I2C_INT_FLAG_BTC: byte transmission finishes
+ \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
+ \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
+ \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
+ \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
+ \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+ \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+ \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+ \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+ \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+ \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+ \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
+ \param[out] none
+ \retval none
+*/
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag)
+{
+ uint32_t evie, errie, bufie;
+
+ evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE;
+ errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE;
+ /* check I2C event interrupt enable bit */
+ if((intflag&0x00ffU) && evie){
+ if(intflag&0x001fU){
+ /* check I2C event flags except TBE and RBNE */
+ if(intflag & I2C_STAT0(i2c_periph)){
+ return SET;
+ }else{
+ return RESET;
+ }
+ }else{
+ /* check I2C event flags TBE and RBNE */
+ bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
+ if(bufie){
+ if(intflag & I2C_STAT0(i2c_periph)){
+ return SET;
+ }else{
+ return RESET;
+ }
+ }else{
+ return RESET;
+ }
+ }
+ /* check I2C error interrupt enable bit */
+ }else if((intflag&0xff00U) && errie){
+ /* check I2C error flags */
+ if(intflag & I2C_STAT0(i2c_periph)){
+ return SET;
+ }else{
+ return RESET;
+ }
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear I2C interrupt flag
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] intflag: interrupt flag
+ \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
+ \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
+ \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
+ \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
+ \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
+ \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
+ \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
+ \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
+ \param[out] none
+ \retval none
+*/
+void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag)
+{
+ if(I2C_INT_FLAG_ADDSEND == intflag){
+ /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
+ I2C_STAT0(i2c_periph);
+ I2C_STAT1(i2c_periph);
+ }else{
+ I2C_STAT0(i2c_periph) &= ~(intflag);
+ }
+}
+
+/*!
+ \brief I2C PEC calculation on or off
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] pecpara:
+ \arg I2C_PEC_ENABLE: PEC calculation on
+ \arg I2C_PEC_DISABLE: PEC calculation off
+ \param[out] none
+ \retval none
+*/
+void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
+{
+ /* on/off PEC calculation */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_PECEN);
+ ctl |= pecstate;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief I2C whether to transfer PEC value
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] pecpara:
+ \arg I2C_PECTRANS_ENABLE: transfer PEC
+ \arg I2C_PECTRANS_DISABLE: not transfer PEC
+ \param[out] none
+ \retval none
+*/
+void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
+{
+ /* whether to transfer PEC */
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_PECTRANS);
+ ctl |= pecpara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief get packet error checking value
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval PEC value
+*/
+uint8_t i2c_pec_value_get(uint32_t i2c_periph)
+{
+ return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8);
+}
+
+/*!
+ \brief I2C issue alert through SMBA pin
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] smbuspara:
+ \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin
+ \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
+ \param[out] none
+ \retval none
+*/
+void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
+{
+ /* issue alert through SMBA pin configure*/
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_SALT);
+ ctl |= smbuspara;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+/*!
+ \brief enable or disable I2C ARP protocol in SMBus switch
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] smbuspara:
+ \arg I2C_ARP_ENABLE: enable ARP
+ \arg I2C_ARP_DISABLE: disable ARP
+ \param[out] none
+ \retval none
+*/
+void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
+{
+ /* enable or disable I2C ARP protocol*/
+ uint32_t ctl = 0U;
+ ctl = I2C_CTL0(i2c_periph);
+ ctl &= ~(I2C_CTL0_ARPEN);
+ ctl |= arpstate;
+ I2C_CTL0(i2c_periph) = ctl;
+}
+
+#ifdef GD32F170_190
+
+/*!
+ \brief enable SAM_V interface
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_enable(uint32_t i2c_periph)
+{
+ I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN;
+}
+
+/*!
+ \brief disable SAM_V interface
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_disable(uint32_t i2c_periph)
+{
+ I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN);
+}
+
+/*!
+ \brief enable SAM_V interface timeout detect
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_timeout_enable(uint32_t i2c_periph)
+{
+ I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN;
+}
+
+/*!
+ \brief disable SAM_V interface timeout detect
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_timeout_disable(uint32_t i2c_periph)
+{
+ I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN);
+}
+
+/*!
+ \brief enable the specified I2C SAM interrupt
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] inttype: interrupt type
+ \@arg I2C_SAMCS_TFFIE: txframe fall interrupt
+ \@arg I2C_SAMCS_TFRIE: txframe rise interrupt
+ \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt
+ \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_interrupt_enable(uint32_t i2c_periph, uint32_t inttype)
+{
+ I2C_SAMCS(i2c_periph) |= (inttype);
+}
+
+/*!
+ \brief disable i2c interrupt
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] inttype: interrupt type
+ \@arg I2C_SAMCS_TFFIE: txframe fall interrupt
+ \@arg I2C_SAMCS_TFRIE: txframe rise interrupt
+ \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt
+ \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_interrupt_disable(uint32_t i2c_periph, uint32_t inttype)
+{
+ I2C_SAMCS(i2c_periph) &= ~(inttype);
+}
+
+/*!
+ \brief check i2c SAM state
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] samstate: state type
+ \@arg I2C_SAMCS_TXF: level of txframe signal
+ \@arg I2C_SAMCS_RXF: level of rxframe signal
+ \@arg I2C_SAMCS_TFF: txframe fall flag
+ \@arg I2C_SAMCS_TFR: txframe rise flag
+ \@arg I2C_SAMCS_RFF: rxframe fall flag
+ \@arg I2C_SAMCS_RFR: rxframe rise flag
+ \param[out] none
+ \retval state of i2c SAM
+*/
+FlagStatus i2c_sam_flag_get(uint32_t i2c_periph, uint32_t samstate)
+{
+ if(I2C_SAMCS(i2c_periph) & samstate){
+ return SET;
+ }
+
+ return RESET;
+}
+/*!
+ \brief clear i2c SAM state
+ \param[in] i2c_periph: I2Cx(x=0,1,2)
+ \param[in] samstate: state type
+ \@arg I2C_SAMCS_TFF: txframe fall flag
+ \@arg I2C_SAMCS_TFR: txframe rise flag
+ \@arg I2C_SAMCS_RFF: rxframe fall flag
+ \@arg I2C_SAMCS_RFR: rxframe rise flag
+ \param[out] none
+ \retval none
+*/
+void i2c_sam_flag_clear(uint32_t i2c_periph, uint32_t samstate)
+{
+ I2C_SAMCS(i2c_periph) &= ~(samstate);
+
+}
+
+#endif /* GD32F170_190 */
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_misc.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_misc.c
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_misc.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_misc.c
index 3e82b5e4..31af322a 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_misc.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_misc.c
@@ -1,149 +1,149 @@
-/*!
- \file gd32f1x0_misc.c
- \brief MISC driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_misc.h"
-
-/*!
- \brief set the priority group
- \param[in] nvic_prigroup: the NVIC priority group
- \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
- \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
- \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
- \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
- \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
- \param[out] none
- \retval none
-*/
-void nvic_priority_group_set(uint32_t nvic_prigroup)
-{
- /* set the priority group value */
- SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
-}
-
-/*!
- \brief enable NVIC request
- \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
- \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
- \param[in] nvic_irq_sub_priority: the subpriority needed to set
- \param[out] none
- \retval none
-*/
-void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
- uint8_t nvic_irq_sub_priority)
-{
- uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
- /* use the priority group value to get the temp_pre and the temp_sub */
- if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE0_SUB4){
- temp_pre = 0U;
- temp_sub = 0x4U;
- }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE1_SUB3){
- temp_pre = 1U;
- temp_sub = 0x3U;
- }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE2_SUB2){
- temp_pre = 2U;
- temp_sub = 0x2U;
- }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE3_SUB1){
- temp_pre = 3U;
- temp_sub = 0x1U;
- }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE4_SUB0){
- temp_pre = 4U;
- temp_sub = 0x0U;
- }else{
- }
- /* get the temp_priority to fill the NVIC->IP register */
- temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
- temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
- temp_priority = temp_priority << 0x04U;
- NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
- /* enable the selected IRQ */
- NVIC->ISER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
-}
-
-/*!
- \brief disable NVIC request
- \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
- \param[out] none
- \retval none
-*/
-void nvic_irq_disable(uint8_t nvic_irq)
-{
- /* disable the selected IRQ.*/
- NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
-}
-
-/*!
- \brief set the NVIC vector table base address
- \param[in] nvic_vict_tab: the RAM or FLASH base address
- \arg NVIC_VECTTAB_RAM: RAM base address
- \are NVIC_VECTTAB_FLASH: Flash base address
- \param[in] offset: Vector Table offset
- \param[out] none
- \retval none
-*/
-void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
-{
- SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
-}
-
-/*!
- \brief set the state of the low power mode
- \param[in] lowpower_mode: the low power mode state
- \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
- mode by exiting from ISR
- \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
- \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
- by all the enable and disable interrupts
- \param[out] none
- \retval none
-*/
-void system_lowpower_set(uint8_t lowpower_mode)
-{
- SCB->SCR |= (uint32_t)lowpower_mode;
-}
-
-/*!
- \brief reset the state of the low power mode
- \param[in] lowpower_mode: the low power mode state
- \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
- mode by exiting from ISR
- \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
- \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
- woke up by the enable interrupts
- \param[out] none
- \retval none
-*/
-void system_lowpower_reset(uint8_t lowpower_mode)
-{
- SCB->SCR &= (~(uint32_t)lowpower_mode);
-}
-
-/*!
- \brief set the systick clock source
- \param[in] systick_clksource: the systick clock source needed to choose
- \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
- \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
- \param[out] none
- \retval none
-*/
-
-void systick_clksource_set(uint32_t systick_clksource)
-{
- if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
- /* set the systick clock source from HCLK */
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- }else{
- /* set the systick clock source from HCLK/8 */
- SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
- }
-}
+/*!
+ \file gd32f1x0_misc.c
+ \brief MISC driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_misc.h"
+
+/*!
+ \brief set the priority group
+ \param[in] nvic_prigroup: the NVIC priority group
+ \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
+ \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
+ \param[out] none
+ \retval none
+*/
+void nvic_priority_group_set(uint32_t nvic_prigroup)
+{
+ /* set the priority group value */
+ SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
+}
+
+/*!
+ \brief enable NVIC request
+ \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+ \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
+ \param[in] nvic_irq_sub_priority: the subpriority needed to set
+ \param[out] none
+ \retval none
+*/
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
+ uint8_t nvic_irq_sub_priority)
+{
+ uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
+ /* use the priority group value to get the temp_pre and the temp_sub */
+ if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE0_SUB4){
+ temp_pre = 0U;
+ temp_sub = 0x4U;
+ }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE1_SUB3){
+ temp_pre = 1U;
+ temp_sub = 0x3U;
+ }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE2_SUB2){
+ temp_pre = 2U;
+ temp_sub = 0x2U;
+ }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE3_SUB1){
+ temp_pre = 3U;
+ temp_sub = 0x1U;
+ }else if(((SCB->AIRCR) & (uint32_t)0x700)==NVIC_PRIGROUP_PRE4_SUB0){
+ temp_pre = 4U;
+ temp_sub = 0x0U;
+ }else{
+ }
+ /* get the temp_priority to fill the NVIC->IP register */
+ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
+ temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
+ temp_priority = temp_priority << 0x04U;
+ NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
+ /* enable the selected IRQ */
+ NVIC->ISER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
+}
+
+/*!
+ \brief disable NVIC request
+ \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
+ \param[out] none
+ \retval none
+*/
+void nvic_irq_disable(uint8_t nvic_irq)
+{
+ /* disable the selected IRQ.*/
+ NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
+}
+
+/*!
+ \brief set the NVIC vector table base address
+ \param[in] nvic_vict_tab: the RAM or FLASH base address
+ \arg NVIC_VECTTAB_RAM: RAM base address
+ \are NVIC_VECTTAB_FLASH: Flash base address
+ \param[in] offset: Vector Table offset
+ \param[out] none
+ \retval none
+*/
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
+{
+ SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
+}
+
+/*!
+ \brief set the state of the low power mode
+ \param[in] lowpower_mode: the low power mode state
+ \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
+ mode by exiting from ISR
+ \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
+ \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
+ by all the enable and disable interrupts
+ \param[out] none
+ \retval none
+*/
+void system_lowpower_set(uint8_t lowpower_mode)
+{
+ SCB->SCR |= (uint32_t)lowpower_mode;
+}
+
+/*!
+ \brief reset the state of the low power mode
+ \param[in] lowpower_mode: the low power mode state
+ \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
+ mode by exiting from ISR
+ \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
+ \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
+ woke up by the enable interrupts
+ \param[out] none
+ \retval none
+*/
+void system_lowpower_reset(uint8_t lowpower_mode)
+{
+ SCB->SCR &= (~(uint32_t)lowpower_mode);
+}
+
+/*!
+ \brief set the systick clock source
+ \param[in] systick_clksource: the systick clock source needed to choose
+ \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
+ \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
+ \param[out] none
+ \retval none
+*/
+
+void systick_clksource_set(uint32_t systick_clksource)
+{
+ if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
+ /* set the systick clock source from HCLK */
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }else{
+ /* set the systick clock source from HCLK/8 */
+ SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
+ }
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_opa.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_opa.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_opa.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_opa.c
index 37da5c00..9800c262 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_opa.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_opa.c
@@ -1,341 +1,341 @@
-/*!
- \file gd32f1x0_opa.c
- \brief OPA driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#ifdef GD32F170_190
-
-#include "gd32f1x0_opa.h"
-
-/*!
- \brief deinit the OPA register to its default reset value
- \param[in] none
- \param[out] none
- \retval none
-*/
-void opa_deinit(void)
-{
- rcu_periph_reset_enable(RCU_OPAIVREFRST);
- rcu_periph_reset_disable(RCU_OPAIVREFRST);
-}
-
-/*!
- \brief enable OPA switch
- \param[in] opax_swy
- \arg OPA_T3OPA0: T3 switch enable for OPA0
- \arg OPA_S1OPA0: S1 switch enable for OPA0
- \arg OPA_S2OPA0: S2 switch enable for OPA0
- \arg OPA_S3OPA0: S3 switch enable for OPA0
- \arg OPA_T3OPA1: T3 switch enable for OPA1
- \arg OPA_S1OPA1: S1 switch enable for OPA1
- \arg OPA_S2OPA1: S2 switch enable for OPA1
- \arg OPA_S3OPA1: S3 switch enable for OPA1
- \arg OPA_S4OPA1: S4 switch enable for OPA1
- \arg OPA_T3OPA2: T3 switch enable for OPA2
- \arg OPA_S1OPA2: S3 switch enable for OPA2
- \arg OPA_S2OPA2: S3 switch enable for OPA2
- \arg OPA_S3OPA2: S3 switch enable for OPA2
- \param[out] none
- \retval none
-*/
-void opa_switch_enable(uint32_t opax_swy)
-{
- OPA_CTL |= (uint32_t)(opax_swy);
-}
-
-/*!
- \brief enable OPA
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[out] none
- \retval none
-*/
-void opa_enable(uint32_t opa_periph)
-{
- if(OPA0 == opa_periph){
- OPA_CTL &= ~OPA_CTL_OPA0PD;
- }else if(OPA1 == opa_periph){
- OPA_CTL &= ~OPA_CTL_OPA1PD;
- }else{
- OPA_CTL &= ~OPA_CTL_OPA2PD;
- }
-}
-
-/*!
- \brief disable OPA
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[out] none
- \retval none
-*/
-void opa_disable(uint32_t opa_periph)
-{
- if(OPA0 == opa_periph){
- OPA_CTL |= OPA_CTL_OPA0PD;
- }else if(OPA1 == opa_periph){
- OPA_CTL |= OPA_CTL_OPA1PD;
- }else{
- OPA_CTL |= OPA_CTL_OPA2PD;
- }
-}
-
-/*!
- \brief disable OPA switch
- \param[in] opax_swy
- \arg OPA_T3OPA0: T3 switch enable for OPA0
- \arg OPA_S1OPA0: S1 switch enable for OPA0
- \arg OPA_S2OPA0: S2 switch enable for OPA0
- \arg OPA_S3OPA0: S3 switch enable for OPA0
- \arg OPA_T3OPA1: T3 switch enable for OPA1
- \arg OPA_S1OPA1: S1 switch enable for OPA1
- \arg OPA_S2OPA1: S2 switch enable for OPA1
- \arg OPA_S3OPA1: S3 switch enable for OPA1
- \arg OPA_S4OPA1: S4 switch enable for OPA1
- \arg OPA_T3OPA2: T3 switch enable for OPA2
- \arg OPA_S1OPA2: S3 switch enable for OPA2
- \arg OPA_S2OPA2: S3 switch enable for OPA2
- \arg OPA_S3OPA2: S3 switch enable for OPA2
- \param[out] none
- \retval none
-*/
-void opa_switch_disable(uint32_t opax_swy)
-{
- OPA_CTL &= ~opax_swy;
-}
-
-/*!
- \brief enable OPA in low power mode
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[out] none
- \retval none
-*/
-void opa_low_power_enable(uint32_t opa_periph)
-{
- if(OPA0 == opa_periph){
- OPA_CTL &= ~OPA_CTL_OPA0LPM;
- }else if(OPA1 == opa_periph){
- OPA_CTL &= ~OPA_CTL_OPA1LPM;
- }else{
- OPA_CTL &= ~OPA_CTL_OPA2LPM;
- }
-}
-
-/*!
- \brief disable OPA in low power mode
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[out] none
- \retval none
-*/
-void opa_low_power_disable(uint32_t opa_periph)
-{
- if(OPA0 == opa_periph){
- OPA_CTL |= OPA_CTL_OPA0LPM;
- }else if(OPA1 == opa_periph){
- OPA_CTL |= OPA_CTL_OPA1LPM;
- }else{
- OPA_CTL |= OPA_CTL_OPA2LPM;
- }
-}
-
-/*!
- \brief set OPA power range
- \param[in] powerrange
- \arg OPA_POWRANGE_LOW: Low power range is selected (VDDA is lower than 3.3V)
- \arg OPA_POWRANGE_HIGH: High power range is selected (VDDA is higher than 3.3V)
- \param[out] none
- \retval none
-*/
-void opa_power_range_config(uint32_t powerrange)
-{
- OPA_CTL &= ~OPA_CTL_OPA_RANGE;
- OPA_CTL |= powerrange;
-}
-
-/*!
- \brief set OPA bias trimming mode
- \param[in] opa_trimmode
- \arg OPA_BT_TRIM_FACTORY: factory trimming values are used for offset calibration
- \arg OPA_BT_TRIM_USER: user trimming values are used for offset calibration
- \param[out] none
- \retval none
-*/
-void opa_trim_mode_set(uint32_t opa_trimmode)
-{
- OPA_BT &= ~OPA_BT_OT_USER;
- OPA_BT |= opa_trimmode;
-}
-
-/*!
- \brief set OPA bias trimming value
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[in] opa_input
- \arg OPA_INPUT_P: PMOS input is selected to configure the trimming value
- \arg OPA_INPUT_N: NMOS input is selected to configure the trimming value
- \param[in] opa_trimmode
- \arg this parameter can be any value lower or equal to 0x0000001F.
- \param[out] none
- \retval none
-*/
-void opa_trim_value_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue)
-{
- uint32_t bt = 0U, ctl = 0U;
- ctl = OPA_CTL;
- bt = OPA_BT;
-
- if(OPA0 == opa_periph){
- /* clear the specified opa calibration for N diff and P diff */
- ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
- /* set the specified opa calibration for N diff or P diff */
- ctl |= opa_input;
- if(OPA_INPUT_P == opa_input){
- /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
- bt &= (~OPA_BT_OA0_TRIM_LOW);
- bt |= (opa_trimvalue);
- }else{
- /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
- bt &= (~OPA_BT_OA0_TRIM_HIGH);
- bt |= (opa_trimvalue << 5U);
- }
-
- }else if(OPA1 == opa_periph){
- ctl &= (uint32_t)~(OPA_CTL_OPA1CAL_L | OPA_CTL_OPA1CAL_H);
- ctl |= (uint32_t)(opa_input << 8U);
- if(OPA_INPUT_P == opa_input){
- /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
- bt &= (~OPA_BT_OA1_TRIM_LOW);
- bt |= (opa_trimvalue << 10U);
- }else{
- /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
- bt &= (~OPA_BT_OA1_TRIM_HIGH);
- bt |= (opa_trimvalue << 15U);
- }
- }else{
- ctl &= (uint32_t)~(OPA_CTL_OPA2CAL_L | OPA_CTL_OPA2CAL_H);
- ctl |= (uint32_t)(opa_input << 16U);
- if(OPA_INPUT_P == opa_input){
- /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
- bt &= (~OPA_BT_OA2_TRIM_LOW);
- bt |= (opa_trimvalue << 20U);
- }else{
- /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
- bt &= (~OPA_BT_OA2_TRIM_HIGH);
- bt |= (opa_trimvalue << 25U);
- }
- }
-
- OPA_CTL = ctl;
- OPA_BT = bt;
-}
-
-/*!
- \brief set OPA bias trimming value low power
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[in] opa_input
- \arg OPA_INPUT_P: PMOS input is selected to configure the trimming value
- \arg OPA_INPUT_N: NMOS input is selected to configure the trimming value
- \param[in] opa_trimmode
- \arg this parameter can be any value lower or equal to 0x0000001F.
- \param[out] none
- \retval none
-*/
-void opa_trim_value_lp_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue)
-{
- uint32_t lpbt = 0U, ctl = 0U;
- ctl = OPA_CTL;
- lpbt = OPA_LPBT;
-
- if(OPA0 == opa_periph){
- ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
- ctl |= opa_input;
- if(OPA_INPUT_P == opa_input){
- /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
- lpbt &= (~OPA_LPBT_OA0_TRIM_LOW);
- lpbt |= (opa_trimvalue);
- }else{
- /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
- lpbt &= (~OPA_LPBT_OA0_TRIM_HIGH);
- lpbt |= (opa_trimvalue << 5U);
- }
- }else if (OPA1 == opa_periph){
- ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
- ctl |= (uint32_t)(opa_input << 8U);
- if(OPA_INPUT_P == opa_input){
- /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
- lpbt &= (~OPA_LPBT_OA1_TRIM_LOW);
- lpbt |= (opa_trimvalue << 10U);
- }else{
- /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
- lpbt &= (~OPA_LPBT_OA1_TRIM_HIGH);
- lpbt |= (opa_trimvalue << 15U);
- }
-
- }else{
- ctl &= (uint32_t)~(OPA_CTL_OPA2CAL_L | OPA_CTL_OPA2CAL_H);
- ctl |= (uint32_t)(opa_input << 16U);
- if(OPA_INPUT_P == opa_input){
- /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
- lpbt &= (~OPA_LPBT_OA2_TRIM_LOW);
- lpbt |= (opa_trimvalue << 20U);
- }else{
- /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
- lpbt &= (~OPA_LPBT_OA2_TRIM_HIGH);
- lpbt |= (opa_trimvalue << 25U);
- }
- }
-
- OPA_CTL = ctl;
- OPA_LPBT = lpbt;
-}
-
-/*!
- \brief get OPA calibration flag
- \param[in] opa_periph
- \arg OPAx(x =0,1,2)
- \param[out] none
- \retval The state of the OPA calibration flag (SET or RESET)
-*/
-FlagStatus opa_cal_out_get(uint32_t opa_periph)
-{
- uint32_t data = 0U;
- FlagStatus bitstatus = RESET;
- data = OPA_CTL;
-
- if(OPA0 == opa_periph){
- /* get opa0 calibration output bit status */
- if ((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
- bitstatus = SET;
- }else{
- bitstatus = RESET;
- }
- }else if(OPA1 == opa_periph){
- /* get opa1 calibration output bit status */
- if ((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
- bitstatus = SET;
- }else{
- bitstatus = RESET;
- }
- }else{
- /* get opa2 calibration output bit status */
- if((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
- bitstatus = SET;
- }else{
- bitstatus = RESET;
- }
- }
- return bitstatus;
-}
-
-#endif /* GD32F170_190 */
+/*!
+ \file gd32f1x0_opa.c
+ \brief OPA driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifdef GD32F170_190
+
+#include "gd32f1x0_opa.h"
+
+/*!
+ \brief deinit the OPA register to its default reset value
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void opa_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_OPAIVREFRST);
+ rcu_periph_reset_disable(RCU_OPAIVREFRST);
+}
+
+/*!
+ \brief enable OPA switch
+ \param[in] opax_swy
+ \arg OPA_T3OPA0: T3 switch enable for OPA0
+ \arg OPA_S1OPA0: S1 switch enable for OPA0
+ \arg OPA_S2OPA0: S2 switch enable for OPA0
+ \arg OPA_S3OPA0: S3 switch enable for OPA0
+ \arg OPA_T3OPA1: T3 switch enable for OPA1
+ \arg OPA_S1OPA1: S1 switch enable for OPA1
+ \arg OPA_S2OPA1: S2 switch enable for OPA1
+ \arg OPA_S3OPA1: S3 switch enable for OPA1
+ \arg OPA_S4OPA1: S4 switch enable for OPA1
+ \arg OPA_T3OPA2: T3 switch enable for OPA2
+ \arg OPA_S1OPA2: S3 switch enable for OPA2
+ \arg OPA_S2OPA2: S3 switch enable for OPA2
+ \arg OPA_S3OPA2: S3 switch enable for OPA2
+ \param[out] none
+ \retval none
+*/
+void opa_switch_enable(uint32_t opax_swy)
+{
+ OPA_CTL |= (uint32_t)(opax_swy);
+}
+
+/*!
+ \brief enable OPA
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[out] none
+ \retval none
+*/
+void opa_enable(uint32_t opa_periph)
+{
+ if(OPA0 == opa_periph){
+ OPA_CTL &= ~OPA_CTL_OPA0PD;
+ }else if(OPA1 == opa_periph){
+ OPA_CTL &= ~OPA_CTL_OPA1PD;
+ }else{
+ OPA_CTL &= ~OPA_CTL_OPA2PD;
+ }
+}
+
+/*!
+ \brief disable OPA
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[out] none
+ \retval none
+*/
+void opa_disable(uint32_t opa_periph)
+{
+ if(OPA0 == opa_periph){
+ OPA_CTL |= OPA_CTL_OPA0PD;
+ }else if(OPA1 == opa_periph){
+ OPA_CTL |= OPA_CTL_OPA1PD;
+ }else{
+ OPA_CTL |= OPA_CTL_OPA2PD;
+ }
+}
+
+/*!
+ \brief disable OPA switch
+ \param[in] opax_swy
+ \arg OPA_T3OPA0: T3 switch enable for OPA0
+ \arg OPA_S1OPA0: S1 switch enable for OPA0
+ \arg OPA_S2OPA0: S2 switch enable for OPA0
+ \arg OPA_S3OPA0: S3 switch enable for OPA0
+ \arg OPA_T3OPA1: T3 switch enable for OPA1
+ \arg OPA_S1OPA1: S1 switch enable for OPA1
+ \arg OPA_S2OPA1: S2 switch enable for OPA1
+ \arg OPA_S3OPA1: S3 switch enable for OPA1
+ \arg OPA_S4OPA1: S4 switch enable for OPA1
+ \arg OPA_T3OPA2: T3 switch enable for OPA2
+ \arg OPA_S1OPA2: S3 switch enable for OPA2
+ \arg OPA_S2OPA2: S3 switch enable for OPA2
+ \arg OPA_S3OPA2: S3 switch enable for OPA2
+ \param[out] none
+ \retval none
+*/
+void opa_switch_disable(uint32_t opax_swy)
+{
+ OPA_CTL &= ~opax_swy;
+}
+
+/*!
+ \brief enable OPA in low power mode
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[out] none
+ \retval none
+*/
+void opa_low_power_enable(uint32_t opa_periph)
+{
+ if(OPA0 == opa_periph){
+ OPA_CTL &= ~OPA_CTL_OPA0LPM;
+ }else if(OPA1 == opa_periph){
+ OPA_CTL &= ~OPA_CTL_OPA1LPM;
+ }else{
+ OPA_CTL &= ~OPA_CTL_OPA2LPM;
+ }
+}
+
+/*!
+ \brief disable OPA in low power mode
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[out] none
+ \retval none
+*/
+void opa_low_power_disable(uint32_t opa_periph)
+{
+ if(OPA0 == opa_periph){
+ OPA_CTL |= OPA_CTL_OPA0LPM;
+ }else if(OPA1 == opa_periph){
+ OPA_CTL |= OPA_CTL_OPA1LPM;
+ }else{
+ OPA_CTL |= OPA_CTL_OPA2LPM;
+ }
+}
+
+/*!
+ \brief set OPA power range
+ \param[in] powerrange
+ \arg OPA_POWRANGE_LOW: Low power range is selected (VDDA is lower than 3.3V)
+ \arg OPA_POWRANGE_HIGH: High power range is selected (VDDA is higher than 3.3V)
+ \param[out] none
+ \retval none
+*/
+void opa_power_range_config(uint32_t powerrange)
+{
+ OPA_CTL &= ~OPA_CTL_OPA_RANGE;
+ OPA_CTL |= powerrange;
+}
+
+/*!
+ \brief set OPA bias trimming mode
+ \param[in] opa_trimmode
+ \arg OPA_BT_TRIM_FACTORY: factory trimming values are used for offset calibration
+ \arg OPA_BT_TRIM_USER: user trimming values are used for offset calibration
+ \param[out] none
+ \retval none
+*/
+void opa_trim_mode_set(uint32_t opa_trimmode)
+{
+ OPA_BT &= ~OPA_BT_OT_USER;
+ OPA_BT |= opa_trimmode;
+}
+
+/*!
+ \brief set OPA bias trimming value
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[in] opa_input
+ \arg OPA_INPUT_P: PMOS input is selected to configure the trimming value
+ \arg OPA_INPUT_N: NMOS input is selected to configure the trimming value
+ \param[in] opa_trimmode
+ \arg this parameter can be any value lower or equal to 0x0000001F.
+ \param[out] none
+ \retval none
+*/
+void opa_trim_value_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue)
+{
+ uint32_t bt = 0U, ctl = 0U;
+ ctl = OPA_CTL;
+ bt = OPA_BT;
+
+ if(OPA0 == opa_periph){
+ /* clear the specified opa calibration for N diff and P diff */
+ ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
+ /* set the specified opa calibration for N diff or P diff */
+ ctl |= opa_input;
+ if(OPA_INPUT_P == opa_input){
+ /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
+ bt &= (~OPA_BT_OA0_TRIM_LOW);
+ bt |= (opa_trimvalue);
+ }else{
+ /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
+ bt &= (~OPA_BT_OA0_TRIM_HIGH);
+ bt |= (opa_trimvalue << 5U);
+ }
+
+ }else if(OPA1 == opa_periph){
+ ctl &= (uint32_t)~(OPA_CTL_OPA1CAL_L | OPA_CTL_OPA1CAL_H);
+ ctl |= (uint32_t)(opa_input << 8U);
+ if(OPA_INPUT_P == opa_input){
+ /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
+ bt &= (~OPA_BT_OA1_TRIM_LOW);
+ bt |= (opa_trimvalue << 10U);
+ }else{
+ /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
+ bt &= (~OPA_BT_OA1_TRIM_HIGH);
+ bt |= (opa_trimvalue << 15U);
+ }
+ }else{
+ ctl &= (uint32_t)~(OPA_CTL_OPA2CAL_L | OPA_CTL_OPA2CAL_H);
+ ctl |= (uint32_t)(opa_input << 16U);
+ if(OPA_INPUT_P == opa_input){
+ /* clear the specified PMOS pairs normal mode 5-bit offset trim value */
+ bt &= (~OPA_BT_OA2_TRIM_LOW);
+ bt |= (opa_trimvalue << 20U);
+ }else{
+ /* clear the specified NMOS pairs normal mode 5-bit offset trim value */
+ bt &= (~OPA_BT_OA2_TRIM_HIGH);
+ bt |= (opa_trimvalue << 25U);
+ }
+ }
+
+ OPA_CTL = ctl;
+ OPA_BT = bt;
+}
+
+/*!
+ \brief set OPA bias trimming value low power
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[in] opa_input
+ \arg OPA_INPUT_P: PMOS input is selected to configure the trimming value
+ \arg OPA_INPUT_N: NMOS input is selected to configure the trimming value
+ \param[in] opa_trimmode
+ \arg this parameter can be any value lower or equal to 0x0000001F.
+ \param[out] none
+ \retval none
+*/
+void opa_trim_value_lp_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue)
+{
+ uint32_t lpbt = 0U, ctl = 0U;
+ ctl = OPA_CTL;
+ lpbt = OPA_LPBT;
+
+ if(OPA0 == opa_periph){
+ ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
+ ctl |= opa_input;
+ if(OPA_INPUT_P == opa_input){
+ /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
+ lpbt &= (~OPA_LPBT_OA0_TRIM_LOW);
+ lpbt |= (opa_trimvalue);
+ }else{
+ /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
+ lpbt &= (~OPA_LPBT_OA0_TRIM_HIGH);
+ lpbt |= (opa_trimvalue << 5U);
+ }
+ }else if (OPA1 == opa_periph){
+ ctl &= (uint32_t)~(OPA_CTL_OPA0CAL_L | OPA_CTL_OPA0CAL_H);
+ ctl |= (uint32_t)(opa_input << 8U);
+ if(OPA_INPUT_P == opa_input){
+ /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
+ lpbt &= (~OPA_LPBT_OA1_TRIM_LOW);
+ lpbt |= (opa_trimvalue << 10U);
+ }else{
+ /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
+ lpbt &= (~OPA_LPBT_OA1_TRIM_HIGH);
+ lpbt |= (opa_trimvalue << 15U);
+ }
+
+ }else{
+ ctl &= (uint32_t)~(OPA_CTL_OPA2CAL_L | OPA_CTL_OPA2CAL_H);
+ ctl |= (uint32_t)(opa_input << 16U);
+ if(OPA_INPUT_P == opa_input){
+ /* clear the specified PMOS pairs low power mode 5-bit offset trim value */
+ lpbt &= (~OPA_LPBT_OA2_TRIM_LOW);
+ lpbt |= (opa_trimvalue << 20U);
+ }else{
+ /* clear the specified NMOS pairs low power mode 5-bit offset trim value */
+ lpbt &= (~OPA_LPBT_OA2_TRIM_HIGH);
+ lpbt |= (opa_trimvalue << 25U);
+ }
+ }
+
+ OPA_CTL = ctl;
+ OPA_LPBT = lpbt;
+}
+
+/*!
+ \brief get OPA calibration flag
+ \param[in] opa_periph
+ \arg OPAx(x =0,1,2)
+ \param[out] none
+ \retval The state of the OPA calibration flag (SET or RESET)
+*/
+FlagStatus opa_cal_out_get(uint32_t opa_periph)
+{
+ uint32_t data = 0U;
+ FlagStatus bitstatus = RESET;
+ data = OPA_CTL;
+
+ if(OPA0 == opa_periph){
+ /* get opa0 calibration output bit status */
+ if ((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
+ bitstatus = SET;
+ }else{
+ bitstatus = RESET;
+ }
+ }else if(OPA1 == opa_periph){
+ /* get opa1 calibration output bit status */
+ if ((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
+ bitstatus = SET;
+ }else{
+ bitstatus = RESET;
+ }
+ }else{
+ /* get opa2 calibration output bit status */
+ if((uint32_t)RESET != (data & OPA_CTL_OPA1CALOUT)){
+ bitstatus = SET;
+ }else{
+ bitstatus = RESET;
+ }
+ }
+ return bitstatus;
+}
+
+#endif /* GD32F170_190 */
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_pmu.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_pmu.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_pmu.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_pmu.c
index cfd142ae..ee594e64 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_pmu.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_pmu.c
@@ -1,257 +1,257 @@
-/*!
- \file gd32f1x0_pmu.c
- \brief PMU driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_pmu.h"
-
-/*!
- \brief reset PMU register
- \param[in] none
- \param[out] none
- \retval none
-*/
-void pmu_deinit(void)
-{
- /* reset PMU */
- rcu_periph_reset_enable(RCU_PMURST);
- rcu_periph_reset_disable(RCU_PMURST);
-}
-
-/*!
- \brief select low voltage detector threshold
- \param[in] lvdt_n:
- \arg PMU_LVDT_0: voltage threshold is 2.2V (GD32F130_150) or 2.4V (GD32F170_190)
- \arg PMU_LVDT_1: voltage threshold is 2.3V (GD32F130_150) or 2.7V (GD32F170_190)
- \arg PMU_LVDT_2: voltage threshold is 2.4V (GD32F130_150) or 3.0V (GD32F170_190)
- \arg PMU_LVDT_3: voltage threshold is 2.5V (GD32F130_150) or 3.3V (GD32F170_190)
- \arg PMU_LVDT_4: voltage threshold is 2.6V (GD32F130_150) or 3.6V (GD32F170_190)
- \arg PMU_LVDT_5: voltage threshold is 2.7V (GD32F130_150) or 3.9V (GD32F170_190)
- \arg PMU_LVDT_6: voltage threshold is 2.8V (GD32F130_150) or 4.2V (GD32F170_190)
- \arg PMU_LVDT_7: voltage threshold is 2.9V (GD32F130_150) or 4.5V (GD32F170_190)
- \param[out] none
- \retval none
-*/
-void pmu_lvd_select(uint32_t lvdt_n)
-{
- /* disable LVD */
- PMU_CTL &= ~PMU_CTL_LVDEN;
- /* clear LVDT bits */
- PMU_CTL &= ~PMU_CTL_LVDT;
- /* set LVDT bits according to lvdt_n */
- PMU_CTL |= lvdt_n;
- /* enable LVD */
- PMU_CTL |= PMU_CTL_LVDEN;
-
-}
-
-/*!
- \brief PMU lvd disable
- \param[in] none
- \param[out] none
- \retval none
-*/
-void pmu_lvd_disable(void)
-{
- /* disable LVD */
- PMU_CTL &= ~PMU_CTL_LVDEN;
-}
-
-/*!
- \brief PMU work at sleep mode
- \param[in] sleepmodecmd:
- \arg WFI_CMD: use WFI command
- \arg WFE_CMD: use WFE command
- \param[out] none
- \retval none
-*/
-void pmu_to_sleepmode(uint8_t sleepmodecmd)
-{
- /* clear sleepdeep bit of Cortex-M3 system control register */
- SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
- /* select WFI or WFE command to enter sleep mode */
- if(WFI_CMD == sleepmodecmd){
- __WFI();
- }else{
- __WFE();
- }
-}
-
-/*!
- \brief PMU work at deepsleep mode
- \param[in] ldo
- \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
- \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
- \param[in] deepsleepmodecmd:
- \arg WFI_CMD: use WFI command
- \arg WFE_CMD: use WFE command
- \param[out] none
- \retval none
-*/
-void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
-{
- static uint32_t reg_snap[ 4 ];
- /* clear stbmod and ldolp bits */
- PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
-
- /* set ldolp bit according to pmu_ldo */
- PMU_CTL |= ldo;
-
- /* set sleepdeep bit of Cortex-M3 system control register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- reg_snap[ 0 ] = REG32( 0xE000E010 );
- reg_snap[ 1 ] = REG32( 0xE000E100 );
- reg_snap[ 2 ] = REG32( 0xE000E104 );
- reg_snap[ 3 ] = REG32( 0xE000E108 );
-
- REG32( 0xE000E010 ) &= 0x00010004;
- REG32( 0xE000E180 ) = 0XB7FFEF19;
- REG32( 0xE000E184 ) = 0XFFFFFBFF;
- REG32( 0xE000E188 ) = 0xFFFFFFFF;
-
- /* select WFI or WFE command to enter deepsleep mode */
- if(WFI_CMD == deepsleepmodecmd){
- __WFI();
- }else{
- __SEV();
- __WFE();
- __WFE();
- }
-
- REG32( 0xE000E010 ) = reg_snap[ 0 ] ;
- REG32( 0xE000E100 ) = reg_snap[ 1 ] ;
- REG32( 0xE000E104 ) = reg_snap[ 2 ] ;
- REG32( 0xE000E108 ) = reg_snap[ 3 ] ;
-
- /* reset sleepdeep bit of Cortex-M3 system control register */
- SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-}
-
-/*!
- \brief pmu work at standby mode
- \param[in] standbymodecmd:
- \arg WFI_CMD: use WFI command
- \arg WFE_CMD: use WFE command
- \param[out] none
- \retval none
-*/
-void pmu_to_standbymode(uint8_t standbymodecmd)
-{
- /* set sleepdeep bit of Cortex-M3 system control register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* set stbmod bit */
- PMU_CTL |= PMU_CTL_STBMOD;
-
- /* reset wakeup flag */
- PMU_CTL |= PMU_CTL_WURST;
-
- /* select WFI or WFE command to enter standby mode */
- if(WFI_CMD == standbymodecmd){
- __WFI();
- }else{
- __WFE();
- }
-}
-
-/*!
- \brief clear flag bit
- \param[in] flag_reset:
- \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
- \arg PMU_FLAG_RESET_STANDBY: reset standby flag
- \param[out] none
- \retval none
-*/
-void pmu_flag_clear(uint32_t flag_reset)
-{
- switch(flag_reset){
- case PMU_FLAG_RESET_WAKEUP:
- /* reset wakeup flag */
- PMU_CTL |= PMU_CTL_WURST;
- break;
- case PMU_FLAG_RESET_STANDBY:
- /* reset standby flag */
- PMU_CTL |= PMU_CTL_STBRST;
- break;
- default :
- break;
- }
-}
-
-/*!
- \brief get flag state
- \param[in] flag:
- \arg PMU_FLAG_WAKEUP: wakeup flag
- \arg PMU_FLAG_STANDBY: standby flag
- \arg PMU_FLAG_LVD: lvd flag
- \param[out] none
- \retval FlagStatus SET or RESET
-*/
-FlagStatus pmu_flag_get(uint32_t flag )
-{
- if(PMU_CS & flag){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief backup domain write enable
- \param[in] none
- \param[out] none
- \retval none
-*/
-void pmu_backup_write_enable(void)
-{
- PMU_CTL |= PMU_CTL_BKPWEN;
-}
-
-/*!
- \brief backup domain write disable
- \param[in] none
- \param[out] none
- \retval none
-*/
-void pmu_backup_write_disable(void)
-{
- PMU_CTL &= ~PMU_CTL_BKPWEN;
-}
-
-/*!
- \brief wakeup pin enable
- \param[in] wakeup_pin:
- \arg PMU_WAKEUP_PIN0: wakeup pin 0
- \arg PMU_WAKEUP_PIN1: wakeup pin 1
- \param[out] none
- \retval none
-*/
-void pmu_wakeup_pin_enable(uint32_t wakeup_pin )
-{
- PMU_CS |= wakeup_pin;
-}
-
-/*!
- \brief wakeup pin disable
- \param[in] wakeup_pin:
- \arg PMU_WAKEUP_PIN0: wakeup pin 0
- \arg PMU_WAKEUP_PIN1: wakeup pin 1
- \param[out] none
- \retval none
-*/
-void pmu_wakeup_pin_disable(uint32_t wakeup_pin )
-{
- PMU_CS &= ~wakeup_pin;
-
-}
+/*!
+ \file gd32f1x0_pmu.c
+ \brief PMU driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_pmu.h"
+
+/*!
+ \brief reset PMU register
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_deinit(void)
+{
+ /* reset PMU */
+ rcu_periph_reset_enable(RCU_PMURST);
+ rcu_periph_reset_disable(RCU_PMURST);
+}
+
+/*!
+ \brief select low voltage detector threshold
+ \param[in] lvdt_n:
+ \arg PMU_LVDT_0: voltage threshold is 2.2V (GD32F130_150) or 2.4V (GD32F170_190)
+ \arg PMU_LVDT_1: voltage threshold is 2.3V (GD32F130_150) or 2.7V (GD32F170_190)
+ \arg PMU_LVDT_2: voltage threshold is 2.4V (GD32F130_150) or 3.0V (GD32F170_190)
+ \arg PMU_LVDT_3: voltage threshold is 2.5V (GD32F130_150) or 3.3V (GD32F170_190)
+ \arg PMU_LVDT_4: voltage threshold is 2.6V (GD32F130_150) or 3.6V (GD32F170_190)
+ \arg PMU_LVDT_5: voltage threshold is 2.7V (GD32F130_150) or 3.9V (GD32F170_190)
+ \arg PMU_LVDT_6: voltage threshold is 2.8V (GD32F130_150) or 4.2V (GD32F170_190)
+ \arg PMU_LVDT_7: voltage threshold is 2.9V (GD32F130_150) or 4.5V (GD32F170_190)
+ \param[out] none
+ \retval none
+*/
+void pmu_lvd_select(uint32_t lvdt_n)
+{
+ /* disable LVD */
+ PMU_CTL &= ~PMU_CTL_LVDEN;
+ /* clear LVDT bits */
+ PMU_CTL &= ~PMU_CTL_LVDT;
+ /* set LVDT bits according to lvdt_n */
+ PMU_CTL |= lvdt_n;
+ /* enable LVD */
+ PMU_CTL |= PMU_CTL_LVDEN;
+
+}
+
+/*!
+ \brief PMU lvd disable
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_lvd_disable(void)
+{
+ /* disable LVD */
+ PMU_CTL &= ~PMU_CTL_LVDEN;
+}
+
+/*!
+ \brief PMU work at sleep mode
+ \param[in] sleepmodecmd:
+ \arg WFI_CMD: use WFI command
+ \arg WFE_CMD: use WFE command
+ \param[out] none
+ \retval none
+*/
+void pmu_to_sleepmode(uint8_t sleepmodecmd)
+{
+ /* clear sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ /* select WFI or WFE command to enter sleep mode */
+ if(WFI_CMD == sleepmodecmd){
+ __WFI();
+ }else{
+ __WFE();
+ }
+}
+
+/*!
+ \brief PMU work at deepsleep mode
+ \param[in] ldo
+ \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
+ \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
+ \param[in] deepsleepmodecmd:
+ \arg WFI_CMD: use WFI command
+ \arg WFE_CMD: use WFE command
+ \param[out] none
+ \retval none
+*/
+void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
+{
+ static uint32_t reg_snap[ 4 ];
+ /* clear stbmod and ldolp bits */
+ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
+
+ /* set ldolp bit according to pmu_ldo */
+ PMU_CTL |= ldo;
+
+ /* set sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ reg_snap[ 0 ] = REG32( 0xE000E010 );
+ reg_snap[ 1 ] = REG32( 0xE000E100 );
+ reg_snap[ 2 ] = REG32( 0xE000E104 );
+ reg_snap[ 3 ] = REG32( 0xE000E108 );
+
+ REG32( 0xE000E010 ) &= 0x00010004;
+ REG32( 0xE000E180 ) = 0XB7FFEF19;
+ REG32( 0xE000E184 ) = 0XFFFFFBFF;
+ REG32( 0xE000E188 ) = 0xFFFFFFFF;
+
+ /* select WFI or WFE command to enter deepsleep mode */
+ if(WFI_CMD == deepsleepmodecmd){
+ __WFI();
+ }else{
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ REG32( 0xE000E010 ) = reg_snap[ 0 ] ;
+ REG32( 0xE000E100 ) = reg_snap[ 1 ] ;
+ REG32( 0xE000E104 ) = reg_snap[ 2 ] ;
+ REG32( 0xE000E108 ) = reg_snap[ 3 ] ;
+
+ /* reset sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/*!
+ \brief pmu work at standby mode
+ \param[in] standbymodecmd:
+ \arg WFI_CMD: use WFI command
+ \arg WFE_CMD: use WFE command
+ \param[out] none
+ \retval none
+*/
+void pmu_to_standbymode(uint8_t standbymodecmd)
+{
+ /* set sleepdeep bit of Cortex-M3 system control register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* set stbmod bit */
+ PMU_CTL |= PMU_CTL_STBMOD;
+
+ /* reset wakeup flag */
+ PMU_CTL |= PMU_CTL_WURST;
+
+ /* select WFI or WFE command to enter standby mode */
+ if(WFI_CMD == standbymodecmd){
+ __WFI();
+ }else{
+ __WFE();
+ }
+}
+
+/*!
+ \brief clear flag bit
+ \param[in] flag_reset:
+ \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
+ \arg PMU_FLAG_RESET_STANDBY: reset standby flag
+ \param[out] none
+ \retval none
+*/
+void pmu_flag_clear(uint32_t flag_reset)
+{
+ switch(flag_reset){
+ case PMU_FLAG_RESET_WAKEUP:
+ /* reset wakeup flag */
+ PMU_CTL |= PMU_CTL_WURST;
+ break;
+ case PMU_FLAG_RESET_STANDBY:
+ /* reset standby flag */
+ PMU_CTL |= PMU_CTL_STBRST;
+ break;
+ default :
+ break;
+ }
+}
+
+/*!
+ \brief get flag state
+ \param[in] flag:
+ \arg PMU_FLAG_WAKEUP: wakeup flag
+ \arg PMU_FLAG_STANDBY: standby flag
+ \arg PMU_FLAG_LVD: lvd flag
+ \param[out] none
+ \retval FlagStatus SET or RESET
+*/
+FlagStatus pmu_flag_get(uint32_t flag )
+{
+ if(PMU_CS & flag){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief backup domain write enable
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_backup_write_enable(void)
+{
+ PMU_CTL |= PMU_CTL_BKPWEN;
+}
+
+/*!
+ \brief backup domain write disable
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void pmu_backup_write_disable(void)
+{
+ PMU_CTL &= ~PMU_CTL_BKPWEN;
+}
+
+/*!
+ \brief wakeup pin enable
+ \param[in] wakeup_pin:
+ \arg PMU_WAKEUP_PIN0: wakeup pin 0
+ \arg PMU_WAKEUP_PIN1: wakeup pin 1
+ \param[out] none
+ \retval none
+*/
+void pmu_wakeup_pin_enable(uint32_t wakeup_pin )
+{
+ PMU_CS |= wakeup_pin;
+}
+
+/*!
+ \brief wakeup pin disable
+ \param[in] wakeup_pin:
+ \arg PMU_WAKEUP_PIN0: wakeup pin 0
+ \arg PMU_WAKEUP_PIN1: wakeup pin 1
+ \param[out] none
+ \retval none
+*/
+void pmu_wakeup_pin_disable(uint32_t wakeup_pin )
+{
+ PMU_CS &= ~wakeup_pin;
+
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_rcu.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_rcu.c
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_rcu.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_rcu.c
index 11fddb47..02f13de9 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_rcu.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_rcu.c
@@ -1,1214 +1,1214 @@
-/*!
- \file gd32f1x0_rcu.c
- \brief RCU driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_rcu.h"
-
-#define SEL_IRC8M 0x00U
-#define SEL_HXTAL 0x01U
-#define SEL_PLL 0x02U
-
-/* define startup timeout count */
-#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
-#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)
-
-/*!
- \brief deinitialize the RCU
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_deinit(void)
-{
- /* enable IRC8M */
- RCU_CTL0 |= RCU_CTL0_IRC8MEN;
- while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
- }
- /* reset RCU */
-#ifdef GD32F130_150
- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
- RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
-#elif defined (GD32F170_190)
- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
- RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
-#endif /* GD32F130_150 */
- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
-#ifdef GD32F130_150
- RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
-#endif /* GD32F130_150 */
- RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
- RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
- RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
-#ifdef GD32F130_150
- RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
-#elif defined (GD32F170_190)
- RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
- RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
- RCU_CFG3 &= ~RCU_CFG3_CKOUT1SRC;
- RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
-#endif /* GD32F130_150 */
- RCU_INT = 0x00000000U;
-}
-
-/*!
- \brief enable the peripherals clock
- \param[in] periph: RCU peripherals, refer to rcu_periph_enum
- \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
- \arg RCU_DMA: DMA clock
- \arg RCU_CRC: CRC clock
- \arg RCU_TSI: TSI clock
- \arg RCU_CFGCMP: CFGCMP clock
- \arg RCU_ADC: ADC clock
- \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock
- \arg RCU_SPIx (x=0,1,2): SPI clock
- \arg RCU_USARTx (x=0,1): USART clock
- \arg RCU_SLCD: SLCD clock, only in GD32F170_190
- \arg RCU_WWDGT: WWDGT clock
- \arg RCU_I2Cx (x=0,1,2): I2C clock
- \arg RCU_USBD: USBD clock, only in GD32F130_150
- \arg RCU_CANx (x=0,1): CAN clock, only in GD32F170_190
- \arg RCU_PMU: PMU clock
- \arg RCU_DAC: DAC clock
- \arg RCU_CEC: CEC clock
- \arg RCU_OPAIVREF: OPAIVREF clock, only in GD32F170_190
- \arg RCU_RTC: RTC clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_enable(rcu_periph_enum periph)
-{
- RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief disable the peripherals clock
- \param[in] periph: RCU peripherals, refer to rcu_periph_enum
- \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
- \arg RCU_DMA: DMA clock
- \arg RCU_CRC: CRC clock
- \arg RCU_TSI: TSI clock
- \arg RCU_CFGCMP: CFGCMP clock
- \arg RCU_ADC: ADC clock
- \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock
- \arg RCU_SPIx (x=0,1,2): SPI clock
- \arg RCU_USARTx (x=0,1): USART clock
- \arg RCU_SLCD: SLCD clock, only in GD32F170_190
- \arg RCU_WWDGT: WWDGT clock
- \arg RCU_I2Cx (x=0,1,2): I2C clock
- \arg RCU_USBD: USBD clock only in GD32F130_150
- \arg RCU_CANx (x=0,1): CAN clock, only in GD32F170_190
- \arg RCU_PMU: PMU clock
- \arg RCU_DAC: DAC clock
- \arg RCU_CEC: CEC clock
- \arg RCU_OPAIVREF: OPAIVREF clock, only in GD32F170_190
- \arg RCU_RTC: RTC clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_disable(rcu_periph_enum periph)
-{
- RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief enable the peripherals clock when sleep mode
- \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_FMC_SLP: FMC clock
- \arg RCU_SRAM_SLP: SRAM clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
-{
- RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief disable the peripherals clock when sleep mode
- \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
- only one parameter can be selected which is shown as below:
- \arg RCU_FMC_SLP: FMC clock
- \arg RCU_SRAM_SLP: SRAM clock
- \param[out] none
- \retval none
-*/
-void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
-{
- RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
-}
-
-/*!
- \brief reset the peripherals
- \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
- \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
- \arg RCU_TSIRST: reset TSI
- \arg RCU_CFGCMPRST: reset CFGCMP
- \arg RCU_ADCRST: reset ADC
- \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER
- \arg RCU_SPIxRST (x=0,1,2): reset SPI
- \arg RCU_USARTxRST (x=0,1): reset USART
- \arg RCU_SLCDRST: reset SLCD, only in GD32F170_190
- \arg RCU_WWDGTRST: reset WWDGT
- \arg RCU_I2CxRST (x=0,1,2): reset I2C
- \arg RCU_USBDRST: reset USBD, only in GD32F130_150
- \arg RCU_CANxRST (x=0,1): reset CAN, only in GD32F170_190
- \arg RCU_PMURST: reset PMU
- \arg RCU_DACRST: reset DAC
- \arg RCU_CECRST: reset CEC
- \arg RCU_OPAIVREFRST: reset OPAIVREF, only in GD32F170_190
- \param[out] none
- \retval none
-*/
-void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
-{
- RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
-}
-
-/*!
- \brief disable reset the peripheral
- \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
- \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
- \arg RCU_TSIRST: reset TSI
- \arg RCU_CFGCMPRST: reset CFGCMP
- \arg RCU_ADCRST: reset ADC
- \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER
- \arg RCU_SPIxRST (x=0,1,2): reset SPI
- \arg RCU_USARTxRST (x=0,1): reset USART
- \arg RCU_SLCDRST: reset SLCD, only in GD32F170_190
- \arg RCU_WWDGTRST: reset WWDGT
- \arg RCU_I2CxRST (x=0,1,2): reset I2C
- \arg RCU_USBDRST: reset USBD, only in GD32F130_150
- \arg RCU_CANxRST (x=0,1): reset CAN, only in GD32F170_190
- \arg RCU_PMURST: reset PMU
- \arg RCU_DACRST: reset DAC
- \arg RCU_CECRST: reset CEC
- \arg RCU_OPAIVREFRST: reset OPAIVREF, only in GD32F170_190
- \param[out] none
- \retval none
-*/
-void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
-{
- RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
-}
-
-/*!
- \brief reset the BKP domain
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_bkp_reset_enable(void)
-{
- RCU_BDCTL |= RCU_BDCTL_BKPRST;
-}
-
-/*!
- \brief disable the BKP domain reset
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_bkp_reset_disable(void)
-{
- RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
-}
-
-/*!
- \brief configure the system clock source
- \param[in] ck_sys: system clock source select
- \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
- \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
- \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
- \param[out] none
- \retval none
-*/
-void rcu_system_clock_source_config(uint32_t ck_sys)
-{
- uint32_t cksys_source = 0U;
- cksys_source = RCU_CFG0;
- /* reset the SCS bits and set according to ck_sys */
- cksys_source &= ~RCU_CFG0_SCS;
- RCU_CFG0 = (ck_sys | cksys_source);
-}
-
-/*!
- \brief get the system clock source
- \param[in] none
- \param[out] none
- \retval which clock is selected as CK_SYS source
- \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source
- \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source
- \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source
-*/
-uint32_t rcu_system_clock_source_get(void)
-{
- return (RCU_CFG0 & 0x0000000CU);
-}
-
-/*!
- \brief configure the AHB clock prescaler selection
- \param[in] ck_ahb: AHB clock prescaler selection
- \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
- \param[out] none
- \retval none
-*/
-void rcu_ahb_clock_config(uint32_t ck_ahb)
-{
- uint32_t ahbpsc = 0U;
- ahbpsc = RCU_CFG0;
- /* reset the AHBPSC bits and set according to ck_ahb */
- ahbpsc &= ~RCU_CFG0_AHBPSC;
- RCU_CFG0 = (ck_ahb | ahbpsc);
-}
-
-/*!
- \brief configure the APB1 clock prescaler selection
- \param[in] ck_apb1: APB1 clock prescaler selection
- \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
- \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
- \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
- \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
- \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
- \param[out] none
- \retval none
-*/
-void rcu_apb1_clock_config(uint32_t ck_apb1)
-{
- uint32_t apb1psc = 0U;
- apb1psc = RCU_CFG0;
- /* reset the APB1PSC and set according to ck_apb1 */
- apb1psc &= ~RCU_CFG0_APB1PSC;
- RCU_CFG0 = (ck_apb1 | apb1psc);
-}
-
-/*!
- \brief configure the APB2 clock prescaler selection
- \param[in] ck_apb2: APB2 clock prescaler selection
- \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
- \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
- \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
- \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
- \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
- \param[out] none
- \retval none
-*/
-void rcu_apb2_clock_config(uint32_t ck_apb2)
-{
- uint32_t apb2psc = 0U;
- apb2psc = RCU_CFG0;
- /* reset the APB2PSC and set according to ck_apb2 */
- apb2psc &= ~RCU_CFG0_APB2PSC;
- RCU_CFG0 = (ck_apb2 | apb2psc);
-}
-
-/*!
- \brief configure the ADC clock prescaler selection
- \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum
- \arg RCU_ADCCK_IRC14M: select CK_IRC14M as CK_ADC, only in GD32F130_150
- \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC, only in GD32F170_190
- \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC, only in GD32F170_190
- \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC
- \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC
- \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC
- \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC
- \param[out] none
- \retval none
-*/
-void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
-{
- /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
- RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
-#ifdef GD32F130_150
- RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
-#elif defined (GD32F170_190)
- RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV);
-#endif /* GD32F130_150 */
- /* set the ADC clock according to ck_adc */
- switch(ck_adc){
-#ifdef GD32F130_150
- case RCU_ADCCK_IRC14M:
- RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
- break;
-#elif defined (GD32F170_190)
- case RCU_ADCCK_IRC28M_DIV2:
- RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
- RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
- break;
- case RCU_ADCCK_IRC28M:
- RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
- RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
- break;
-#endif /* GD32F130_150 */
- case RCU_ADCCK_APB2_DIV2:
- RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
- RCU_CFG2 |= RCU_CFG2_ADCSEL;
- break;
- case RCU_ADCCK_APB2_DIV4:
- RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
- RCU_CFG2 |= RCU_CFG2_ADCSEL;
- break;
- case RCU_ADCCK_APB2_DIV6:
- RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
- RCU_CFG2 |= RCU_CFG2_ADCSEL;
- break;
- case RCU_ADCCK_APB2_DIV8:
- RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
- RCU_CFG2 |= RCU_CFG2_ADCSEL;
- break;
- default:
- break;
- }
-}
-
-#ifdef GD32F130_150
-/*!
- \brief configure the USBD clock prescaler selection
- \param[in] ck_usbd: USBD clock prescaler selection
- \arg RCU_USBD_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBD
- \arg RCU_USBD_CKPLL_DIV1: select CK_PLL as CK_USBD
- \arg RCU_USBD_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBD
- \arg RCU_USBD_CKPLL_DIV2: select CK_PLL/2 as CK_USBD
- \param[out] none
- \retval none
-*/
-void rcu_usbd_clock_config(uint32_t ck_usbd)
-{
- /* reset the USBDPSC bits and set according to ck_usbd */
- RCU_CFG0 &= ~RCU_CFG0_USBDPSC;
- RCU_CFG0 |= ck_usbd;
-}
-
-/*!
- \brief configure the CK_OUT clock source and divider
- \param[in] ckout_src: CK_OUT clock source selection
- \arg RCU_CKOUTSRC_NONE: no clock selected
- \arg RCU_CKOUTSRC_IRC14M: IRC14M selected
- \arg RCU_CKOUTSRC_IRC40K: IRC40K selected
- \arg RCU_CKOUTSRC_LXTAL: LXTAL selected
- \arg RCU_CKOUTSRC_CKSYS: CKSYS selected
- \arg RCU_CKOUTSRC_IRC8M: IRC8M selected
- \arg RCU_CKOUTSRC_HXTAL: HXTAL selected
- \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
- \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
- \param[in] ckout_div: CK_OUT divider
- \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
- \param[out] none
- \retval none
-*/
-void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
-{
- uint32_t ckout = 0U;
- ckout = RCU_CFG0;
- /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
- ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
- RCU_CFG0 = (ckout | ckout_src | ckout_div);
-}
-#elif defined (GD32F170_190)
-/*!
- \brief configure the CK_OUT0 clock source and divider
- \param[in] ckout0_src: CK_OUT0 clock source selection
- \arg RCU_CKOUT0SRC_NONE: no clock selected
- \arg RCU_CKOUT0SRC_IRC28M: IRC28M selected
- \arg RCU_CKOUT0SRC_IRC40K: IRC40K selected
- \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected
- \arg RCU_CKOUT0SRC_CKSYS: CKSYS selected
- \arg RCU_CKOUT0SRC_IRC8M: IRC8M selected
- \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected
- \arg RCU_CKOUT0SRC_CKPLL_DIV1: CK_PLL selected
- \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
- \param[in] ckout0_div: CK_OUT0 divider
- \arg RCU_CKOUT0_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT0 is divided by x
- \param[out] none
- \retval none
-*/
-void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div)
-{
- uint32_t ckout0 = 0U;
- ckout0 = RCU_CFG0;
- /* reset the CKOUT0SEL, CKOUT0DIV and PLLDV bits and set according to ckout0_src and ckout0_div */
- ckout0 &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
- RCU_CFG0 = (ckout0 | ckout0_src | ckout0_div);
-}
-
-/*!
- \brief configure the CK_OUT1 clock source and divider
- \param[in] ckout1_src: CK_OUT1 clock source selection
- \arg RCU_CKOUT1SRC_NONE: no clock selected
- \arg RCU_CKOUT1SRC_IRC28M: IRC28M selected
- \arg RCU_CKOUT1SRC_IRC40K: IRC40K selected
- \arg RCU_CKOUT1SRC_LXTAL: LXTAL selected
- \arg RCU_CKOUT1SRC_CKSYS: CKSYS selected
- \arg RCU_CKOUT1SRC_IRC8M: IRC8M selected
- \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected
- \arg RCU_CKOUT1SRC_CKPLL_DIV1: CK_PLL selected
- \arg RCU_CKOUT1SRC_CKPLL_DIV2: CK_PLL/2 selected
- \param[in] ckout1_div: CK_OUT1 divider
- \arg RCU_CKOUT1_DIVx(x=1..64): CK_OUT1 is divided by x
- \param[out] none
- \retval none
-*/
-void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div)
-{
- uint32_t ckout1 = 0U;
- ckout1 = RCU_CFG3;
- /* reset the CKOUT1SRC, CKOUT1DIV bits and set according to ckout1_src and ckout1_div */
- ckout1 &= ~(RCU_CFG3_CKOUT1SRC | RCU_CFG3_CKOUT1DIV);
- if(RCU_CKOUT1SRC_CKPLL_DIV1 == ckout1_src){
- RCU_CFG0 |= RCU_CFG0_PLLDV;
- ckout1_src = CFG3_CKOUT1SRC(7);
- }else if(RCU_CKOUT1SRC_CKPLL_DIV2 == ckout1_src){
- RCU_CFG0 &= ~RCU_CFG0_PLLDV;
- ckout1_src = CFG3_CKOUT1SRC(7);
- }else{
- }
- RCU_CFG3 = (ckout1 | ckout1_src | ckout1_div);
-}
-#endif /* GD32F130_150 */
-
-/*!
- \brief configure the PLL clock source selection and PLL multiply factor
- \param[in] pll_src: PLL clock source selection
- \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
- \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock
- \param[in] pll_mul: PLL multiply factor
- \arg RCU_PLL_MULx(x=2..32): PLL source clock * x
- \param[out] none
- \retval none
-*/
-void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
-{
- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
- RCU_CFG0 |= (pll_src | pll_mul);
-}
-
-/*!
- \brief configure the USART clock source selection
- \param[in] ck_usart: USART clock source selection
- \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2
- \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS
- \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL
- \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M
- \param[out] none
- \retval none
-*/
-void rcu_usart_clock_config(uint32_t ck_usart)
-{
- /* reset the USART0SEL bits and set according to ck_usart */
- RCU_CFG2 &= ~RCU_CFG2_USART0SEL;
- RCU_CFG2 |= ck_usart;
-}
-
-/*!
- \brief configure the CEC clock source selection
- \param[in] ck_cec: CEC clock source selection
- \arg RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244
- \arg RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL
- \param[out] none
- \retval none
-*/
-void rcu_cec_clock_config(uint32_t ck_cec)
-{
- /* reset the CECSEL bit and set according to ck_cec */
- RCU_CFG2 &= ~RCU_CFG2_CECSEL;
- RCU_CFG2 |= ck_cec;
-}
-
-/*!
- \brief configure the RTC clock source selection
- \param[in] rtc_clock_source: RTC clock source selection
- \arg RCU_RTCSRC_NONE: no clock selected
- \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
- \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
- \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock
- \param[out] none
- \retval none
-*/
-void rcu_rtc_clock_config(uint32_t rtc_clock_source)
-{
- /* reset the RTCSRC bits and set according to rtc_clock_source */
- RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
- RCU_BDCTL |= rtc_clock_source;
-}
-
-#ifdef GD32F170_190
-/*!
- \brief configure the SLCD clock source selection
- \param[in] slcd_clock_source: SLCD clock source selection
- \arg RCU_SLCDSRC_NONE: no clock selected
- \arg RCU_SLCDSRC_LXTAL: CK_LXTAL selected as SLCD source clock
- \arg RCU_SLCDSRC_IRC40K: CK_IRC40K selected as SLCD source clock
- \arg RCU_SLCDSRC_HXTAL_DIV32: CK_HXTAL/32 selected as SLCD source clock
- \param[out] none
- \retval none
-*/
-void rcu_slcd_clock_config(uint32_t slcd_clock_source)
-{
- /* reset the bits and set according to rtc_clock_source */
- RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
- RCU_BDCTL |= slcd_clock_source;
-}
-#endif /* GD32F170_190 */
-
-/*!
- \brief configure the HXTAL divider used as input of PLL
- \param[in] hxtal_prediv: HXTAL divider used as input of PLL
- \arg RCU_PLL_HXTAL_DIVx(x=1..16): HXTAL divided x used as input of PLL
- \param[out] none
- \retval none
-*/
-void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
-{
- uint32_t prediv = 0U;
- prediv = RCU_CFG1;
- /* reset the HXTALPREDV bits and set according to hxtal_prediv */
- prediv &= ~RCU_CFG1_HXTALPREDV;
- RCU_CFG1 = (prediv | hxtal_prediv);
-}
-
-/*!
- \brief configure the LXTAL drive capability
- \param[in] lxtal_dricap: drive capability of LXTAL
- \arg RCU_LXTAL_LOWDRI: lower driving capability
- \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability
- \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability
- \arg RCU_LXTAL_HIGHDRI: higher driving capability
- \param[out] none
- \retval none
-*/
-void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
-{
- /* reset the LXTALDRI bits and set according to lxtal_dricap */
- RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI;
- RCU_BDCTL |= lxtal_dricap;
-}
-
-/*!
- \brief get the clock stabilization and periphral reset flags
- \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
- \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
- \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
- \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
- \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
- \arg RCU_FLAG_PLLSTB: PLL stabilization flag
- \arg RCU_FLAG_IRC14MSTB: IRC14M stabilization flag, only in GD32F130_150
- \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag, only in GD32F170_190
- \arg RCU_FLAG_V12RST: V12 domain Power reset flag
- \arg RCU_FLAG_OBLRST: Option byte loader reset flag
- \arg RCU_FLAG_EPRST: External PIN reset flag
- \arg RCU_FLAG_PORRST: Power reset flag
- \arg RCU_FLAG_SWRST: Software reset flag
- \arg RCU_FLAG_FWDGTRST: Free watchdog timer reset flag
- \arg RCU_FLAG_WWDGTRST: Window watchdog timer reset flag
- \arg RCU_FLAG_LPRST: Low-power reset flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus rcu_flag_get(rcu_flag_enum flag)
-{
- if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear the reset flag
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_all_reset_flag_clear(void)
-{
- RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
-}
-
-/*!
- \brief get the clock stabilization interrupt and ckm flags
- \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
- \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
- \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
- \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
- \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
- \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
- \arg RCU_INT_FLAG_IRC14MSTB: IRC14M stabilization interrupt flag, only in GD32F130_150
- \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag, only in GD32F170_190
- \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
-{
- if(RESET != (RCU_INT & int_flag)){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear the interrupt flags
- \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
- \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
- \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
- \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
- \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
- \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
- \arg RCU_INT_FLAG_IRC14MSTB_CLR: IRC14M stabilization interrupt flag clear, only in GD32F130_150
- \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear, only in GD32F170_190
- \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
- \param[out] none
- \retval none
-*/
-void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
-{
- RCU_INT |= (uint32_t)int_flag_clear;
-}
-
-/*!
- \brief enable the stabilization interrupt
- \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
- \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
- \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
- \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
- \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
- \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
- \arg RCU_INT_IRC14MSTB: IRC14M stabilization interrupt enable, only in GD32F130_150
- \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable, only in GD32F170_190
- \param[out] none
- \retval none
-*/
-void rcu_interrupt_enable(rcu_int_enum stab_int)
-{
- RCU_INT |= (uint32_t)stab_int;
-}
-
-
-/*!
- \brief disable the stabilization interrupt
- \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
- \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable
- \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
- \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable
- \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
- \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable
- \arg RCU_INT_IRC14MSTB: IRC14M stabilization interrupt disable, only in GD32F130_150
- \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable, only in GD32F170_190
- \param[out] none
- \retval none
-*/
-void rcu_interrupt_disable(rcu_int_enum stab_int)
-{
- RCU_INT &= ~(uint32_t)stab_int;
-}
-
-/*!
- \brief wait until oscillator stabilization flags is SET or oscillator startup is timeout
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- \arg RCU_HXTAL: HXTAL
- \arg RCU_LXTAL: LXTAL
- \arg RCU_IRC8M: IRC8M
- \arg RCU_IRC14M: IRC14M, only in GD32F130_150
- \arg RCU_IRC28M: IRC28M, only in GD32F170_190
- \arg RCU_IRC40K: IRC40K
- \arg RCU_PLL_CK: PLL
- \param[out] none
- \retval ErrStatus: SUCCESS or ERROR
-*/
-ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
-{
- uint32_t stb_cnt = 0U;
- ErrStatus reval = ERROR;
- FlagStatus osci_stat = RESET;
-
- switch(osci){
- /* wait HXTAL stable */
- case RCU_HXTAL:
- while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
- reval = SUCCESS;
- }
- break;
- /* wait LXTAL stable */
- case RCU_LXTAL:
- while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
- reval = SUCCESS;
- }
- break;
- /* wait IRC8M stable */
- case RCU_IRC8M:
- while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
- reval = SUCCESS;
- }
- break;
-#ifdef GD32F130_150
- /* wait IRC14M stable */
- case RCU_IRC14M:
- while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_IRC14MSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_IRC14MSTB)){
- reval = SUCCESS;
- }
- break;
-#elif defined (GD32F170_190)
- /* wait IRC28M stable */
- case RCU_IRC28M:
- while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){
- reval = SUCCESS;
- }
- break;
-#endif /* GD32F130_150 */
- /* wait IRC40K stable */
- case RCU_IRC40K:
- while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
- reval = SUCCESS;
- }
- break;
- /* wait PLL stable */
- case RCU_PLL_CK:
- while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
- osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
- stb_cnt++;
- }
-
- /* check whether flag is set or not */
- if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
- reval = SUCCESS;
- }
- break;
- default:
- break;
- }
-
- /* return value */
- return reval;
-}
-
-/*!
- \brief turn on the oscillator
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- \arg RCU_HXTAL: HXTAL
- \arg RCU_LXTAL: LXTAL
- \arg RCU_IRC8M: IRC8M
- \arg RCU_IRC14M: IRC14M, only in GD32F130_150
- \arg RCU_IRC28M: IRC28M, only in GD32F170_190
- \arg RCU_IRC40K: IRC40K
- \arg RCU_PLL_CK: PLL
- \param[out] none
- \retval none
-*/
-void rcu_osci_on(rcu_osci_type_enum osci)
-{
- RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
-}
-
-/*!
- \brief turn off the oscillator
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- \arg RCU_HXTAL: HXTAL
- \arg RCU_LXTAL: LXTAL
- \arg RCU_IRC8M: IRC8M
- \arg RCU_IRC14M: IRC14M, only in GD32F130_150
- \arg RCU_IRC28M: IRC28M, only in GD32F170_190
- \arg RCU_IRC40K: IRC40K
- \arg RCU_PLL_CK: PLL
- \param[out] none
- \retval none
-*/
-void rcu_osci_off(rcu_osci_type_enum osci)
-{
- RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
-}
-
-/*!
- \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- \arg RCU_HXTAL: HXTAL
- \arg RCU_LXTAL: LXTAL
- \param[out] none
- \retval none
-*/
-void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
-{
- uint32_t reg;
- switch(osci){
- case RCU_HXTAL:
- /* HXTALEN must be reset before enable the oscillator bypass mode */
- reg = RCU_CTL0;
- RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
- RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS);
- break;
- case RCU_LXTAL:
- /* LXTALEN must be reset before enable the oscillator bypass mode */
- reg = RCU_BDCTL;
- RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
- RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
- break;
- case RCU_IRC8M:
-#ifdef GD32F130_150
- case RCU_IRC14M:
-#elif defined (GD32F170_190)
- case RCU_IRC28M:
-#endif /* GD32F130_150 */
- case RCU_IRC40K:
- case RCU_PLL_CK:
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
- \param[in] osci: oscillator types, refer to rcu_osci_type_enum
- \arg RCU_HXTAL: HXTAL
- \arg RCU_LXTAL: LXTAL
- \param[out] none
- \retval none
-*/
-void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
-{
- uint32_t reg;
- switch(osci){
- case RCU_HXTAL:
- /* HXTALEN must be reset before disable the oscillator bypass mode */
- reg = RCU_CTL0;
- RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
- RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS));
- break;
- case RCU_LXTAL:
- /* LXTALEN must be reset before disable the oscillator bypass mode */
- reg = RCU_BDCTL;
- RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
- RCU_BDCTL =(reg & (~RCU_BDCTL_LXTALBPS));
- break;
- case RCU_IRC8M:
-#ifdef GD32F130_150
- case RCU_IRC14M:
-#elif defined (GD32F170_190)
- case RCU_IRC28M:
-#endif /* GD32F130_150 */
- case RCU_IRC40K:
- case RCU_PLL_CK:
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief enable the HXTAL clock monitor
- \param[in] none
- \param[out] none
- \retval none
-*/
-
-void rcu_hxtal_clock_monitor_enable(void)
-{
- RCU_CTL0 |= RCU_CTL0_CKMEN;
-}
-
-/*!
- \brief disable the HXTAL clock monitor
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_hxtal_clock_monitor_disable(void)
-{
- RCU_CTL0 &= ~RCU_CTL0_CKMEN;
-}
-
-/*!
- \brief set the IRC8M adjust value
- \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
- \param[out] none
- \retval none
-*/
-void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
-{
- uint32_t adjust = 0U;
- adjust = RCU_CTL0;
- /* reset the IRC8MADJ bits and set according to irc8m_adjval */
- adjust &= ~RCU_CTL0_IRC8MADJ;
- RCU_CTL0 = (adjust | ((uint32_t)(irc8m_adjval)<<3));
-}
-
-#ifdef GD32F130_150
-/*!
- \brief set the IRC14M adjust value
- \param[in] irc14m_adjval: IRC14M adjust value, must be between 0 and 0x1F
- \param[out] none
- \retval none
-*/
-void rcu_irc14m_adjust_value_set(uint8_t irc14m_adjval)
-{
- uint32_t adjust = 0U;
- adjust = RCU_CTL1;
- /* reset the IRC14MADJ bits and set according to irc14m_adjval */
- adjust &= ~RCU_CTL1_IRC14MADJ;
- RCU_CTL1 = (adjust | ((uint32_t)(irc14m_adjval)<<3));
-}
-#elif defined (GD32F170_190)
-/*!
- \brief set the IRC28M adjust value
- \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F
- \param[out] none
- \retval none
-*/
-void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
-{
- uint32_t adjust = 0U;
- adjust = RCU_CTL1;
- /* reset the IRC28MADJ bits and set according to irc28m_adjval */
- adjust &= ~RCU_CTL1_IRC28MADJ;
- RCU_CTL1 = (adjust | ((uint32_t)(irc28m_adjval)<<3));
-}
-#endif /* GD32F130_150 */
-
-/*!
- \brief unlock the voltage key
- \param[in] none
- \param[out] none
- \retval none
-*/
-void rcu_voltage_key_unlock(void)
-{
- /* reset the KEY bits and set 0x1A2B3C4D */
- RCU_VKEY &= ~RCU_VKEY_KEY;
- RCU_VKEY |= RCU_VKEY_UNLOCK;
-}
-
-/*!
- \brief set voltage in deep sleep mode
- \param[in] dsvol: deep sleep mode voltage
- \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V, only in GD32F130_150
- \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V, only in GD32F130_150
- \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V, only in GD32F130_150
- \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V, only in GD32F130_150
-
- \arg RCU_DEEPSLEEP_V_1_8: the core voltage is 1.8V, only in GD32F170_190
- \arg RCU_DEEPSLEEP_V_1_6: the core voltage is 1.6V, only in GD32F170_190
- \arg RCU_DEEPSLEEP_V_1_4: the core voltage is 1.4V, only in GD32F170_190
- \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V, only in GD32F170_190
- \param[out] none
- \retval none
-*/
-void rcu_deepsleep_voltage_set(uint32_t dsvol)
-{
- /* reset the DSLPVS bits and set according to dsvol */
- RCU_DSV &= ~RCU_DSV_DSLPVS;
- RCU_DSV |= dsvol;
-}
-
-#ifdef GD32F130_150
-/*!
- \brief set the power down voltage
- \param[in] pdvol: power down voltage select
- \arg RCU_PDR_V_2_6: power down voltage is 2.6V
- \arg RCU_PDR_V_1_8: power down voltage is 1.8V
- \param[out] none
- \retval none
-*/
-void rcu_power_down_voltage_set(uint32_t pdvol)
-{
- /* reset the PDRVS bits and set according to pdvol */
- RCU_PDVSEL &= ~RCU_PDVSEL_PDRVS;
- RCU_PDVSEL |= pdvol;
-}
-#endif /* GD32F130_150 */
-
-/*!
- \brief get the system clock, bus and peripheral clock frequency
- \param[in] clock: the clock frequency which to get
- \arg CK_SYS: system clock frequency
- \arg CK_AHB: AHB clock frequency
- \arg CK_APB1: APB1 clock frequency
- \arg CK_APB2: APB2 clock frequency
- \arg CK_ADC: ADC clock frequency
- \arg CK_CEC: CEC clock frequency
- \arg CK_USART: USART clock frequency
- \param[out] none
- \retval clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT
-*/
-uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
-{
- uint32_t sws = 0U, adcps = 0U, ck_freq = 0U;
- uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
- uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U;
- uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
- /* exponent of AHB, APB1 and APB2 clock divider */
- const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
- const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
- const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
- sws = GET_BITS(RCU_CFG0, 2, 3);
- switch(sws){
- /* IRC8M is selected as CK_SYS */
- case SEL_IRC8M:
- cksys_freq = IRC8M_VALUE;
- break;
- /* HXTAL is selected as CK_SYS */
- case SEL_HXTAL:
- cksys_freq = HXTAL_VALUE;
- break;
- /* PLL is selected as CK_SYS */
- case SEL_PLL:
- /* get the value of PLLMF[3:0] */
- pllmf = GET_BITS(RCU_CFG0, 18, 21);
- pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
- /* high 16 bits */
- if(1U == pllmf4){
- pllmf += 17U;
- }else{
- pllmf += 2U;
- }
- /* PLL clock source selection, HXTAL or IRC8M/2 */
- pllsel = GET_BITS(RCU_CFG0, 16, 16);
- if(0U != pllsel){
- prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U);
- cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
- }else{
- cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
- }
- break;
- /* IRC8M is selected as CK_SYS */
- default:
- cksys_freq = IRC8M_VALUE;
- break;
- }
- /* calculate AHB clock frequency */
- idx = GET_BITS(RCU_CFG0, 4, 7);
- clk_exp = ahb_exp[idx];
- ahb_freq = cksys_freq >> clk_exp;
-
- /* calculate APB1 clock frequency */
- idx = GET_BITS(RCU_CFG0, 8, 10);
- clk_exp = apb1_exp[idx];
- apb1_freq = ahb_freq >> clk_exp;
-
- /* calculate APB2 clock frequency */
- idx = GET_BITS(RCU_CFG0, 11, 13);
- clk_exp = apb2_exp[idx];
- apb2_freq = ahb_freq >> clk_exp;
-
- /* return the clocks frequency */
- switch(clock){
- case CK_SYS:
- ck_freq = cksys_freq;
- break;
- case CK_AHB:
- ck_freq = ahb_freq;
- break;
- case CK_APB1:
- ck_freq = apb1_freq;
- break;
- case CK_APB2:
- ck_freq = apb2_freq;
- break;
- case CK_ADC:
- /* calculate ADC clock frequency */
- if(RCU_ADCSRC_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
-#ifdef GD32F130_150
- adc_freq = IRC14M_VALUE;
-#elif defined (GD32F170_190)
- if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
- adc_freq = IRC28M_VALUE >> 1;
- }else{
- adc_freq = IRC28M_VALUE;
- }
-#endif /* GD32F130_150 */
- }else{
- /* ADC clock select CK_APB2 divided by 2/4/6/8 */
- adcps = GET_BITS(RCU_CFG0, 14, 15);
- switch(adcps){
- case 0:
- adc_freq = apb2_freq / 2U;
- break;
- case 1:
- adc_freq = apb2_freq / 4U;
- break;
- case 2:
- adc_freq = apb2_freq / 6U;
- break;
- case 3:
- adc_freq = apb2_freq / 8U;
- break;
- default:
- break;
- }
- }
- ck_freq = adc_freq;
- break;
- case CK_CEC:
- /* calculate CEC clock frequency */
- if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){
- cec_freq = IRC8M_VALUE / 244U;
- }else{
- cec_freq = LXTAL_VALUE;
- }
- ck_freq = cec_freq;
- break;
- case CK_USART:
- /* calculate USART clock frequency */
- if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
- usart_freq = apb2_freq;
- }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
- usart_freq = cksys_freq;
- }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
- usart_freq = LXTAL_VALUE;
- }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
- usart_freq = IRC8M_VALUE;
- }else{
- }
- ck_freq = usart_freq;
- break;
- default:
- break;
- }
- return ck_freq;
-}
+/*!
+ \file gd32f1x0_rcu.c
+ \brief RCU driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_rcu.h"
+
+#define SEL_IRC8M 0x00U
+#define SEL_HXTAL 0x01U
+#define SEL_PLL 0x02U
+
+/* define startup timeout count */
+#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU)
+#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU)
+
+/*!
+ \brief deinitialize the RCU
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_deinit(void)
+{
+ /* enable IRC8M */
+ RCU_CTL0 |= RCU_CTL0_IRC8MEN;
+ while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
+ }
+ /* reset RCU */
+#ifdef GD32F130_150
+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+ RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+#elif defined (GD32F170_190)
+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+ RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
+#endif /* GD32F130_150 */
+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
+#ifdef GD32F130_150
+ RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
+#endif /* GD32F130_150 */
+ RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
+ RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
+ RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
+#ifdef GD32F130_150
+ RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
+#elif defined (GD32F170_190)
+ RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+ RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
+ RCU_CFG3 &= ~RCU_CFG3_CKOUT1SRC;
+ RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
+#endif /* GD32F130_150 */
+ RCU_INT = 0x00000000U;
+}
+
+/*!
+ \brief enable the peripherals clock
+ \param[in] periph: RCU peripherals, refer to rcu_periph_enum
+ \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
+ \arg RCU_DMA: DMA clock
+ \arg RCU_CRC: CRC clock
+ \arg RCU_TSI: TSI clock
+ \arg RCU_CFGCMP: CFGCMP clock
+ \arg RCU_ADC: ADC clock
+ \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock
+ \arg RCU_SPIx (x=0,1,2): SPI clock
+ \arg RCU_USARTx (x=0,1): USART clock
+ \arg RCU_SLCD: SLCD clock, only in GD32F170_190
+ \arg RCU_WWDGT: WWDGT clock
+ \arg RCU_I2Cx (x=0,1,2): I2C clock
+ \arg RCU_USBD: USBD clock, only in GD32F130_150
+ \arg RCU_CANx (x=0,1): CAN clock, only in GD32F170_190
+ \arg RCU_PMU: PMU clock
+ \arg RCU_DAC: DAC clock
+ \arg RCU_CEC: CEC clock
+ \arg RCU_OPAIVREF: OPAIVREF clock, only in GD32F170_190
+ \arg RCU_RTC: RTC clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_enable(rcu_periph_enum periph)
+{
+ RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief disable the peripherals clock
+ \param[in] periph: RCU peripherals, refer to rcu_periph_enum
+ \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock
+ \arg RCU_DMA: DMA clock
+ \arg RCU_CRC: CRC clock
+ \arg RCU_TSI: TSI clock
+ \arg RCU_CFGCMP: CFGCMP clock
+ \arg RCU_ADC: ADC clock
+ \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock
+ \arg RCU_SPIx (x=0,1,2): SPI clock
+ \arg RCU_USARTx (x=0,1): USART clock
+ \arg RCU_SLCD: SLCD clock, only in GD32F170_190
+ \arg RCU_WWDGT: WWDGT clock
+ \arg RCU_I2Cx (x=0,1,2): I2C clock
+ \arg RCU_USBD: USBD clock only in GD32F130_150
+ \arg RCU_CANx (x=0,1): CAN clock, only in GD32F170_190
+ \arg RCU_PMU: PMU clock
+ \arg RCU_DAC: DAC clock
+ \arg RCU_CEC: CEC clock
+ \arg RCU_OPAIVREF: OPAIVREF clock, only in GD32F170_190
+ \arg RCU_RTC: RTC clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_disable(rcu_periph_enum periph)
+{
+ RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief enable the peripherals clock when sleep mode
+ \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_FMC_SLP: FMC clock
+ \arg RCU_SRAM_SLP: SRAM clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
+{
+ RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief disable the peripherals clock when sleep mode
+ \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum
+ only one parameter can be selected which is shown as below:
+ \arg RCU_FMC_SLP: FMC clock
+ \arg RCU_SRAM_SLP: SRAM clock
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
+{
+ RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
+}
+
+/*!
+ \brief reset the peripherals
+ \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+ \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
+ \arg RCU_TSIRST: reset TSI
+ \arg RCU_CFGCMPRST: reset CFGCMP
+ \arg RCU_ADCRST: reset ADC
+ \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER
+ \arg RCU_SPIxRST (x=0,1,2): reset SPI
+ \arg RCU_USARTxRST (x=0,1): reset USART
+ \arg RCU_SLCDRST: reset SLCD, only in GD32F170_190
+ \arg RCU_WWDGTRST: reset WWDGT
+ \arg RCU_I2CxRST (x=0,1,2): reset I2C
+ \arg RCU_USBDRST: reset USBD, only in GD32F130_150
+ \arg RCU_CANxRST (x=0,1): reset CAN, only in GD32F170_190
+ \arg RCU_PMURST: reset PMU
+ \arg RCU_DACRST: reset DAC
+ \arg RCU_CECRST: reset CEC
+ \arg RCU_OPAIVREFRST: reset OPAIVREF, only in GD32F170_190
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
+{
+ RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+ \brief disable reset the peripheral
+ \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum
+ \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports
+ \arg RCU_TSIRST: reset TSI
+ \arg RCU_CFGCMPRST: reset CFGCMP
+ \arg RCU_ADCRST: reset ADC
+ \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER
+ \arg RCU_SPIxRST (x=0,1,2): reset SPI
+ \arg RCU_USARTxRST (x=0,1): reset USART
+ \arg RCU_SLCDRST: reset SLCD, only in GD32F170_190
+ \arg RCU_WWDGTRST: reset WWDGT
+ \arg RCU_I2CxRST (x=0,1,2): reset I2C
+ \arg RCU_USBDRST: reset USBD, only in GD32F130_150
+ \arg RCU_CANxRST (x=0,1): reset CAN, only in GD32F170_190
+ \arg RCU_PMURST: reset PMU
+ \arg RCU_DACRST: reset DAC
+ \arg RCU_CECRST: reset CEC
+ \arg RCU_OPAIVREFRST: reset OPAIVREF, only in GD32F170_190
+ \param[out] none
+ \retval none
+*/
+void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
+{
+ RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
+}
+
+/*!
+ \brief reset the BKP domain
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_bkp_reset_enable(void)
+{
+ RCU_BDCTL |= RCU_BDCTL_BKPRST;
+}
+
+/*!
+ \brief disable the BKP domain reset
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_bkp_reset_disable(void)
+{
+ RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
+}
+
+/*!
+ \brief configure the system clock source
+ \param[in] ck_sys: system clock source select
+ \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source
+ \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source
+ \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source
+ \param[out] none
+ \retval none
+*/
+void rcu_system_clock_source_config(uint32_t ck_sys)
+{
+ uint32_t cksys_source = 0U;
+ cksys_source = RCU_CFG0;
+ /* reset the SCS bits and set according to ck_sys */
+ cksys_source &= ~RCU_CFG0_SCS;
+ RCU_CFG0 = (ck_sys | cksys_source);
+}
+
+/*!
+ \brief get the system clock source
+ \param[in] none
+ \param[out] none
+ \retval which clock is selected as CK_SYS source
+ \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source
+ \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source
+ \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source
+*/
+uint32_t rcu_system_clock_source_get(void)
+{
+ return (RCU_CFG0 & 0x0000000CU);
+}
+
+/*!
+ \brief configure the AHB clock prescaler selection
+ \param[in] ck_ahb: AHB clock prescaler selection
+ \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
+ \param[out] none
+ \retval none
+*/
+void rcu_ahb_clock_config(uint32_t ck_ahb)
+{
+ uint32_t ahbpsc = 0U;
+ ahbpsc = RCU_CFG0;
+ /* reset the AHBPSC bits and set according to ck_ahb */
+ ahbpsc &= ~RCU_CFG0_AHBPSC;
+ RCU_CFG0 = (ck_ahb | ahbpsc);
+}
+
+/*!
+ \brief configure the APB1 clock prescaler selection
+ \param[in] ck_apb1: APB1 clock prescaler selection
+ \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1
+ \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1
+ \param[out] none
+ \retval none
+*/
+void rcu_apb1_clock_config(uint32_t ck_apb1)
+{
+ uint32_t apb1psc = 0U;
+ apb1psc = RCU_CFG0;
+ /* reset the APB1PSC and set according to ck_apb1 */
+ apb1psc &= ~RCU_CFG0_APB1PSC;
+ RCU_CFG0 = (ck_apb1 | apb1psc);
+}
+
+/*!
+ \brief configure the APB2 clock prescaler selection
+ \param[in] ck_apb2: APB2 clock prescaler selection
+ \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2
+ \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2
+ \param[out] none
+ \retval none
+*/
+void rcu_apb2_clock_config(uint32_t ck_apb2)
+{
+ uint32_t apb2psc = 0U;
+ apb2psc = RCU_CFG0;
+ /* reset the APB2PSC and set according to ck_apb2 */
+ apb2psc &= ~RCU_CFG0_APB2PSC;
+ RCU_CFG0 = (ck_apb2 | apb2psc);
+}
+
+/*!
+ \brief configure the ADC clock prescaler selection
+ \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum
+ \arg RCU_ADCCK_IRC14M: select CK_IRC14M as CK_ADC, only in GD32F130_150
+ \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC, only in GD32F170_190
+ \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC, only in GD32F170_190
+ \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC
+ \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC
+ \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC
+ \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC
+ \param[out] none
+ \retval none
+*/
+void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc)
+{
+ /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */
+ RCU_CFG0 &= ~RCU_CFG0_ADCPSC;
+#ifdef GD32F130_150
+ RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
+#elif defined (GD32F170_190)
+ RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV);
+#endif /* GD32F130_150 */
+ /* set the ADC clock according to ck_adc */
+ switch(ck_adc){
+#ifdef GD32F130_150
+ case RCU_ADCCK_IRC14M:
+ RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
+ break;
+#elif defined (GD32F170_190)
+ case RCU_ADCCK_IRC28M_DIV2:
+ RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+ RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
+ break;
+ case RCU_ADCCK_IRC28M:
+ RCU_CFG2 |= RCU_CFG2_IRC28MDIV;
+ RCU_CFG2 &= ~RCU_CFG2_ADCSEL;
+ break;
+#endif /* GD32F130_150 */
+ case RCU_ADCCK_APB2_DIV2:
+ RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2;
+ RCU_CFG2 |= RCU_CFG2_ADCSEL;
+ break;
+ case RCU_ADCCK_APB2_DIV4:
+ RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4;
+ RCU_CFG2 |= RCU_CFG2_ADCSEL;
+ break;
+ case RCU_ADCCK_APB2_DIV6:
+ RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6;
+ RCU_CFG2 |= RCU_CFG2_ADCSEL;
+ break;
+ case RCU_ADCCK_APB2_DIV8:
+ RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8;
+ RCU_CFG2 |= RCU_CFG2_ADCSEL;
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef GD32F130_150
+/*!
+ \brief configure the USBD clock prescaler selection
+ \param[in] ck_usbd: USBD clock prescaler selection
+ \arg RCU_USBD_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBD
+ \arg RCU_USBD_CKPLL_DIV1: select CK_PLL as CK_USBD
+ \arg RCU_USBD_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBD
+ \arg RCU_USBD_CKPLL_DIV2: select CK_PLL/2 as CK_USBD
+ \param[out] none
+ \retval none
+*/
+void rcu_usbd_clock_config(uint32_t ck_usbd)
+{
+ /* reset the USBDPSC bits and set according to ck_usbd */
+ RCU_CFG0 &= ~RCU_CFG0_USBDPSC;
+ RCU_CFG0 |= ck_usbd;
+}
+
+/*!
+ \brief configure the CK_OUT clock source and divider
+ \param[in] ckout_src: CK_OUT clock source selection
+ \arg RCU_CKOUTSRC_NONE: no clock selected
+ \arg RCU_CKOUTSRC_IRC14M: IRC14M selected
+ \arg RCU_CKOUTSRC_IRC40K: IRC40K selected
+ \arg RCU_CKOUTSRC_LXTAL: LXTAL selected
+ \arg RCU_CKOUTSRC_CKSYS: CKSYS selected
+ \arg RCU_CKOUTSRC_IRC8M: IRC8M selected
+ \arg RCU_CKOUTSRC_HXTAL: HXTAL selected
+ \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected
+ \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected
+ \param[in] ckout_div: CK_OUT divider
+ \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x
+ \param[out] none
+ \retval none
+*/
+void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div)
+{
+ uint32_t ckout = 0U;
+ ckout = RCU_CFG0;
+ /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */
+ ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+ RCU_CFG0 = (ckout | ckout_src | ckout_div);
+}
+#elif defined (GD32F170_190)
+/*!
+ \brief configure the CK_OUT0 clock source and divider
+ \param[in] ckout0_src: CK_OUT0 clock source selection
+ \arg RCU_CKOUT0SRC_NONE: no clock selected
+ \arg RCU_CKOUT0SRC_IRC28M: IRC28M selected
+ \arg RCU_CKOUT0SRC_IRC40K: IRC40K selected
+ \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected
+ \arg RCU_CKOUT0SRC_CKSYS: CKSYS selected
+ \arg RCU_CKOUT0SRC_IRC8M: IRC8M selected
+ \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected
+ \arg RCU_CKOUT0SRC_CKPLL_DIV1: CK_PLL selected
+ \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected
+ \param[in] ckout0_div: CK_OUT0 divider
+ \arg RCU_CKOUT0_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT0 is divided by x
+ \param[out] none
+ \retval none
+*/
+void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div)
+{
+ uint32_t ckout0 = 0U;
+ ckout0 = RCU_CFG0;
+ /* reset the CKOUT0SEL, CKOUT0DIV and PLLDV bits and set according to ckout0_src and ckout0_div */
+ ckout0 &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
+ RCU_CFG0 = (ckout0 | ckout0_src | ckout0_div);
+}
+
+/*!
+ \brief configure the CK_OUT1 clock source and divider
+ \param[in] ckout1_src: CK_OUT1 clock source selection
+ \arg RCU_CKOUT1SRC_NONE: no clock selected
+ \arg RCU_CKOUT1SRC_IRC28M: IRC28M selected
+ \arg RCU_CKOUT1SRC_IRC40K: IRC40K selected
+ \arg RCU_CKOUT1SRC_LXTAL: LXTAL selected
+ \arg RCU_CKOUT1SRC_CKSYS: CKSYS selected
+ \arg RCU_CKOUT1SRC_IRC8M: IRC8M selected
+ \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected
+ \arg RCU_CKOUT1SRC_CKPLL_DIV1: CK_PLL selected
+ \arg RCU_CKOUT1SRC_CKPLL_DIV2: CK_PLL/2 selected
+ \param[in] ckout1_div: CK_OUT1 divider
+ \arg RCU_CKOUT1_DIVx(x=1..64): CK_OUT1 is divided by x
+ \param[out] none
+ \retval none
+*/
+void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div)
+{
+ uint32_t ckout1 = 0U;
+ ckout1 = RCU_CFG3;
+ /* reset the CKOUT1SRC, CKOUT1DIV bits and set according to ckout1_src and ckout1_div */
+ ckout1 &= ~(RCU_CFG3_CKOUT1SRC | RCU_CFG3_CKOUT1DIV);
+ if(RCU_CKOUT1SRC_CKPLL_DIV1 == ckout1_src){
+ RCU_CFG0 |= RCU_CFG0_PLLDV;
+ ckout1_src = CFG3_CKOUT1SRC(7);
+ }else if(RCU_CKOUT1SRC_CKPLL_DIV2 == ckout1_src){
+ RCU_CFG0 &= ~RCU_CFG0_PLLDV;
+ ckout1_src = CFG3_CKOUT1SRC(7);
+ }else{
+ }
+ RCU_CFG3 = (ckout1 | ckout1_src | ckout1_div);
+}
+#endif /* GD32F130_150 */
+
+/*!
+ \brief configure the PLL clock source selection and PLL multiply factor
+ \param[in] pll_src: PLL clock source selection
+ \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock
+ \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock
+ \param[in] pll_mul: PLL multiply factor
+ \arg RCU_PLL_MULx(x=2..32): PLL source clock * x
+ \param[out] none
+ \retval none
+*/
+void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
+{
+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+ RCU_CFG0 |= (pll_src | pll_mul);
+}
+
+/*!
+ \brief configure the USART clock source selection
+ \param[in] ck_usart: USART clock source selection
+ \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2
+ \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS
+ \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL
+ \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M
+ \param[out] none
+ \retval none
+*/
+void rcu_usart_clock_config(uint32_t ck_usart)
+{
+ /* reset the USART0SEL bits and set according to ck_usart */
+ RCU_CFG2 &= ~RCU_CFG2_USART0SEL;
+ RCU_CFG2 |= ck_usart;
+}
+
+/*!
+ \brief configure the CEC clock source selection
+ \param[in] ck_cec: CEC clock source selection
+ \arg RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244
+ \arg RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL
+ \param[out] none
+ \retval none
+*/
+void rcu_cec_clock_config(uint32_t ck_cec)
+{
+ /* reset the CECSEL bit and set according to ck_cec */
+ RCU_CFG2 &= ~RCU_CFG2_CECSEL;
+ RCU_CFG2 |= ck_cec;
+}
+
+/*!
+ \brief configure the RTC clock source selection
+ \param[in] rtc_clock_source: RTC clock source selection
+ \arg RCU_RTCSRC_NONE: no clock selected
+ \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock
+ \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock
+ \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock
+ \param[out] none
+ \retval none
+*/
+void rcu_rtc_clock_config(uint32_t rtc_clock_source)
+{
+ /* reset the RTCSRC bits and set according to rtc_clock_source */
+ RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
+ RCU_BDCTL |= rtc_clock_source;
+}
+
+#ifdef GD32F170_190
+/*!
+ \brief configure the SLCD clock source selection
+ \param[in] slcd_clock_source: SLCD clock source selection
+ \arg RCU_SLCDSRC_NONE: no clock selected
+ \arg RCU_SLCDSRC_LXTAL: CK_LXTAL selected as SLCD source clock
+ \arg RCU_SLCDSRC_IRC40K: CK_IRC40K selected as SLCD source clock
+ \arg RCU_SLCDSRC_HXTAL_DIV32: CK_HXTAL/32 selected as SLCD source clock
+ \param[out] none
+ \retval none
+*/
+void rcu_slcd_clock_config(uint32_t slcd_clock_source)
+{
+ /* reset the bits and set according to rtc_clock_source */
+ RCU_BDCTL &= ~RCU_BDCTL_RTCSRC;
+ RCU_BDCTL |= slcd_clock_source;
+}
+#endif /* GD32F170_190 */
+
+/*!
+ \brief configure the HXTAL divider used as input of PLL
+ \param[in] hxtal_prediv: HXTAL divider used as input of PLL
+ \arg RCU_PLL_HXTAL_DIVx(x=1..16): HXTAL divided x used as input of PLL
+ \param[out] none
+ \retval none
+*/
+void rcu_hxtal_prediv_config(uint32_t hxtal_prediv)
+{
+ uint32_t prediv = 0U;
+ prediv = RCU_CFG1;
+ /* reset the HXTALPREDV bits and set according to hxtal_prediv */
+ prediv &= ~RCU_CFG1_HXTALPREDV;
+ RCU_CFG1 = (prediv | hxtal_prediv);
+}
+
+/*!
+ \brief configure the LXTAL drive capability
+ \param[in] lxtal_dricap: drive capability of LXTAL
+ \arg RCU_LXTAL_LOWDRI: lower driving capability
+ \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability
+ \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability
+ \arg RCU_LXTAL_HIGHDRI: higher driving capability
+ \param[out] none
+ \retval none
+*/
+void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap)
+{
+ /* reset the LXTALDRI bits and set according to lxtal_dricap */
+ RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI;
+ RCU_BDCTL |= lxtal_dricap;
+}
+
+/*!
+ \brief get the clock stabilization and periphral reset flags
+ \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
+ \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag
+ \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
+ \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag
+ \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
+ \arg RCU_FLAG_PLLSTB: PLL stabilization flag
+ \arg RCU_FLAG_IRC14MSTB: IRC14M stabilization flag, only in GD32F130_150
+ \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag, only in GD32F170_190
+ \arg RCU_FLAG_V12RST: V12 domain Power reset flag
+ \arg RCU_FLAG_OBLRST: Option byte loader reset flag
+ \arg RCU_FLAG_EPRST: External PIN reset flag
+ \arg RCU_FLAG_PORRST: Power reset flag
+ \arg RCU_FLAG_SWRST: Software reset flag
+ \arg RCU_FLAG_FWDGTRST: Free watchdog timer reset flag
+ \arg RCU_FLAG_WWDGTRST: Window watchdog timer reset flag
+ \arg RCU_FLAG_LPRST: Low-power reset flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus rcu_flag_get(rcu_flag_enum flag)
+{
+ if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear the reset flag
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_all_reset_flag_clear(void)
+{
+ RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
+}
+
+/*!
+ \brief get the clock stabilization interrupt and ckm flags
+ \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
+ \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag
+ \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
+ \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag
+ \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
+ \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
+ \arg RCU_INT_FLAG_IRC14MSTB: IRC14M stabilization interrupt flag, only in GD32F130_150
+ \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag, only in GD32F170_190
+ \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
+{
+ if(RESET != (RCU_INT & int_flag)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear the interrupt flags
+ \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
+ \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
+ \arg RCU_INT_FLAG_IRC14MSTB_CLR: IRC14M stabilization interrupt flag clear, only in GD32F130_150
+ \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear, only in GD32F170_190
+ \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
+ \param[out] none
+ \retval none
+*/
+void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
+{
+ RCU_INT |= (uint32_t)int_flag_clear;
+}
+
+/*!
+ \brief enable the stabilization interrupt
+ \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
+ \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable
+ \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
+ \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable
+ \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
+ \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
+ \arg RCU_INT_IRC14MSTB: IRC14M stabilization interrupt enable, only in GD32F130_150
+ \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable, only in GD32F170_190
+ \param[out] none
+ \retval none
+*/
+void rcu_interrupt_enable(rcu_int_enum stab_int)
+{
+ RCU_INT |= (uint32_t)stab_int;
+}
+
+
+/*!
+ \brief disable the stabilization interrupt
+ \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum
+ \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable
+ \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
+ \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable
+ \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
+ \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable
+ \arg RCU_INT_IRC14MSTB: IRC14M stabilization interrupt disable, only in GD32F130_150
+ \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable, only in GD32F170_190
+ \param[out] none
+ \retval none
+*/
+void rcu_interrupt_disable(rcu_int_enum stab_int)
+{
+ RCU_INT &= ~(uint32_t)stab_int;
+}
+
+/*!
+ \brief wait until oscillator stabilization flags is SET or oscillator startup is timeout
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ \arg RCU_HXTAL: HXTAL
+ \arg RCU_LXTAL: LXTAL
+ \arg RCU_IRC8M: IRC8M
+ \arg RCU_IRC14M: IRC14M, only in GD32F130_150
+ \arg RCU_IRC28M: IRC28M, only in GD32F170_190
+ \arg RCU_IRC40K: IRC40K
+ \arg RCU_PLL_CK: PLL
+ \param[out] none
+ \retval ErrStatus: SUCCESS or ERROR
+*/
+ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
+{
+ uint32_t stb_cnt = 0U;
+ ErrStatus reval = ERROR;
+ FlagStatus osci_stat = RESET;
+
+ switch(osci){
+ /* wait HXTAL stable */
+ case RCU_HXTAL:
+ while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
+ reval = SUCCESS;
+ }
+ break;
+ /* wait LXTAL stable */
+ case RCU_LXTAL:
+ while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
+ reval = SUCCESS;
+ }
+ break;
+ /* wait IRC8M stable */
+ case RCU_IRC8M:
+ while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
+ reval = SUCCESS;
+ }
+ break;
+#ifdef GD32F130_150
+ /* wait IRC14M stable */
+ case RCU_IRC14M:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_IRC14MSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_IRC14MSTB)){
+ reval = SUCCESS;
+ }
+ break;
+#elif defined (GD32F170_190)
+ /* wait IRC28M stable */
+ case RCU_IRC28M:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){
+ reval = SUCCESS;
+ }
+ break;
+#endif /* GD32F130_150 */
+ /* wait IRC40K stable */
+ case RCU_IRC40K:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
+ reval = SUCCESS;
+ }
+ break;
+ /* wait PLL stable */
+ case RCU_PLL_CK:
+ while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
+ osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
+ stb_cnt++;
+ }
+
+ /* check whether flag is set or not */
+ if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
+ reval = SUCCESS;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* return value */
+ return reval;
+}
+
+/*!
+ \brief turn on the oscillator
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ \arg RCU_HXTAL: HXTAL
+ \arg RCU_LXTAL: LXTAL
+ \arg RCU_IRC8M: IRC8M
+ \arg RCU_IRC14M: IRC14M, only in GD32F130_150
+ \arg RCU_IRC28M: IRC28M, only in GD32F170_190
+ \arg RCU_IRC40K: IRC40K
+ \arg RCU_PLL_CK: PLL
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_on(rcu_osci_type_enum osci)
+{
+ RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+ \brief turn off the oscillator
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ \arg RCU_HXTAL: HXTAL
+ \arg RCU_LXTAL: LXTAL
+ \arg RCU_IRC8M: IRC8M
+ \arg RCU_IRC14M: IRC14M, only in GD32F130_150
+ \arg RCU_IRC28M: IRC28M, only in GD32F170_190
+ \arg RCU_IRC40K: IRC40K
+ \arg RCU_PLL_CK: PLL
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_off(rcu_osci_type_enum osci)
+{
+ RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
+}
+
+/*!
+ \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ \arg RCU_HXTAL: HXTAL
+ \arg RCU_LXTAL: LXTAL
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
+{
+ uint32_t reg;
+ switch(osci){
+ case RCU_HXTAL:
+ /* HXTALEN must be reset before enable the oscillator bypass mode */
+ reg = RCU_CTL0;
+ RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
+ RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS);
+ break;
+ case RCU_LXTAL:
+ /* LXTALEN must be reset before enable the oscillator bypass mode */
+ reg = RCU_BDCTL;
+ RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+ RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS);
+ break;
+ case RCU_IRC8M:
+#ifdef GD32F130_150
+ case RCU_IRC14M:
+#elif defined (GD32F170_190)
+ case RCU_IRC28M:
+#endif /* GD32F130_150 */
+ case RCU_IRC40K:
+ case RCU_PLL_CK:
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
+ \param[in] osci: oscillator types, refer to rcu_osci_type_enum
+ \arg RCU_HXTAL: HXTAL
+ \arg RCU_LXTAL: LXTAL
+ \param[out] none
+ \retval none
+*/
+void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
+{
+ uint32_t reg;
+ switch(osci){
+ case RCU_HXTAL:
+ /* HXTALEN must be reset before disable the oscillator bypass mode */
+ reg = RCU_CTL0;
+ RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
+ RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS));
+ break;
+ case RCU_LXTAL:
+ /* LXTALEN must be reset before disable the oscillator bypass mode */
+ reg = RCU_BDCTL;
+ RCU_BDCTL &= ~RCU_BDCTL_LXTALEN;
+ RCU_BDCTL =(reg & (~RCU_BDCTL_LXTALBPS));
+ break;
+ case RCU_IRC8M:
+#ifdef GD32F130_150
+ case RCU_IRC14M:
+#elif defined (GD32F170_190)
+ case RCU_IRC28M:
+#endif /* GD32F130_150 */
+ case RCU_IRC40K:
+ case RCU_PLL_CK:
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief enable the HXTAL clock monitor
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+
+void rcu_hxtal_clock_monitor_enable(void)
+{
+ RCU_CTL0 |= RCU_CTL0_CKMEN;
+}
+
+/*!
+ \brief disable the HXTAL clock monitor
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_hxtal_clock_monitor_disable(void)
+{
+ RCU_CTL0 &= ~RCU_CTL0_CKMEN;
+}
+
+/*!
+ \brief set the IRC8M adjust value
+ \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F
+ \param[out] none
+ \retval none
+*/
+void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval)
+{
+ uint32_t adjust = 0U;
+ adjust = RCU_CTL0;
+ /* reset the IRC8MADJ bits and set according to irc8m_adjval */
+ adjust &= ~RCU_CTL0_IRC8MADJ;
+ RCU_CTL0 = (adjust | ((uint32_t)(irc8m_adjval)<<3));
+}
+
+#ifdef GD32F130_150
+/*!
+ \brief set the IRC14M adjust value
+ \param[in] irc14m_adjval: IRC14M adjust value, must be between 0 and 0x1F
+ \param[out] none
+ \retval none
+*/
+void rcu_irc14m_adjust_value_set(uint8_t irc14m_adjval)
+{
+ uint32_t adjust = 0U;
+ adjust = RCU_CTL1;
+ /* reset the IRC14MADJ bits and set according to irc14m_adjval */
+ adjust &= ~RCU_CTL1_IRC14MADJ;
+ RCU_CTL1 = (adjust | ((uint32_t)(irc14m_adjval)<<3));
+}
+#elif defined (GD32F170_190)
+/*!
+ \brief set the IRC28M adjust value
+ \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F
+ \param[out] none
+ \retval none
+*/
+void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval)
+{
+ uint32_t adjust = 0U;
+ adjust = RCU_CTL1;
+ /* reset the IRC28MADJ bits and set according to irc28m_adjval */
+ adjust &= ~RCU_CTL1_IRC28MADJ;
+ RCU_CTL1 = (adjust | ((uint32_t)(irc28m_adjval)<<3));
+}
+#endif /* GD32F130_150 */
+
+/*!
+ \brief unlock the voltage key
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void rcu_voltage_key_unlock(void)
+{
+ /* reset the KEY bits and set 0x1A2B3C4D */
+ RCU_VKEY &= ~RCU_VKEY_KEY;
+ RCU_VKEY |= RCU_VKEY_UNLOCK;
+}
+
+/*!
+ \brief set voltage in deep sleep mode
+ \param[in] dsvol: deep sleep mode voltage
+ \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V, only in GD32F130_150
+ \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V, only in GD32F130_150
+ \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V, only in GD32F130_150
+ \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V, only in GD32F130_150
+
+ \arg RCU_DEEPSLEEP_V_1_8: the core voltage is 1.8V, only in GD32F170_190
+ \arg RCU_DEEPSLEEP_V_1_6: the core voltage is 1.6V, only in GD32F170_190
+ \arg RCU_DEEPSLEEP_V_1_4: the core voltage is 1.4V, only in GD32F170_190
+ \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V, only in GD32F170_190
+ \param[out] none
+ \retval none
+*/
+void rcu_deepsleep_voltage_set(uint32_t dsvol)
+{
+ /* reset the DSLPVS bits and set according to dsvol */
+ RCU_DSV &= ~RCU_DSV_DSLPVS;
+ RCU_DSV |= dsvol;
+}
+
+#ifdef GD32F130_150
+/*!
+ \brief set the power down voltage
+ \param[in] pdvol: power down voltage select
+ \arg RCU_PDR_V_2_6: power down voltage is 2.6V
+ \arg RCU_PDR_V_1_8: power down voltage is 1.8V
+ \param[out] none
+ \retval none
+*/
+void rcu_power_down_voltage_set(uint32_t pdvol)
+{
+ /* reset the PDRVS bits and set according to pdvol */
+ RCU_PDVSEL &= ~RCU_PDVSEL_PDRVS;
+ RCU_PDVSEL |= pdvol;
+}
+#endif /* GD32F130_150 */
+
+/*!
+ \brief get the system clock, bus and peripheral clock frequency
+ \param[in] clock: the clock frequency which to get
+ \arg CK_SYS: system clock frequency
+ \arg CK_AHB: AHB clock frequency
+ \arg CK_APB1: APB1 clock frequency
+ \arg CK_APB2: APB2 clock frequency
+ \arg CK_ADC: ADC clock frequency
+ \arg CK_CEC: CEC clock frequency
+ \arg CK_USART: USART clock frequency
+ \param[out] none
+ \retval clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT
+*/
+uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
+{
+ uint32_t sws = 0U, adcps = 0U, ck_freq = 0U;
+ uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U;
+ uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U;
+ uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
+ /* exponent of AHB, APB1 and APB2 clock divider */
+ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+ sws = GET_BITS(RCU_CFG0, 2, 3);
+ switch(sws){
+ /* IRC8M is selected as CK_SYS */
+ case SEL_IRC8M:
+ cksys_freq = IRC8M_VALUE;
+ break;
+ /* HXTAL is selected as CK_SYS */
+ case SEL_HXTAL:
+ cksys_freq = HXTAL_VALUE;
+ break;
+ /* PLL is selected as CK_SYS */
+ case SEL_PLL:
+ /* get the value of PLLMF[3:0] */
+ pllmf = GET_BITS(RCU_CFG0, 18, 21);
+ pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
+ /* high 16 bits */
+ if(1U == pllmf4){
+ pllmf += 17U;
+ }else{
+ pllmf += 2U;
+ }
+ /* PLL clock source selection, HXTAL or IRC8M/2 */
+ pllsel = GET_BITS(RCU_CFG0, 16, 16);
+ if(0U != pllsel){
+ prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U);
+ cksys_freq = (HXTAL_VALUE / prediv) * pllmf;
+ }else{
+ cksys_freq = (IRC8M_VALUE >> 1) * pllmf;
+ }
+ break;
+ /* IRC8M is selected as CK_SYS */
+ default:
+ cksys_freq = IRC8M_VALUE;
+ break;
+ }
+ /* calculate AHB clock frequency */
+ idx = GET_BITS(RCU_CFG0, 4, 7);
+ clk_exp = ahb_exp[idx];
+ ahb_freq = cksys_freq >> clk_exp;
+
+ /* calculate APB1 clock frequency */
+ idx = GET_BITS(RCU_CFG0, 8, 10);
+ clk_exp = apb1_exp[idx];
+ apb1_freq = ahb_freq >> clk_exp;
+
+ /* calculate APB2 clock frequency */
+ idx = GET_BITS(RCU_CFG0, 11, 13);
+ clk_exp = apb2_exp[idx];
+ apb2_freq = ahb_freq >> clk_exp;
+
+ /* return the clocks frequency */
+ switch(clock){
+ case CK_SYS:
+ ck_freq = cksys_freq;
+ break;
+ case CK_AHB:
+ ck_freq = ahb_freq;
+ break;
+ case CK_APB1:
+ ck_freq = apb1_freq;
+ break;
+ case CK_APB2:
+ ck_freq = apb2_freq;
+ break;
+ case CK_ADC:
+ /* calculate ADC clock frequency */
+ if(RCU_ADCSRC_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){
+#ifdef GD32F130_150
+ adc_freq = IRC14M_VALUE;
+#elif defined (GD32F170_190)
+ if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){
+ adc_freq = IRC28M_VALUE >> 1;
+ }else{
+ adc_freq = IRC28M_VALUE;
+ }
+#endif /* GD32F130_150 */
+ }else{
+ /* ADC clock select CK_APB2 divided by 2/4/6/8 */
+ adcps = GET_BITS(RCU_CFG0, 14, 15);
+ switch(adcps){
+ case 0:
+ adc_freq = apb2_freq / 2U;
+ break;
+ case 1:
+ adc_freq = apb2_freq / 4U;
+ break;
+ case 2:
+ adc_freq = apb2_freq / 6U;
+ break;
+ case 3:
+ adc_freq = apb2_freq / 8U;
+ break;
+ default:
+ break;
+ }
+ }
+ ck_freq = adc_freq;
+ break;
+ case CK_CEC:
+ /* calculate CEC clock frequency */
+ if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){
+ cec_freq = IRC8M_VALUE / 244U;
+ }else{
+ cec_freq = LXTAL_VALUE;
+ }
+ ck_freq = cec_freq;
+ break;
+ case CK_USART:
+ /* calculate USART clock frequency */
+ if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+ usart_freq = apb2_freq;
+ }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+ usart_freq = cksys_freq;
+ }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+ usart_freq = LXTAL_VALUE;
+ }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){
+ usart_freq = IRC8M_VALUE;
+ }else{
+ }
+ ck_freq = usart_freq;
+ break;
+ default:
+ break;
+ }
+ return ck_freq;
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_syscfg.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_syscfg.c
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_syscfg.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_syscfg.c
index ad7a625b..70be0e7c 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_syscfg.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_syscfg.c
@@ -1,214 +1,214 @@
-/*!
- \file gd32f1x0_syscfg.c
- \brief SYSCFG driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_syscfg.h"
-
-/*!
- \brief reset the SYSCFG registers
- \param[in] none
- \param[out] none
- \retval none
-*/
-void syscfg_deinit(void)
-{
- rcu_periph_reset_enable(RCU_CFGCMPRST);
- rcu_periph_reset_disable(RCU_CFGCMPRST);
-}
-
-/*!
- \brief enable the DMA channels remapping
- \param[in] syscfg_dma_remap: specify the DMA channels to remap
- \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
- \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
- \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
- \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
- \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
- \param[out] none
- \retval none
-*/
-void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
-{
- SYSCFG_CFG0 |= syscfg_dma_remap;
-}
-
-/*!
- \brief disable the DMA channels remapping
- \param[in] syscfg_dma_remap: specify the DMA channels to remap
- \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
- \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
- \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
- \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
- \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
- \param[out] none
- \retval none
-*/
-void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
-{
- SYSCFG_CFG0 &= ~syscfg_dma_remap;
-}
-
-/*!
- \brief enable PB9 high current capability
- \param[in] none
- \param[out] none
- \retval none
-*/
-void syscfg_high_current_enable(void)
-{
- SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
-}
-
-/*!
- \brief disable PB9 high current capability
- \param[in] none
- \param[out] none
- \retval none
-*/
-void syscfg_high_current_disable(void)
-{
- SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
-}
-
-#ifdef GD32F170_190
-/*!
- \brief configure the VLCD intermediate voltage rail
- \param[in] vlcd_bias: specify VLCD bias
- \arg VLCD_BIAS1_2_RAIL1: VLCD bias is 1/2, using rail1
- \arg VLCD_BIAS1_2_RAIL2: VLCD bias is 1/2, using rail2
- \arg VLCD_BIAS1_2_RAIL3: VLCD bias is 1/2, using rail3
- \arg VLCD_BIAS1_3_RAIL1_2: VLCD bias is 1/3, using rail1 and rail2
- \arg VLCD_BIAS1_3_RAIL1_3: VLCD bias is 1/3, using rail1 and rail3
- \arg VLCD_BIAS1_4_RAILALL: VLCD bias is 1/4, using all rails
- \param[out] none
- \retval none
-*/
-void syscfg_vlcd_rail_config(uint8_t vlcd_bias)
-{
- uint32_t cfg1 = SYSCFG_CFG1;
-
- /* Clear system configuration register 1 */
- SYSCFG_CFG1 = 0U;
-
- switch(vlcd_bias){
- /* according to VLCD bias, configure rails combination */
- case VLCD_BIAS1_2_RAIL1:
- SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL1;
- break;
- case VLCD_BIAS1_2_RAIL2:
- SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL2;
- break;
- case VLCD_BIAS1_2_RAIL3:
- SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3;
- break;
- case VLCD_BIAS1_3_RAIL1_2:
- SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL2 | SYSCFG_VLCD_RAIL1;
- break;
- case VLCD_BIAS1_3_RAIL1_3:
- SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3 | SYSCFG_VLCD_RAIL1;
- break;
- case VLCD_BIAS1_4_RAILALL:
- SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3 | SYSCFG_VLCD_RAIL2 | SYSCFG_VLCD_RAIL1;
- break;
- default:
- SYSCFG_CFG1 = cfg1;
- break;
- }
-}
-#endif /* GD32F170_190 */
-
-/*!
- \brief configure the GPIO pin as EXTI Line
- \param[in] exti_port: specify the GPIO port used in EXTI
- \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port
- \param[in] exti_pin: specify the EXTI line
- \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
- \param[out] none
- \retval none
-*/
-void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
-{
- uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
- uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
-
- switch(exti_pin / EXTI_SS_JSTEP){
- case EXTISS0:
- /* clear EXTI source line(0..3) */
- SYSCFG_EXTISS0 &= clear_exti_mask;
- /* configure EXTI soure line(0..3) */
- SYSCFG_EXTISS0 |= config_exti_mask;
- break;
- case EXTISS1:
- /* clear EXTI soure line(4..7) */
- SYSCFG_EXTISS1 &= clear_exti_mask;
- /* configure EXTI soure line(4..7) */
- SYSCFG_EXTISS1 |= config_exti_mask;
- break;
- case EXTISS2:
- /* clear EXTI soure line(8..11) */
- SYSCFG_EXTISS2 &= clear_exti_mask;
- /* configure EXTI soure line(8..11) */
- SYSCFG_EXTISS2 |= config_exti_mask;
- break;
- case EXTISS3:
- /* clear EXTI soure line(12..15) */
- SYSCFG_EXTISS3 &= clear_exti_mask;
- /* configure EXTI soure line(12..15) */
- SYSCFG_EXTISS3 |= config_exti_mask;
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief connect TIMER0/14/15/16 break input to the selected parameter
- \param[in] syscfg_lock: Specify the parameter to be connected
- \arg SYSCFG_LOCK_LOCKUP: Cortex-M3 lockup output connected to the break input
- \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
- \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
- \param[out] none
- \retval none
-*/
-void syscfg_lock_config(uint32_t syscfg_lock)
-{
- SYSCFG_CFG2 |= syscfg_lock;
-}
-
-/*!
- \brief check if the specified flag in SYSCFG_CFG2 is set or not.
- \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check.
- \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
- \param[out] none
- \retval the syscfg_flag state returned (SET or RESET).
- */
-FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
-{
- if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear the flag in SYSCFG_CFG2 by writing 1.
- \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear.
- \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
- \param[out] none
- \retval none
-*/
-void syscfg_flag_clear(uint32_t syscfg_flag)
-{
- SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
-}
+/*!
+ \file gd32f1x0_syscfg.c
+ \brief SYSCFG driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_syscfg.h"
+
+/*!
+ \brief reset the SYSCFG registers
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void syscfg_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_CFGCMPRST);
+ rcu_periph_reset_disable(RCU_CFGCMPRST);
+}
+
+/*!
+ \brief enable the DMA channels remapping
+ \param[in] syscfg_dma_remap: specify the DMA channels to remap
+ \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
+ \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
+ \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
+ \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
+ \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
+ \param[out] none
+ \retval none
+*/
+void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
+{
+ SYSCFG_CFG0 |= syscfg_dma_remap;
+}
+
+/*!
+ \brief disable the DMA channels remapping
+ \param[in] syscfg_dma_remap: specify the DMA channels to remap
+ \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
+ \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
+ \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
+ \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
+ \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
+ \param[out] none
+ \retval none
+*/
+void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
+{
+ SYSCFG_CFG0 &= ~syscfg_dma_remap;
+}
+
+/*!
+ \brief enable PB9 high current capability
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void syscfg_high_current_enable(void)
+{
+ SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
+}
+
+/*!
+ \brief disable PB9 high current capability
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void syscfg_high_current_disable(void)
+{
+ SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
+}
+
+#ifdef GD32F170_190
+/*!
+ \brief configure the VLCD intermediate voltage rail
+ \param[in] vlcd_bias: specify VLCD bias
+ \arg VLCD_BIAS1_2_RAIL1: VLCD bias is 1/2, using rail1
+ \arg VLCD_BIAS1_2_RAIL2: VLCD bias is 1/2, using rail2
+ \arg VLCD_BIAS1_2_RAIL3: VLCD bias is 1/2, using rail3
+ \arg VLCD_BIAS1_3_RAIL1_2: VLCD bias is 1/3, using rail1 and rail2
+ \arg VLCD_BIAS1_3_RAIL1_3: VLCD bias is 1/3, using rail1 and rail3
+ \arg VLCD_BIAS1_4_RAILALL: VLCD bias is 1/4, using all rails
+ \param[out] none
+ \retval none
+*/
+void syscfg_vlcd_rail_config(uint8_t vlcd_bias)
+{
+ uint32_t cfg1 = SYSCFG_CFG1;
+
+ /* Clear system configuration register 1 */
+ SYSCFG_CFG1 = 0U;
+
+ switch(vlcd_bias){
+ /* according to VLCD bias, configure rails combination */
+ case VLCD_BIAS1_2_RAIL1:
+ SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL1;
+ break;
+ case VLCD_BIAS1_2_RAIL2:
+ SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL2;
+ break;
+ case VLCD_BIAS1_2_RAIL3:
+ SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3;
+ break;
+ case VLCD_BIAS1_3_RAIL1_2:
+ SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL2 | SYSCFG_VLCD_RAIL1;
+ break;
+ case VLCD_BIAS1_3_RAIL1_3:
+ SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3 | SYSCFG_VLCD_RAIL1;
+ break;
+ case VLCD_BIAS1_4_RAILALL:
+ SYSCFG_CFG1 |= SYSCFG_VLCD_RAIL3 | SYSCFG_VLCD_RAIL2 | SYSCFG_VLCD_RAIL1;
+ break;
+ default:
+ SYSCFG_CFG1 = cfg1;
+ break;
+ }
+}
+#endif /* GD32F170_190 */
+
+/*!
+ \brief configure the GPIO pin as EXTI Line
+ \param[in] exti_port: specify the GPIO port used in EXTI
+ \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port
+ \param[in] exti_pin: specify the EXTI line
+ \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
+ \param[out] none
+ \retval none
+*/
+void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
+{
+ uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
+ uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
+
+ switch(exti_pin / EXTI_SS_JSTEP){
+ case EXTISS0:
+ /* clear EXTI source line(0..3) */
+ SYSCFG_EXTISS0 &= clear_exti_mask;
+ /* configure EXTI soure line(0..3) */
+ SYSCFG_EXTISS0 |= config_exti_mask;
+ break;
+ case EXTISS1:
+ /* clear EXTI soure line(4..7) */
+ SYSCFG_EXTISS1 &= clear_exti_mask;
+ /* configure EXTI soure line(4..7) */
+ SYSCFG_EXTISS1 |= config_exti_mask;
+ break;
+ case EXTISS2:
+ /* clear EXTI soure line(8..11) */
+ SYSCFG_EXTISS2 &= clear_exti_mask;
+ /* configure EXTI soure line(8..11) */
+ SYSCFG_EXTISS2 |= config_exti_mask;
+ break;
+ case EXTISS3:
+ /* clear EXTI soure line(12..15) */
+ SYSCFG_EXTISS3 &= clear_exti_mask;
+ /* configure EXTI soure line(12..15) */
+ SYSCFG_EXTISS3 |= config_exti_mask;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief connect TIMER0/14/15/16 break input to the selected parameter
+ \param[in] syscfg_lock: Specify the parameter to be connected
+ \arg SYSCFG_LOCK_LOCKUP: Cortex-M3 lockup output connected to the break input
+ \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
+ \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
+ \param[out] none
+ \retval none
+*/
+void syscfg_lock_config(uint32_t syscfg_lock)
+{
+ SYSCFG_CFG2 |= syscfg_lock;
+}
+
+/*!
+ \brief check if the specified flag in SYSCFG_CFG2 is set or not.
+ \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check.
+ \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
+ \param[out] none
+ \retval the syscfg_flag state returned (SET or RESET).
+ */
+FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
+{
+ if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear the flag in SYSCFG_CFG2 by writing 1.
+ \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear.
+ \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
+ \param[out] none
+ \retval none
+*/
+void syscfg_flag_clear(uint32_t syscfg_flag)
+{
+ SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_timer.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_timer.c
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_timer.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_timer.c
index 21337ef1..4dad6363 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_timer.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_timer.c
@@ -1,1887 +1,1887 @@
-/*!
- \file gd32f1x0_timer.c
- \brief TIMER driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_timer.h"
-
-/*!
- \brief deinit a timer
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_deinit(uint32_t timer_periph)
-{
- switch(timer_periph){
- case TIMER0:
- /* reset TIMER0 */
- rcu_periph_reset_enable(RCU_TIMER0RST);
- rcu_periph_reset_disable(RCU_TIMER0RST);
- break;
- case TIMER1:
- /* reset TIMER1 */
- rcu_periph_reset_enable(RCU_TIMER1RST);
- rcu_periph_reset_disable(RCU_TIMER1RST);
- break;
- case TIMER2:
- /* reset TIMER2 */
- rcu_periph_reset_enable(RCU_TIMER2RST);
- rcu_periph_reset_disable(RCU_TIMER2RST);
- break;
- case TIMER5:
- /* reset TIMER5 */
- rcu_periph_reset_enable(RCU_TIMER5RST);
- rcu_periph_reset_disable(RCU_TIMER5RST);
- break;
- case TIMER13:
- /* reset TIMER13 */
- rcu_periph_reset_enable(RCU_TIMER13RST);
- rcu_periph_reset_disable(RCU_TIMER13RST);
- break;
- case TIMER14:
- /* reset TIMER14 */
- rcu_periph_reset_enable(RCU_TIMER14RST);
- rcu_periph_reset_disable(RCU_TIMER14RST);
- break;
- case TIMER15:
- /* reset TIMER15 */
- rcu_periph_reset_enable(RCU_TIMER15RST);
- rcu_periph_reset_disable(RCU_TIMER15RST);
- break;
- case TIMER16:
- /* reset TIMER16 */
- rcu_periph_reset_enable(RCU_TIMER16RST);
- rcu_periph_reset_disable(RCU_TIMER16RST);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief initialize TIMER counter
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] initpara: init parameter struct
- prescaler: prescaler value of the counter clock,0~65535
- alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH
- counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN
- period: counter auto reload value
- clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4
- repetitioncounter: counter repetition value,0~255
- \param[out] none
- \retval none
-*/
-void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
-{
- /* configure the counter prescaler value */
- TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
-
- /* configure the counter direction and aligned mode */
- if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){
- TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR|TIMER_CTL0_CAM);
- TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
- TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
- }else{
- TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
- TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
- }
-
- /* configure the autoreload value */
- TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
-
- if((TIMER5 != timer_periph)){
- /* reset the CKDIV bit */
- TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_CKDIV);
- TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
- }
-
- if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph)|| (TIMER16 == timer_periph)){
- /* configure the repetition counter value */
- TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
- }
-
- /* generate an update event */
- TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_PSC_RELOAD_NOW;
-}
-
-/*!
- \brief enable a timer
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_enable(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_COUNTER_ENABLE;
-}
-
-/*!
- \brief disable a timer
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_disable(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) &= (uint32_t)TIMER_COUNTER_DISABLE;
-}
-
-/*!
- \brief enable the auto reload shadow function
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_auto_reload_shadow_enable(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_ARSE_ENABLE;
-}
-
-/*!
- \brief disable the auto reload shadow function
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_auto_reload_shadow_disable(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) &= (uint32_t) TIMER_ARSE_DISABLE;
-}
-
-/*!
- \brief enable the update event
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_update_event_enable(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_UPDIS_ENABLE;
-}
-
-/*!
- \brief disable the update event
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_update_event_disable(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) &= (uint32_t) TIMER_UPDIS_DISABLE;
-}
-
-/*!
- \brief set TIMER counter alignment mode
- \param[in] timer_periph: TIMERx(x=0,1,2)
- \param[in] aligned:
- \arg TIMER_COUNTER_EDGE: edge-aligned mode
- \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
- \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
- \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
- \param[out] none
- \retval none
-*/
-void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
-{
- TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_CAM);
- TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
-}
-
-/*!
- \brief set TIMER counter up direction
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_counter_up_direction(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
- TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_COUNTER_UP;
-}
-
-/*!
- \brief set TIMER counter down direction
- \param[in] timer_periph: TIMERx(x=0,1,2)
- \param[out] none
- \retval none
-*/
-void timer_counter_down_direction(uint32_t timer_periph)
-{
- TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
- TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_COUNTER_DOWN;
-}
-
-/*!
- \brief configure TIMER prescaler
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] prescaler: prescaler value
- \param[in] pscreload: prescaler reload mode
- \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
- \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
- \param[out] none
- \retval none
-*/
-void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
-{
- TIMER_PSC(timer_periph) = (uint32_t)prescaler;
-
- if(TIMER_PSC_RELOAD_NOW == pscreload){
- TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
- }
-}
-
-/*!
- \brief configure TIMER repetition register value
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[in] repetition: the counter repetition value
- \param[out] none
- \retval none
-*/
-void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
-{
- TIMER_CREP(timer_periph) = (uint32_t)repetition;
-}
-
-/*!
- \brief configure TIMER autoreload register value
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] autoreload: the counter auto-reload value
- \param[out] none
- \retval none
-*/
-void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
-{
- TIMER_CAR(timer_periph) = (uint32_t)autoreload;
-}
-
-/*!
- \brief configure TIMER counter register value
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] counter: the counter value
- \param[out] none
- \retval none
-*/
-void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
-{
- TIMER_CNT(timer_periph) = (uint32_t)counter;
-}
-
-/*!
- \brief read TIMER counter value
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval counter value
-*/
-uint32_t timer_counter_read(uint32_t timer_periph)
-{
- uint32_t count_value = 0U;
- count_value = TIMER_CNT(timer_periph);
- return (count_value);
-}
-
-/*!
- \brief read TIMER prescaler value
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[out] none
- \retval prescaler register value
-*/
-uint16_t timer_prescaler_read(uint32_t timer_periph)
-{
- uint16_t prescaler_value = 0U;
- prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
- return (prescaler_value);
-}
-
-/*!
- \brief configure TIMER single pulse mode
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] spmode:
- \arg TIMER_SP_MODE_SINGLE: single pulse mode
- \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
- \param[out] none
- \retval none
-*/
-void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
-{
- if(TIMER_SP_MODE_SINGLE == spmode){
- TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
- }else if(TIMER_SP_MODE_REPETITIVE == spmode){
- TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
- }else{
- }
-}
-
-/*!
- \brief configure TIMER update source
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] update:
- \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
- \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
- \param[out] none
- \retval none
-*/
-void timer_update_source_config(uint32_t timer_periph, uint8_t update)
-{
- if(TIMER_UPDATE_SRC_REGULAR == update){
- TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
- }else if(update == TIMER_UPDATE_SRC_GLOBAL){
- TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
- }else{
- }
-}
-
-/*!
- \brief enable the TIMER interrupt
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] interrupt: timer interrupt enable source
- \arg TIMER_INT_UP: update interrupt enable
- \arg TIMER_INT_CH0: channel 0 interrupt enable
- \arg TIMER_INT_CH1: channel 1 interrupt enable
- \arg TIMER_INT_CH2: channel 2 interrupt enable
- \arg TIMER_INT_CH3: channel 3 interrupt enable
- \arg TIMER_INT_CMT: commutation interrupt enable
- \arg TIMER_INT_TRG: trigger interrupt enable
- \arg TIMER_INT_BRK: break interrupt enable
- \param[out] none
- \retval none
-*/
-void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
-{
- TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
-}
-
-/*!
- \brief disable the TIMER interrupt
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] interrupt: timer interrupt source enable
- \arg TIMER_INT_UP: update interrupt enable
- \arg TIMER_INT_CH0: channel 0 interrupt enable
- \arg TIMER_INT_CH1: channel 1 interrupt enable
- \arg TIMER_INT_CH2: channel 2 interrupt enable
- \arg TIMER_INT_CH3: channel 3 interrupt enable
- \arg TIMER_INT_CMT: commutation interrupt enable
- \arg TIMER_INT_TRG: trigger interrupt enable
- \arg TIMER_INT_BRK: break interrupt enable
- \param[out] none
- \retval none
-*/
-void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
-{
- TIMER_DMAINTEN(timer_periph) &= (uint32_t)(~ interrupt);
-}
-
-/*!
- \brief get timer interrupt flag
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] interrupt: the timer interrupt bits
- \arg TIMER_INT_FLAG_UP: update interrupt flag
- \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag
- \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag
- \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag
- \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag
- \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag
- \arg TIMER_INT_FLAG_TRG: trigger interrupt flag
- \arg TIMER_INT_FLAG_BRK: break interrupt flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
-{
- uint16_t intval = 0U, intenable = 0U;
-
- intval = (uint16_t)(TIMER_INTF(timer_periph) & interrupt);
- intenable = (uint16_t)(TIMER_DMAINTEN(timer_periph) & interrupt);
-
- if(((uint16_t)RESET != intval ) && (((uint16_t)RESET) != intenable)){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear TIMER interrupt flag
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] interrupt: the timer interrupt bits
- \arg TIMER_INT_FLAG_UP: update interrupt flag
- \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag
- \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag
- \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag
- \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag
- \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag
- \arg TIMER_INT_FLAG_TRG: trigger interrupt flag
- \arg TIMER_INT_FLAG_BRK: break interrupt flag
- \param[out] none
- \retval none
-*/
-void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
-{
- TIMER_INTF(timer_periph) &= (uint32_t)(~(uint32_t)interrupt);
-}
-
-/*!
- \brief get TIMER flags
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] flag: the timer interrupt flags
- \arg TIMER_FLAG_UP: update flag
- \arg TIMER_FLAG_CH0: channel 0 flag
- \arg TIMER_FLAG_CH1: channel 1 flag
- \arg TIMER_FLAG_CH2: channel 2 flag
- \arg TIMER_FLAG_CH3: channel 3 flag
- \arg TIMER_FLAG_CMT: channel commutation flag
- \arg TIMER_FLAG_TRG: trigger flag
- \arg TIMER_FLAG_BRK: break flag
- \arg TIMER_FLAG_CH0O: channel 0 overcapture flag
- \arg TIMER_FLAG_CH1O: channel 1 overcapture flag
- \arg TIMER_FLAG_CH2O: channel 2 overcapture flag
- \arg TIMER_FLAG_CH3O: channel 3 overcapture flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
-{
- if(((uint16_t)RESET) != ((uint16_t)(TIMER_INTF(timer_periph) & flag))){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear TIMER flags
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] flag: the timer interrupt flags
- \arg TIMER_FLAG_UP: update flag
- \arg TIMER_FLAG_CH0: channel 0 flag
- \arg TIMER_FLAG_CH1: channel 1 flag
- \arg TIMER_FLAG_CH2: channel 2 flag
- \arg TIMER_FLAG_CH3: channel 3 flag
- \arg TIMER_FLAG_CMT: channel commutation flag
- \arg TIMER_FLAG_TRG: trigger flag
- \arg TIMER_FLAG_BRK: break flag
- \arg TIMER_FLAG_CH0O: channel 0 overcapture flag
- \arg TIMER_FLAG_CH1O: channel 1 overcapture flag
- \arg TIMER_FLAG_CH2O: channel 2 overcapture flag
- \arg TIMER_FLAG_CH3O: channel 3 overcapture flag
- \param[out] none
- \retval none
-*/
-void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
-{
- TIMER_INTF(timer_periph) &= (uint32_t)(~(uint32_t)flag);
-}
-
-/*!
- \brief enable the TIMER DMA
- \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
- \param[in] dma: timer DMA source enable
- \arg TIMER_DMA_UPD: update DMA enable
- \arg TIMER_DMA_CH0D: channel 0 DMA enable
- \arg TIMER_DMA_CH1D: channel 1 DMA enable
- \arg TIMER_DMA_CH2D: channel 2 DMA enable
- \arg TIMER_DMA_CH3D: channel 3 DMA enable
- \arg TIMER_DMA_CMTD: channel commutation DMA request enable
- \arg TIMER_DMA_TRGD: trigger DMA enable
- \param[out] none
- \retval none
-*/
-void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
-{
- TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
-}
-
-/*!
- \brief disable the TIMER DMA
- \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
- \param[in] dma: timer DMA source enable
- \arg TIMER_DMA_UPD: update DMA enable
- \arg TIMER_DMA_CH0D: channel 0 DMA enable
- \arg TIMER_DMA_CH1D: channel 1 DMA enable
- \arg TIMER_DMA_CH2D: channel 2 DMA enable
- \arg TIMER_DMA_CH3D: channel 3 DMA enable
- \arg TIMER_DMA_CMTD: channel commutation DMA request enable
- \arg TIMER_DMA_TRGD: trigger DMA enable
- \param[out] none
- \retval none
-*/
-void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
-{
- TIMER_DMAINTEN(timer_periph) &= ~(uint32_t)dma;
-}
-
-/*!
- \brief channel DMA request source selection
- \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
- \param[in] dma_request: channel DMA request source selection
- \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
- \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
- \param[out] none
- \retval none
-*/
-void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
-{
- if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
- TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
- }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
- TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
- }else{
- }
-}
-
-/*!
- \brief configure the TIMER DMA transfer
- \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
- \param[in] dma_baseaddr:
- \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0
- \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1
- \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG
- \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN
- \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF
- \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG
- \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0
- \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1
- \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2
- \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT
- \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC
- \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR
- \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP
- \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV
- \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV
- \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV
- \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV
- \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP
- \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG
- \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB
- \param[in] dma_lenth:
- \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
- \param[out] none
- \retval none
-*/
-void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
-{
- TIMER_DMACFG(timer_periph) &= (uint32_t)(~(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
- TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
-}
-
-/*!
- \brief software generate events
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] event: the timer software event generation sources
- \arg TIMER_EVENT_SRC_UPG: update event generation
- \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation
- \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation
- \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation
- \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation
- \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation
- \arg TIMER_EVENT_SRC_TRGG: trigger event generation
- \arg TIMER_EVENT_SRC_BRKG: break event generation
- \param[out] none
- \retval none
-*/
-void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
-{
- TIMER_SWEVG(timer_periph) |= (uint32_t)event;
-}
-
-/*!
- \brief configure TIMER break function
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[in] breakpara: TIMER break parameter struct
- runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
- ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
- deadtime: 0~255
- breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
- outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
- protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
- breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
- \param[out] none
- \retval none
-*/
-void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
-{
- TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)breakpara->runoffstate) |
- ((uint32_t)breakpara->ideloffstate) |
- ((uint32_t)breakpara->deadtime) |
- ((uint32_t)breakpara->breakpolarity) |
- ((uint32_t)breakpara->outputautostate) |
- ((uint32_t)breakpara->protectmode) |
- ((uint32_t)breakpara->breakstate));
-}
-
-/*!
- \brief enable TIMER break function
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_break_enable(uint32_t timer_periph)
-{
- TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_BREAK_ENABLE;
-}
-
-/*!
- \brief disable TIMER break function
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_break_disable(uint32_t timer_periph)
-{
- TIMER_CCHP(timer_periph) &= (uint32_t)TIMER_BREAK_DISABLE;
-}
-
-/*!
- \brief enable TIMER output automatic function
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_automatic_output_enable(uint32_t timer_periph)
-{
- TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_OUTAUTO_ENABLE;
-}
-
-/*!
- \brief disable TIMER output automatic function
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[out] none
- \retval none
-*/
-void timer_automatic_output_disable(uint32_t timer_periph)
-{
- TIMER_CCHP(timer_periph) &= (uint32_t)TIMER_OUTAUTO_DISABLE;
-}
-
-/*!
- \brief configure TIMER primary output function
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[in] newvalue: ENABLE or DISABLE
- \param[out] none
- \retval none
-*/
-void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)
-{
- if(newvalue){
- TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
- }else{
- TIMER_CCHP(timer_periph) &= (uint32_t)(~ TIMER_CCHP_POEN);
- }
-}
-
-/*!
- \brief channel capture/compare control shadow register enable
- \param[in] timer_periph: TIMERx(x=0,14,15,16)
- \param[in] newvalue: ENABLE or DISABLE
- \param[out] none
- \retval none
-*/
-void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
-{
- if(newvalue){
- TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
- }else{
- TIMER_CTL1(timer_periph) &= (uint32_t)(~TIMER_CTL1_CCSE);
- }
-}
-
-/*!
- \brief configure TIMER channel control shadow register update control
- \param[in] timer_periph: TIMERx(x=0,1,2)
- \param[in] ccuctl: channel control shadow register update control
- \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
- \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
- \param[out] none
- \retval none
-*/
-void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
-{
- if(TIMER_UPDATECTL_CCU == ccuctl){
- TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
- }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
- TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
- }else{
- }
-}
-
-/*!
- \brief configure TIMER channel output function
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] ocpara: TIMER channeln output parameter struct
- outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
- outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
- ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
- ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
- ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
- ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
- \param[out] none
- \retval none
-*/
-void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- /* reset the CH0EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
- /* set the CH0EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
- /* reset the CH0P bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0P);
- /* set the CH0P bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
-
- if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
- /* reset the CH0NEN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NEN);
- /* set the CH0NEN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
- /* reset the CH0NP bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NP);
- /* set the CH0NP bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
- /* reset the ISO0 bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO0);
- /* set the ISO0 bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
- /* reset the ISO0N bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO0N);
- /* set the ISO0N bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
- }
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- /* reset the CH1EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
- /* set the CH1EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4);
- /* reset the CH1P bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1P);
- /* set the CH1P bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocpolarity << 4);
-
- if((TIMER0 == timer_periph)){
- /* reset the CH1NEN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NEN);
- /* set the CH1NEN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputnstate << 4);
- /* reset the CH1NP bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NP);
- /* set the CH1NP bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnpolarity << 4);
- /* reset the ISO1 bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO1);
- /* set the ISO1 bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocidlestate << 2);
- /* reset the ISO1N bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO1N);
- /* set the ISO1N bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnidlestate << 2);
- }
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- /* reset the CH2EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2EN);
- /* set the CH2EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8);
- /* reset the CH2P bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2P);
- /* set the CH2P bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocpolarity << 8);
-
- if((TIMER0 == timer_periph)){
- /* reset the CH2NEN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NEN);
- /* set the CH2NEN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputnstate << 8);
- /* reset the CH2NP bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NP);
- /* set the CH2NP bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnpolarity << 8);
- /* reset the ISO2 bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO2);
- /* set the ISO2 bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocidlestate << 4);
- /* reset the ISO2N bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO2N);
- /* set the ISO2N bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnidlestate << 4);
- }
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- /* reset the CH3EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3EN);
- /* set the CH3EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12);
- /* reset the CH3P bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3P);
- /* set the CH3P bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocpolarity << 12);
-
- if((TIMER0 == timer_periph)){
- /* reset the ISO3 bit */
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO3);
- /* set the ISO3 bit */
- TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocidlestate << 6);
- }
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel output compare mode
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] ocmode: channel output compare mode
- \arg TIMER_OC_MODE_TIMING: timing mode
- \arg TIMER_OC_MODE_ACTIVE: active mode
- \arg TIMER_OC_MODE_INACTIVE: inactive mode
- \arg TIMER_OC_MODE_TOGGLE: toggle mode
- \arg TIMER_OC_MODE_LOW: force low mode
- \arg TIMER_OC_MODE_HIGH: force high mode
- \arg TIMER_OC_MODE_PWM0: PWM0 mode
- \arg TIMER_OC_MODE_PWM1: PWM1 mode
- \param[out] none
- \retval none
-*/
-void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMCTL);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMCTL);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocmode << 8);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMCTL);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMCTL);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocmode << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel output pulse value
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] pulse: channel output pulse value
- \param[out] none
- \retval none
-*/
-void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel output shadow function
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] ocshadow: channel output shadow state
- \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
- \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
- \param[out] none
- \retval none
-*/
-void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMSEN);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMSEN);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocshadow << 8);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMSEN);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMSEN);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocshadow << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel output fast function
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] ocfast: channel output fast function
- \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
- \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
- \param[out] none
- \retval none
-*/
-void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMFEN);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMFEN);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMFEN);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMFEN);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel output clear function
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] occlear: channel output clear function
- \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
- \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
- \param[out] none
- \retval none
-*/
-void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMCEN);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMCEN);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMCEN);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMCEN);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel output polarity
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] ocpolarity: channel output polarity
- \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
- \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
- \param[out] none
- \retval none
-*/
-void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0P);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1P);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2P);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8);
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3P);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel complementary output polarity
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \param[in] ocnpolarity: channel complementary output polarity
- \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
- \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
- \param[out] none
- \retval none
-*/
-void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NP);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NP);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NP);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER OCPRE clear source selection
- \param[in] timer_periph: TIMERx(x=0,1,2)
- \param[in] clear: OCPRE clear source
- \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF
- \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input
- \param[out] none
- \retval none
-*/
-void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
-{
- if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC;
- }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){
- TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC;
- }else{
- }
-}
-
-/*!
- \brief configure TIMER channel enable state
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] state: TIMER channel enable state
- \arg TIMER_CCX_ENABLE: channel enable
- \arg TIMER_CCX_DISABLE: channel disable
- \param[out] none
- \retval none
-*/
-void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t state)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2EN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8);
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3EN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER channel complementary output enable state
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \param[in] ocnstate: TIMER channel complementary output enable state
- \arg TIMER_CCXN_ENABLE: channel complementary enable
- \arg TIMER_CCXN_DISABLE: channel complementary disable
- \param[out] none
- \retval none
-*/
-void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NEN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NEN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NEN);
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure TIMER input capture parameter
- \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] icpara: TIMER channel intput parameter struct
- icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE
- icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS
- icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
- icfilter: 0~15
- \param[out] none
- \retval none
-*/
-void timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct* icpara)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- /* reset the CH0EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
-
- /* reset the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
- TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
- /* reset the CH0MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
- /* reset the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(((uint32_t)icpara->icfilter << 4));
-
- /* set the CH0EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- /* reset the CH1EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
-
- /* reset the CH1P and CH1NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpara->icpolarity << 4);
- /* reset the CH1MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpara->icselection << 8);
- /* reset the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpara->icfilter << 12);
-
- /* set the CH1EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- /* reset the CH2EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2EN);
-
- /* reset the CH2P and CH2NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpara->icpolarity << 8);
- /* reset the CH2MS bit */
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2MS);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)(icpara->icselection);
- /* reset the CH2CAPFLT bit */
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2CAPFLT);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)icpara->icfilter<< 4);
-
- /* set the CH2EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- /* reset the CH3EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3EN);
-
- /* reset the CH3P bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH3P));
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpara->icpolarity << 12);
- /* reset the CH3MS bit */
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3MS);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)icpara->icselection << 8);
- /* reset the CH3CAPFLT bit */
- TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3CAPFLT);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)icpara->icfilter << 12);
-
- /* set the CH3EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
- break;
- default:
- break;
- }
- /* configure TIMER channel input capture prescaler value */
- timer_channel_input_capture_prescaler_config(timer_periph, channel,(uint32_t)icpara->icprescaler);
-}
-
-/*!
- \brief configure TIMER channel input capture prescaler value
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[in] prescaler: channel input capture prescaler value
- \arg TIMER_IC_PSC_DIV1: no prescaler
- \arg TIMER_IC_PSC_DIV2: divided by 2
- \arg TIMER_IC_PSC_DIV4: divided by 4
- \arg TIMER_IC_PSC_DIV8: divided by 8
- \param[out] none
- \retval none
-*/
-void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint32_t prescaler)
-{
- switch(channel){
- /* configure TIMER_CH_0 */
- case TIMER_CH_0:
- TIMER_CHCTL0(timer_periph) &= (uint32_t)(~ TIMER_CHCTL0_CH0CAPPSC);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
- break;
- /* configure TIMER_CH_1 */
- case TIMER_CH_1:
- TIMER_CHCTL0(timer_periph) &= (uint32_t)(~TIMER_CHCTL0_CH1CAPPSC);
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(prescaler << 8);
- break;
- /* configure TIMER_CH_2 */
- case TIMER_CH_2:
- TIMER_CHCTL1(timer_periph) &= (uint32_t)(~TIMER_CHCTL1_CH2CAPPSC);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
- break;
- /* configure TIMER_CH_3 */
- case TIMER_CH_3:
- TIMER_CHCTL1(timer_periph) &= (uint32_t)(~TIMER_CHCTL1_CH3CAPPSC);
- TIMER_CHCTL1(timer_periph) |= (uint32_t)(prescaler << 8);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief read TIMER channel capture compare register value
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
- \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
- \param[out] none
- \retval channel capture compare register value
-*/
-uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
-{
- uint32_t count_value=0U;
-
- switch(channel){
- case TIMER_CH_0:
- count_value = TIMER_CH0CV(timer_periph);
- break;
- case TIMER_CH_1:
- count_value = TIMER_CH1CV(timer_periph);
- break;
- case TIMER_CH_2:
- count_value = TIMER_CH2CV(timer_periph);
- break;
- case TIMER_CH_3:
- count_value = TIMER_CH3CV(timer_periph);
- break;
- default:
- break;
- }
- return (count_value);
-}
-
-/*!
- \brief configure TIMER input pwm capture function
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,14))
- \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
- \param[in] icpwm:TIMER channel intput pwm parameter struct
- icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
- icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
- icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
- icfilter: 0~15
- \param[out] none
- \retval none
-*/
-void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
-{
- uint16_t icpolarity = 0x0U;
- uint16_t icselection = 0x0U;
-
- if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
- icpolarity = TIMER_IC_POLARITY_FALLING;
- }else{
- icpolarity = TIMER_IC_POLARITY_RISING;
- }
-
- if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
- icselection = TIMER_IC_SELECTION_INDIRECTTI;
- }else{
- icselection = TIMER_IC_SELECTION_DIRECTTI;
- }
-
- if(TIMER_CH_0 == channel){
- /* reset the CH0EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
- /* reset the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
- /* set the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
- /* reset the CH0MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
- /* set the CH0MS bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
- /* reset the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
- /* set the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icfilter);
- /* set the CH0EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
- /* configure TIMER channel input capture prescaler value */
- timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint32_t)icpwm->icprescaler);
-
- /* reset the CH1EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
- /* reset the CH1P and CH1NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
- /* set the CH1P and CH1NP bits */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4);
- /* reset the CH1MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
- /* set the CH1MS bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8);
- /* reset the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
- /* set the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpwm->icfilter << 8);
- /* set the CH1EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
- /* configure TIMER channel input capture prescaler value */
- timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint32_t)icpwm->icprescaler);
- }else{
- /* reset the CH1EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
- /* reset the CH1P and CH1NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
- /* set the CH1P and CH1NP bits */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpwm->icpolarity << 4);
- /* reset the CH1MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
- /* set the CH1MS bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpwm->icselection << 8);
- /* reset the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
- /* set the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpwm->icfilter << 8);
- /* set the CH1EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
- /* configure TIMER channel input capture prescaler value */
- timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint32_t)icpwm->icprescaler);
-
- /* reset the CH0EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
- /* reset the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
- /* set the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
- /* reset the CH0MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
- /* set the CH0MS bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
- /* reset the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
- /* set the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)icpwm->icfilter;
- /* set the CH0EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
- /* configure TIMER channel input capture prescaler value */
- timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint32_t)icpwm->icprescaler);
- }
-}
-
-/*!
- \brief configure TIMER hall sensor mode
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] hallmode:
- \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
- \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
- \param[out] none
- \retval none
-*/
-void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
-{
- if(TIMER_HALLINTERFACE_ENABLE == hallmode){
- TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
- }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
- TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
- }else{
- }
-}
-
-/*!
- \brief select TIMER input trigger source
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] intrigger:
- \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
- \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
- \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
- \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
- \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
- \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
- \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
- \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger
- \param[out] none
- \retval none
-*/
-void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)
-{
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_TRGS);
- TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
-}
-
-/*!
- \brief select TIMER master mode output trigger source
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] outrigger:
- \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output
- \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output
- \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output
- \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO
- \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output
- \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output
- \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output
- \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output
- \param[out] none
- \retval none
-*/
-void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
-{
- TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_MMC);
- TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
-}
-
-/*!
- \brief select TIMER slave mode
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] slavemode:
- \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
- \arg TIMER_ENCODER_MODE0: encoder mode 0
- \arg TIMER_ENCODER_MODE1: encoder mode 1
- \arg TIMER_ENCODER_MODE2: encoder mode 2
- \arg TIMER_SLAVE_MODE_RESTART: restart mode
- \arg TIMER_SLAVE_MODE_PAUSE: pause mode
- \arg TIMER_SLAVE_MODE_EVENT: event mode
- \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.
- \param[out] none
- \retval none
-*/
-
-void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)
-{
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
-
- TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
-}
-
-/*!
- \brief configure TIMER master slave mode
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] masterslave:
- \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
- \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
- \param[out] none
- \retval none
-*/
-void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
-{
- if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
- }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
- TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
- }else{
- }
-}
-
-/*!
- \brief configure TIMER external trigger input
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] extprescaler:
- \arg TIMER_EXT_TRI_PSC_OFF: no divided
- \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
- \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
- \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
- \param[in] expolarity:
- \arg TIMER_ETP_FALLING: active low or falling edge active
- \arg TIMER_ETP_RISING: active high or rising edge active
- \param[in] extfilter: a value between 0x00 and 0x0F
- \param[out] none
- \retval none
-*/
-void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
-{
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC));
- TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity);
- TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << (uint16_t)8);
-}
-
-/*!
- \brief configure TIMER quadrature decoder mode
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] decomode:
- \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
- \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
- \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
- \param[in] ic0polarity:
- \arg TIMER_IC_POLARITY_RISING: capture rising edge
- \arg TIMER_IC_POLARITY_FALLING: capture falling edge
- \param[in] ic1polarity:
- \arg TIMER_IC_POLARITY_RISING: capture rising edge
- \arg TIMER_IC_POLARITY_FALLING: capture falling edge
- \param[out] none
- \retval none
-*/
-void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
-{
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
- TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
-
- TIMER_CHCTL0(timer_periph) &= (uint32_t)(((uint32_t)(~TIMER_CHCTL0_CH0MS))&((uint32_t)(~TIMER_CHCTL0_CH1MS)));
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8));
-
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
- TIMER_CHCTL2(timer_periph) |= (uint32_t)(ic0polarity|((uint32_t)ic1polarity << 4U));
-}
-
-/*!
- \brief configure TIMER internal clock mode
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[out] none
- \retval none
-*/
-void timer_internal_clock_config(uint32_t timer_periph)
-{
- TIMER_SMCFG(timer_periph) &= (uint32_t)TIMER_SLAVE_MODE_DISABLE;
-}
-
-/*!
- \brief configure TIMER the internal trigger as external clock input
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] intrigger:
- \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
- \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
- \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
- \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
- \param[out] none
- \retval none
-*/
-void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
-{
- timer_input_trigger_source_select(timer_periph, intrigger);
- TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
-}
-
-/*!
- \brief configure TIMER the external trigger as external clock input
- \param[in] timer_periph: TIMERx(x=0,1,2,14)
- \param[in] extrigger:
- \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
- \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
- \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
- \param[in] expolarity:
- \arg TIMER_IC_POLARITY_RISING: active low or falling edge active
- \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active
- \param[in] extfilter: a value between 0 and 15
- \param[out] none
- \retval none
-*/
-void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
-{
- if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
- /* reset the CH1EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
- /* reset the CH1NP bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
- /* set the CH1NP bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
- /* reset the CH1MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
- /* set the CH1MS bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
- /* reset the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
- /* set the CH1CAPFLT bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
- /* set the CH1EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
- }else{
- /* reset the CH0EN bit */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
- /* reset the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
- /* set the CH0P and CH0NP bits */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
- /* reset the CH0MS bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
- /* set the CH0MS bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
- /* reset the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
- /* reset the CH0CAPFLT bit */
- TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
- /* set the CH0EN bit */
- TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
- }
- /* select TIMER input trigger source */
- timer_input_trigger_source_select(timer_periph, extrigger);
- /* reset the SMC bit */
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
- /* set the SMC bit */
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
-}
-
-/*!
- \brief configure TIMER the external clock mode0
- \param[in] timer_periph: TIMERx(x=0,1,2)
- \param[in] extprescaler:
- \arg TIMER_EXT_TRI_PSC_OFF: no divided
- \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
- \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
- \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
- \param[in] expolarity:
- \arg TIMER_ETP_FALLING: active low or falling edge active
- \arg TIMER_ETP_RISING: active high or rising edge active
- \param[in] extfilter: a value between 0 and 15
- \param[out] none
- \retval none
-*/
-void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
-{
- /* configure TIMER external trigger input */
- timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
-
- /* reset the SMC bit */
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
- /* set the SMC bit */
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
-
- /* reset the TRGS bit */
- TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_TRGS);
- /* set the TRGS bit */
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_TRGSEL_ETIFP;
-}
-
-/*!
- \brief configure TIMER the external clock mode1
- \param[in] timer_periph: TIMERx(x=0,1,2)
- \param[in] extprescaler:
- \arg TIMER_EXT_TRI_PSC_OFF: no divided
- \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
- \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
- \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
- \param[in] expolarity:
- \arg TIMER_ETP_FALLING: active low or falling edge active
- \arg TIMER_ETP_RISING: active high or rising edge active
- \param[in] extfilter: a value between 0 and 15
- \param[out] none
- \retval none
-*/
-void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
- uint32_t expolarity, uint32_t extfilter)
-{
- /* configure TIMER external trigger input */
- timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
-
- TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
-}
-
-/*!
- \brief disable TIMER the external clock mode1
- \param[in] timer_periph: TIMERx(x=0..4,7)
- \param[out] none
- \retval none
-*/
-void timer_external_clock_mode1_disable(uint32_t timer_periph)
-{
- TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
-}
-
-/*!
- \brief configure TIMER13 channel0 remap function
- \param[in] timer_periph: TIMERx(x=13)
- \param[in] channel:
- \arg TIMER_CH_0: TIMER channel0(TIMERx(x=13))
- \param[in] remap:
- \arg TIMER_IRMP_CI0_RMP_GPIO: channel 0 input is connected to GPIO
- \arg TIMER_IRMP_CI0_RTCCLK: channel 0 input is connected to the RTCCLK
- \arg TIMER_IRMP_CI0_HXTALDIV32: channel 0 input is connected to HXTAL/32 clock
- \arg TIMER_IRMP_CI0_CKOUTSEL: channel 0 input is connected to CKOUTSEL
- \param[out] none
- \retval none
-*/
-void timer_channel_remap_config(uint32_t timer_periph, uint16_t channel, uint32_t remap)
-{
- if(TIMER_CH_0 == channel){
- TIMER_IRMP(timer_periph) = (uint32_t)remap;
- }
-}
-
-#ifdef GD32F170_190
-
-/*!
- \brief configure TIMER cc register selection
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] ccsel:
- \arg TIMER_CHVSEL_DISABLE: write CHxVAL register selection disable
- \arg TIMER_CHVSEL_ENABLE: write CHxVAL register selection enable
- \param[out] none
- \retval none
-*/
-void timer_write_cc_register_config(uint32_t timer_periph, uint32_t ccsel)
-{
- if(ccsel){
- TIMER_CFG(timer_periph) |= (uint32_t)ccsel;
- }else{
- TIMER_CFG(timer_periph) &= (uint32_t)ccsel;
- }
-}
-
-/*!
- \brief configure TIMER output value selection
- \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
- \param[in] outsel:
- \arg TIMER_OUTSEL_DISABLE: output value selection disable
- \arg TIMER_OUTSEL_ENABLE: output value selection enable
- \param[out] none
- \retval none
-*/
-void timer_output_value_selection_config(uint32_t timer_periph, uint32_t outsel)
-{
- if(outsel){
- TIMER_CFG(timer_periph) |= (uint32_t)outsel;
- }else{
- TIMER_CFG(timer_periph) &= (uint32_t)outsel;
- }
-}
-
-#endif /* GD32F170_190 */
+/*!
+ \file gd32f1x0_timer.c
+ \brief TIMER driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_timer.h"
+
+/*!
+ \brief deinit a timer
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_deinit(uint32_t timer_periph)
+{
+ switch(timer_periph){
+ case TIMER0:
+ /* reset TIMER0 */
+ rcu_periph_reset_enable(RCU_TIMER0RST);
+ rcu_periph_reset_disable(RCU_TIMER0RST);
+ break;
+ case TIMER1:
+ /* reset TIMER1 */
+ rcu_periph_reset_enable(RCU_TIMER1RST);
+ rcu_periph_reset_disable(RCU_TIMER1RST);
+ break;
+ case TIMER2:
+ /* reset TIMER2 */
+ rcu_periph_reset_enable(RCU_TIMER2RST);
+ rcu_periph_reset_disable(RCU_TIMER2RST);
+ break;
+ case TIMER5:
+ /* reset TIMER5 */
+ rcu_periph_reset_enable(RCU_TIMER5RST);
+ rcu_periph_reset_disable(RCU_TIMER5RST);
+ break;
+ case TIMER13:
+ /* reset TIMER13 */
+ rcu_periph_reset_enable(RCU_TIMER13RST);
+ rcu_periph_reset_disable(RCU_TIMER13RST);
+ break;
+ case TIMER14:
+ /* reset TIMER14 */
+ rcu_periph_reset_enable(RCU_TIMER14RST);
+ rcu_periph_reset_disable(RCU_TIMER14RST);
+ break;
+ case TIMER15:
+ /* reset TIMER15 */
+ rcu_periph_reset_enable(RCU_TIMER15RST);
+ rcu_periph_reset_disable(RCU_TIMER15RST);
+ break;
+ case TIMER16:
+ /* reset TIMER16 */
+ rcu_periph_reset_enable(RCU_TIMER16RST);
+ rcu_periph_reset_disable(RCU_TIMER16RST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief initialize TIMER counter
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] initpara: init parameter struct
+ prescaler: prescaler value of the counter clock,0~65535
+ alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH
+ counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN
+ period: counter auto reload value
+ clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4
+ repetitioncounter: counter repetition value,0~255
+ \param[out] none
+ \retval none
+*/
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
+{
+ /* configure the counter prescaler value */
+ TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
+
+ /* configure the counter direction and aligned mode */
+ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){
+ TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR|TIMER_CTL0_CAM);
+ TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
+ TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
+ }else{
+ TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
+ TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
+ }
+
+ /* configure the autoreload value */
+ TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
+
+ if((TIMER5 != timer_periph)){
+ /* reset the CKDIV bit */
+ TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_CKDIV);
+ TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
+ }
+
+ if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph)|| (TIMER16 == timer_periph)){
+ /* configure the repetition counter value */
+ TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
+ }
+
+ /* generate an update event */
+ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_PSC_RELOAD_NOW;
+}
+
+/*!
+ \brief enable a timer
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_enable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_COUNTER_ENABLE;
+}
+
+/*!
+ \brief disable a timer
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_disable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= (uint32_t)TIMER_COUNTER_DISABLE;
+}
+
+/*!
+ \brief enable the auto reload shadow function
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_auto_reload_shadow_enable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_ARSE_ENABLE;
+}
+
+/*!
+ \brief disable the auto reload shadow function
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_auto_reload_shadow_disable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= (uint32_t) TIMER_ARSE_DISABLE;
+}
+
+/*!
+ \brief enable the update event
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_update_event_enable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_UPDIS_ENABLE;
+}
+
+/*!
+ \brief disable the update event
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_update_event_disable(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= (uint32_t) TIMER_UPDIS_DISABLE;
+}
+
+/*!
+ \brief set TIMER counter alignment mode
+ \param[in] timer_periph: TIMERx(x=0,1,2)
+ \param[in] aligned:
+ \arg TIMER_COUNTER_EDGE: edge-aligned mode
+ \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
+ \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
+ \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
+ \param[out] none
+ \retval none
+*/
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
+{
+ TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_CAM);
+ TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
+}
+
+/*!
+ \brief set TIMER counter up direction
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_counter_up_direction(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_COUNTER_UP;
+}
+
+/*!
+ \brief set TIMER counter down direction
+ \param[in] timer_periph: TIMERx(x=0,1,2)
+ \param[out] none
+ \retval none
+*/
+void timer_counter_down_direction(uint32_t timer_periph)
+{
+ TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_COUNTER_DOWN;
+}
+
+/*!
+ \brief configure TIMER prescaler
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] prescaler: prescaler value
+ \param[in] pscreload: prescaler reload mode
+ \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
+ \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
+ \param[out] none
+ \retval none
+*/
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
+{
+ TIMER_PSC(timer_periph) = (uint32_t)prescaler;
+
+ if(TIMER_PSC_RELOAD_NOW == pscreload){
+ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
+ }
+}
+
+/*!
+ \brief configure TIMER repetition register value
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[in] repetition: the counter repetition value
+ \param[out] none
+ \retval none
+*/
+void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
+{
+ TIMER_CREP(timer_periph) = (uint32_t)repetition;
+}
+
+/*!
+ \brief configure TIMER autoreload register value
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] autoreload: the counter auto-reload value
+ \param[out] none
+ \retval none
+*/
+void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
+{
+ TIMER_CAR(timer_periph) = (uint32_t)autoreload;
+}
+
+/*!
+ \brief configure TIMER counter register value
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] counter: the counter value
+ \param[out] none
+ \retval none
+*/
+void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
+{
+ TIMER_CNT(timer_periph) = (uint32_t)counter;
+}
+
+/*!
+ \brief read TIMER counter value
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval counter value
+*/
+uint32_t timer_counter_read(uint32_t timer_periph)
+{
+ uint32_t count_value = 0U;
+ count_value = TIMER_CNT(timer_periph);
+ return (count_value);
+}
+
+/*!
+ \brief read TIMER prescaler value
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[out] none
+ \retval prescaler register value
+*/
+uint16_t timer_prescaler_read(uint32_t timer_periph)
+{
+ uint16_t prescaler_value = 0U;
+ prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
+ return (prescaler_value);
+}
+
+/*!
+ \brief configure TIMER single pulse mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] spmode:
+ \arg TIMER_SP_MODE_SINGLE: single pulse mode
+ \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
+ \param[out] none
+ \retval none
+*/
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode)
+{
+ if(TIMER_SP_MODE_SINGLE == spmode){
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
+ }else if(TIMER_SP_MODE_REPETITIVE == spmode){
+ TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
+ }else{
+ }
+}
+
+/*!
+ \brief configure TIMER update source
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] update:
+ \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
+ \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
+ \param[out] none
+ \retval none
+*/
+void timer_update_source_config(uint32_t timer_periph, uint8_t update)
+{
+ if(TIMER_UPDATE_SRC_REGULAR == update){
+ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
+ }else if(update == TIMER_UPDATE_SRC_GLOBAL){
+ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
+ }else{
+ }
+}
+
+/*!
+ \brief enable the TIMER interrupt
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] interrupt: timer interrupt enable source
+ \arg TIMER_INT_UP: update interrupt enable
+ \arg TIMER_INT_CH0: channel 0 interrupt enable
+ \arg TIMER_INT_CH1: channel 1 interrupt enable
+ \arg TIMER_INT_CH2: channel 2 interrupt enable
+ \arg TIMER_INT_CH3: channel 3 interrupt enable
+ \arg TIMER_INT_CMT: commutation interrupt enable
+ \arg TIMER_INT_TRG: trigger interrupt enable
+ \arg TIMER_INT_BRK: break interrupt enable
+ \param[out] none
+ \retval none
+*/
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
+{
+ TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
+}
+
+/*!
+ \brief disable the TIMER interrupt
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] interrupt: timer interrupt source enable
+ \arg TIMER_INT_UP: update interrupt enable
+ \arg TIMER_INT_CH0: channel 0 interrupt enable
+ \arg TIMER_INT_CH1: channel 1 interrupt enable
+ \arg TIMER_INT_CH2: channel 2 interrupt enable
+ \arg TIMER_INT_CH3: channel 3 interrupt enable
+ \arg TIMER_INT_CMT: commutation interrupt enable
+ \arg TIMER_INT_TRG: trigger interrupt enable
+ \arg TIMER_INT_BRK: break interrupt enable
+ \param[out] none
+ \retval none
+*/
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
+{
+ TIMER_DMAINTEN(timer_periph) &= (uint32_t)(~ interrupt);
+}
+
+/*!
+ \brief get timer interrupt flag
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] interrupt: the timer interrupt bits
+ \arg TIMER_INT_FLAG_UP: update interrupt flag
+ \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag
+ \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag
+ \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag
+ \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag
+ \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag
+ \arg TIMER_INT_FLAG_TRG: trigger interrupt flag
+ \arg TIMER_INT_FLAG_BRK: break interrupt flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
+{
+ uint16_t intval = 0U, intenable = 0U;
+
+ intval = (uint16_t)(TIMER_INTF(timer_periph) & interrupt);
+ intenable = (uint16_t)(TIMER_DMAINTEN(timer_periph) & interrupt);
+
+ if(((uint16_t)RESET != intval ) && (((uint16_t)RESET) != intenable)){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear TIMER interrupt flag
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] interrupt: the timer interrupt bits
+ \arg TIMER_INT_FLAG_UP: update interrupt flag
+ \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag
+ \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag
+ \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag
+ \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag
+ \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag
+ \arg TIMER_INT_FLAG_TRG: trigger interrupt flag
+ \arg TIMER_INT_FLAG_BRK: break interrupt flag
+ \param[out] none
+ \retval none
+*/
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
+{
+ TIMER_INTF(timer_periph) &= (uint32_t)(~(uint32_t)interrupt);
+}
+
+/*!
+ \brief get TIMER flags
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] flag: the timer interrupt flags
+ \arg TIMER_FLAG_UP: update flag
+ \arg TIMER_FLAG_CH0: channel 0 flag
+ \arg TIMER_FLAG_CH1: channel 1 flag
+ \arg TIMER_FLAG_CH2: channel 2 flag
+ \arg TIMER_FLAG_CH3: channel 3 flag
+ \arg TIMER_FLAG_CMT: channel commutation flag
+ \arg TIMER_FLAG_TRG: trigger flag
+ \arg TIMER_FLAG_BRK: break flag
+ \arg TIMER_FLAG_CH0O: channel 0 overcapture flag
+ \arg TIMER_FLAG_CH1O: channel 1 overcapture flag
+ \arg TIMER_FLAG_CH2O: channel 2 overcapture flag
+ \arg TIMER_FLAG_CH3O: channel 3 overcapture flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
+{
+ if(((uint16_t)RESET) != ((uint16_t)(TIMER_INTF(timer_periph) & flag))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear TIMER flags
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] flag: the timer interrupt flags
+ \arg TIMER_FLAG_UP: update flag
+ \arg TIMER_FLAG_CH0: channel 0 flag
+ \arg TIMER_FLAG_CH1: channel 1 flag
+ \arg TIMER_FLAG_CH2: channel 2 flag
+ \arg TIMER_FLAG_CH3: channel 3 flag
+ \arg TIMER_FLAG_CMT: channel commutation flag
+ \arg TIMER_FLAG_TRG: trigger flag
+ \arg TIMER_FLAG_BRK: break flag
+ \arg TIMER_FLAG_CH0O: channel 0 overcapture flag
+ \arg TIMER_FLAG_CH1O: channel 1 overcapture flag
+ \arg TIMER_FLAG_CH2O: channel 2 overcapture flag
+ \arg TIMER_FLAG_CH3O: channel 3 overcapture flag
+ \param[out] none
+ \retval none
+*/
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
+{
+ TIMER_INTF(timer_periph) &= (uint32_t)(~(uint32_t)flag);
+}
+
+/*!
+ \brief enable the TIMER DMA
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
+ \param[in] dma: timer DMA source enable
+ \arg TIMER_DMA_UPD: update DMA enable
+ \arg TIMER_DMA_CH0D: channel 0 DMA enable
+ \arg TIMER_DMA_CH1D: channel 1 DMA enable
+ \arg TIMER_DMA_CH2D: channel 2 DMA enable
+ \arg TIMER_DMA_CH3D: channel 3 DMA enable
+ \arg TIMER_DMA_CMTD: channel commutation DMA request enable
+ \arg TIMER_DMA_TRGD: trigger DMA enable
+ \param[out] none
+ \retval none
+*/
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
+{
+ TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
+}
+
+/*!
+ \brief disable the TIMER DMA
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
+ \param[in] dma: timer DMA source enable
+ \arg TIMER_DMA_UPD: update DMA enable
+ \arg TIMER_DMA_CH0D: channel 0 DMA enable
+ \arg TIMER_DMA_CH1D: channel 1 DMA enable
+ \arg TIMER_DMA_CH2D: channel 2 DMA enable
+ \arg TIMER_DMA_CH3D: channel 3 DMA enable
+ \arg TIMER_DMA_CMTD: channel commutation DMA request enable
+ \arg TIMER_DMA_TRGD: trigger DMA enable
+ \param[out] none
+ \retval none
+*/
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
+{
+ TIMER_DMAINTEN(timer_periph) &= ~(uint32_t)dma;
+}
+
+/*!
+ \brief channel DMA request source selection
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
+ \param[in] dma_request: channel DMA request source selection
+ \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
+ \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
+ \param[out] none
+ \retval none
+*/
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
+{
+ if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
+ }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
+ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
+ }else{
+ }
+}
+
+/*!
+ \brief configure the TIMER DMA transfer
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16)
+ \param[in] dma_baseaddr:
+ \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0
+ \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1
+ \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG
+ \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN
+ \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF
+ \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG
+ \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0
+ \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1
+ \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2
+ \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT
+ \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC
+ \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR
+ \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP
+ \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV
+ \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV
+ \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV
+ \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV
+ \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP
+ \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG
+ \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB
+ \param[in] dma_lenth:
+ \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
+ \param[out] none
+ \retval none
+*/
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
+{
+ TIMER_DMACFG(timer_periph) &= (uint32_t)(~(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
+ TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
+}
+
+/*!
+ \brief software generate events
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] event: the timer software event generation sources
+ \arg TIMER_EVENT_SRC_UPG: update event generation
+ \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation
+ \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation
+ \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation
+ \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation
+ \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation
+ \arg TIMER_EVENT_SRC_TRGG: trigger event generation
+ \arg TIMER_EVENT_SRC_BRKG: break event generation
+ \param[out] none
+ \retval none
+*/
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
+{
+ TIMER_SWEVG(timer_periph) |= (uint32_t)event;
+}
+
+/*!
+ \brief configure TIMER break function
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[in] breakpara: TIMER break parameter struct
+ runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
+ ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
+ deadtime: 0~255
+ breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
+ outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
+ protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
+ breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
+ \param[out] none
+ \retval none
+*/
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
+{
+ TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)breakpara->runoffstate) |
+ ((uint32_t)breakpara->ideloffstate) |
+ ((uint32_t)breakpara->deadtime) |
+ ((uint32_t)breakpara->breakpolarity) |
+ ((uint32_t)breakpara->outputautostate) |
+ ((uint32_t)breakpara->protectmode) |
+ ((uint32_t)breakpara->breakstate));
+}
+
+/*!
+ \brief enable TIMER break function
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_break_enable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_BREAK_ENABLE;
+}
+
+/*!
+ \brief disable TIMER break function
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_break_disable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) &= (uint32_t)TIMER_BREAK_DISABLE;
+}
+
+/*!
+ \brief enable TIMER output automatic function
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_automatic_output_enable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_OUTAUTO_ENABLE;
+}
+
+/*!
+ \brief disable TIMER output automatic function
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[out] none
+ \retval none
+*/
+void timer_automatic_output_disable(uint32_t timer_periph)
+{
+ TIMER_CCHP(timer_periph) &= (uint32_t)TIMER_OUTAUTO_DISABLE;
+}
+
+/*!
+ \brief configure TIMER primary output function
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)
+{
+ if(newvalue){
+ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
+ }else{
+ TIMER_CCHP(timer_periph) &= (uint32_t)(~ TIMER_CCHP_POEN);
+ }
+}
+
+/*!
+ \brief channel capture/compare control shadow register enable
+ \param[in] timer_periph: TIMERx(x=0,14,15,16)
+ \param[in] newvalue: ENABLE or DISABLE
+ \param[out] none
+ \retval none
+*/
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
+{
+ if(newvalue){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
+ }else{
+ TIMER_CTL1(timer_periph) &= (uint32_t)(~TIMER_CTL1_CCSE);
+ }
+}
+
+/*!
+ \brief configure TIMER channel control shadow register update control
+ \param[in] timer_periph: TIMERx(x=0,1,2)
+ \param[in] ccuctl: channel control shadow register update control
+ \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
+ \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
+ \param[out] none
+ \retval none
+*/
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
+{
+ if(TIMER_UPDATECTL_CCU == ccuctl){
+ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
+ }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
+ }else{
+ }
+}
+
+/*!
+ \brief configure TIMER channel output function
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] ocpara: TIMER channeln output parameter struct
+ outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
+ outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
+ ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
+ ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
+ ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
+ ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
+ /* reset the CH0P bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0P);
+ /* set the CH0P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
+
+ if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){
+ /* reset the CH0NEN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NEN);
+ /* set the CH0NEN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
+ /* reset the CH0NP bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NP);
+ /* set the CH0NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
+ /* reset the ISO0 bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO0);
+ /* set the ISO0 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
+ /* reset the ISO0N bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO0N);
+ /* set the ISO0N bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
+ }
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4);
+ /* reset the CH1P bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1P);
+ /* set the CH1P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocpolarity << 4);
+
+ if((TIMER0 == timer_periph)){
+ /* reset the CH1NEN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NEN);
+ /* set the CH1NEN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputnstate << 4);
+ /* reset the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NP);
+ /* set the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnpolarity << 4);
+ /* reset the ISO1 bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO1);
+ /* set the ISO1 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocidlestate << 2);
+ /* reset the ISO1N bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO1N);
+ /* set the ISO1N bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnidlestate << 2);
+ }
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ /* reset the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2EN);
+ /* set the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8);
+ /* reset the CH2P bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2P);
+ /* set the CH2P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocpolarity << 8);
+
+ if((TIMER0 == timer_periph)){
+ /* reset the CH2NEN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NEN);
+ /* set the CH2NEN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputnstate << 8);
+ /* reset the CH2NP bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NP);
+ /* set the CH2NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnpolarity << 8);
+ /* reset the ISO2 bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO2);
+ /* set the ISO2 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocidlestate << 4);
+ /* reset the ISO2N bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO2N);
+ /* set the ISO2N bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocnidlestate << 4);
+ }
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ /* reset the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3EN);
+ /* set the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12);
+ /* reset the CH3P bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3P);
+ /* set the CH3P bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocpolarity << 12);
+
+ if((TIMER0 == timer_periph)){
+ /* reset the ISO3 bit */
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_ISO3);
+ /* set the ISO3 bit */
+ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)ocpara->ocidlestate << 6);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output compare mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] ocmode: channel output compare mode
+ \arg TIMER_OC_MODE_TIMING: timing mode
+ \arg TIMER_OC_MODE_ACTIVE: active mode
+ \arg TIMER_OC_MODE_INACTIVE: inactive mode
+ \arg TIMER_OC_MODE_TOGGLE: toggle mode
+ \arg TIMER_OC_MODE_LOW: force low mode
+ \arg TIMER_OC_MODE_HIGH: force high mode
+ \arg TIMER_OC_MODE_PWM0: PWM0 mode
+ \arg TIMER_OC_MODE_PWM1: PWM1 mode
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMCTL);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMCTL);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocmode << 8);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMCTL);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMCTL);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocmode << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output pulse value
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] pulse: channel output pulse value
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output shadow function
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] ocshadow: channel output shadow state
+ \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
+ \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMSEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMSEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocshadow << 8);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMSEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMSEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocshadow << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output fast function
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] ocfast: channel output fast function
+ \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
+ \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMFEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMFEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMFEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMFEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output clear function
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] occlear: channel output clear function
+ \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
+ \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0COMCEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1COMCEN);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2COMCEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3COMCEN);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel output polarity
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] ocpolarity: channel output polarity
+ \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
+ \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8);
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3P);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel complementary output polarity
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \param[in] ocnpolarity: channel complementary output polarity
+ \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
+ \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
+ \param[out] none
+ \retval none
+*/
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NP);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NP);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NP);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER OCPRE clear source selection
+ \param[in] timer_periph: TIMERx(x=0,1,2)
+ \param[in] clear: OCPRE clear source
+ \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF
+ \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input
+ \param[out] none
+ \retval none
+*/
+void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear)
+{
+ if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC;
+ }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC;
+ }else{
+ }
+}
+
+/*!
+ \brief configure TIMER channel enable state
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] state: TIMER channel enable state
+ \arg TIMER_CCX_ENABLE: channel enable
+ \arg TIMER_CCX_DISABLE: channel disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t state)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8);
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3EN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER channel complementary output enable state
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \param[in] ocnstate: TIMER channel complementary output enable state
+ \arg TIMER_CCXN_ENABLE: channel complementary enable
+ \arg TIMER_CCXN_DISABLE: channel complementary disable
+ \param[out] none
+ \retval none
+*/
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0NEN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1NEN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2NEN);
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure TIMER input capture parameter
+ \param[in] timer_periph: TIMERx(x=0,1,2,5,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] icpara: TIMER channel intput parameter struct
+ icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE
+ icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS
+ icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
+ icfilter: 0~15
+ \param[out] none
+ \retval none
+*/
+void timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct* icpara)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
+
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(((uint32_t)icpara->icfilter << 4));
+
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
+
+ /* reset the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpara->icpolarity << 4);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpara->icselection << 8);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpara->icfilter << 12);
+
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ /* reset the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH2EN);
+
+ /* reset the CH2P and CH2NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpara->icpolarity << 8);
+ /* reset the CH2MS bit */
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2MS);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)(icpara->icselection);
+ /* reset the CH2CAPFLT bit */
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH2CAPFLT);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)icpara->icfilter<< 4);
+
+ /* set the CH2EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ /* reset the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH3EN);
+
+ /* reset the CH3P bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH3P));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpara->icpolarity << 12);
+ /* reset the CH3MS bit */
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3MS);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)icpara->icselection << 8);
+ /* reset the CH3CAPFLT bit */
+ TIMER_CHCTL1(timer_periph) &=(uint32_t)(~TIMER_CHCTL1_CH3CAPFLT);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)icpara->icfilter << 12);
+
+ /* set the CH3EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
+ break;
+ default:
+ break;
+ }
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph, channel,(uint32_t)icpara->icprescaler);
+}
+
+/*!
+ \brief configure TIMER channel input capture prescaler value
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[in] prescaler: channel input capture prescaler value
+ \arg TIMER_IC_PSC_DIV1: no prescaler
+ \arg TIMER_IC_PSC_DIV2: divided by 2
+ \arg TIMER_IC_PSC_DIV4: divided by 4
+ \arg TIMER_IC_PSC_DIV8: divided by 8
+ \param[out] none
+ \retval none
+*/
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint32_t prescaler)
+{
+ switch(channel){
+ /* configure TIMER_CH_0 */
+ case TIMER_CH_0:
+ TIMER_CHCTL0(timer_periph) &= (uint32_t)(~ TIMER_CHCTL0_CH0CAPPSC);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
+ break;
+ /* configure TIMER_CH_1 */
+ case TIMER_CH_1:
+ TIMER_CHCTL0(timer_periph) &= (uint32_t)(~TIMER_CHCTL0_CH1CAPPSC);
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(prescaler << 8);
+ break;
+ /* configure TIMER_CH_2 */
+ case TIMER_CH_2:
+ TIMER_CHCTL1(timer_periph) &= (uint32_t)(~TIMER_CHCTL1_CH2CAPPSC);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
+ break;
+ /* configure TIMER_CH_3 */
+ case TIMER_CH_3:
+ TIMER_CHCTL1(timer_periph) &= (uint32_t)(~TIMER_CHCTL1_CH3CAPPSC);
+ TIMER_CHCTL1(timer_periph) |= (uint32_t)(prescaler << 8);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief read TIMER channel capture compare register value
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,13,14,15,16))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,1,2))
+ \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,1,2))
+ \param[out] none
+ \retval channel capture compare register value
+*/
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
+{
+ uint32_t count_value=0U;
+
+ switch(channel){
+ case TIMER_CH_0:
+ count_value = TIMER_CH0CV(timer_periph);
+ break;
+ case TIMER_CH_1:
+ count_value = TIMER_CH1CV(timer_periph);
+ break;
+ case TIMER_CH_2:
+ count_value = TIMER_CH2CV(timer_periph);
+ break;
+ case TIMER_CH_3:
+ count_value = TIMER_CH3CV(timer_periph);
+ break;
+ default:
+ break;
+ }
+ return (count_value);
+}
+
+/*!
+ \brief configure TIMER input pwm capture function
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,1,2,14))
+ \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,1,2,14))
+ \param[in] icpwm:TIMER channel intput pwm parameter struct
+ icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
+ icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
+ icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
+ icfilter: 0~15
+ \param[out] none
+ \retval none
+*/
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
+{
+ uint16_t icpolarity = 0x0U;
+ uint16_t icselection = 0x0U;
+
+ if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
+ icpolarity = TIMER_IC_POLARITY_FALLING;
+ }else{
+ icpolarity = TIMER_IC_POLARITY_RISING;
+ }
+
+ if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
+ icselection = TIMER_IC_SELECTION_INDIRECTTI;
+ }else{
+ icselection = TIMER_IC_SELECTION_DIRECTTI;
+ }
+
+ if(TIMER_CH_0 == channel){
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ /* set the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
+ /* set the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
+ /* set the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icfilter);
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint32_t)icpwm->icprescaler);
+
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
+ /* reset the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ /* set the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
+ /* set the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
+ /* set the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpwm->icfilter << 8);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint32_t)icpwm->icprescaler);
+ }else{
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
+ /* reset the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ /* set the CH1P and CH1NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpwm->icpolarity << 4);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
+ /* set the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpwm->icselection << 8);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
+ /* set the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icpwm->icfilter << 8);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint32_t)icpwm->icprescaler);
+
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ /* set the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
+ /* set the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
+ /* set the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)icpwm->icfilter;
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ /* configure TIMER channel input capture prescaler value */
+ timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint32_t)icpwm->icprescaler);
+ }
+}
+
+/*!
+ \brief configure TIMER hall sensor mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] hallmode:
+ \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
+ \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
+ \param[out] none
+ \retval none
+*/
+void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode)
+{
+ if(TIMER_HALLINTERFACE_ENABLE == hallmode){
+ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
+ }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
+ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
+ }else{
+ }
+}
+
+/*!
+ \brief select TIMER input trigger source
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] intrigger:
+ \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
+ \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
+ \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
+ \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
+ \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
+ \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
+ \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
+ \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger
+ \param[out] none
+ \retval none
+*/
+void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)
+{
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_TRGS);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
+}
+
+/*!
+ \brief select TIMER master mode output trigger source
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] outrigger:
+ \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output
+ \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output
+ \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output
+ \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO
+ \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output
+ \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output
+ \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output
+ \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output
+ \param[out] none
+ \retval none
+*/
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
+{
+ TIMER_CTL1(timer_periph) &=(uint32_t)(~TIMER_CTL1_MMC);
+ TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
+}
+
+/*!
+ \brief select TIMER slave mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] slavemode:
+ \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
+ \arg TIMER_ENCODER_MODE0: encoder mode 0
+ \arg TIMER_ENCODER_MODE1: encoder mode 1
+ \arg TIMER_ENCODER_MODE2: encoder mode 2
+ \arg TIMER_SLAVE_MODE_RESTART: restart mode
+ \arg TIMER_SLAVE_MODE_PAUSE: pause mode
+ \arg TIMER_SLAVE_MODE_EVENT: event mode
+ \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.
+ \param[out] none
+ \retval none
+*/
+
+void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)
+{
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
+
+ TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
+}
+
+/*!
+ \brief configure TIMER master slave mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] masterslave:
+ \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
+ \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
+ \param[out] none
+ \retval none
+*/
+void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave)
+{
+ if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
+ }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
+ }else{
+ }
+}
+
+/*!
+ \brief configure TIMER external trigger input
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] extprescaler:
+ \arg TIMER_EXT_TRI_PSC_OFF: no divided
+ \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
+ \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
+ \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
+ \param[in] expolarity:
+ \arg TIMER_ETP_FALLING: active low or falling edge active
+ \arg TIMER_ETP_RISING: active high or rising edge active
+ \param[in] extfilter: a value between 0x00 and 0x0F
+ \param[out] none
+ \retval none
+*/
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
+{
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC));
+ TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << (uint16_t)8);
+}
+
+/*!
+ \brief configure TIMER quadrature decoder mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] decomode:
+ \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
+ \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
+ \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
+ \param[in] ic0polarity:
+ \arg TIMER_IC_POLARITY_RISING: capture rising edge
+ \arg TIMER_IC_POLARITY_FALLING: capture falling edge
+ \param[in] ic1polarity:
+ \arg TIMER_IC_POLARITY_RISING: capture rising edge
+ \arg TIMER_IC_POLARITY_FALLING: capture falling edge
+ \param[out] none
+ \retval none
+*/
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
+{
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
+ TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
+
+ TIMER_CHCTL0(timer_periph) &= (uint32_t)(((uint32_t)(~TIMER_CHCTL0_CH0MS))&((uint32_t)(~TIMER_CHCTL0_CH1MS)));
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8));
+
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)(ic0polarity|((uint32_t)ic1polarity << 4U));
+}
+
+/*!
+ \brief configure TIMER internal clock mode
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[out] none
+ \retval none
+*/
+void timer_internal_clock_config(uint32_t timer_periph)
+{
+ TIMER_SMCFG(timer_periph) &= (uint32_t)TIMER_SLAVE_MODE_DISABLE;
+}
+
+/*!
+ \brief configure TIMER the internal trigger as external clock input
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] intrigger:
+ \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
+ \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
+ \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
+ \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
+ \param[out] none
+ \retval none
+*/
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
+{
+ timer_input_trigger_source_select(timer_periph, intrigger);
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+ \brief configure TIMER the external trigger as external clock input
+ \param[in] timer_periph: TIMERx(x=0,1,2,14)
+ \param[in] extrigger:
+ \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
+ \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
+ \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
+ \param[in] expolarity:
+ \arg TIMER_IC_POLARITY_RISING: active low or falling edge active
+ \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter)
+{
+ if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
+ /* reset the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH1EN);
+ /* reset the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP));
+ /* set the CH1NP bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U);
+ /* reset the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1MS);
+ /* set the CH1MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
+ /* reset the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH1CAPFLT);
+ /* set the CH1CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U);
+ /* set the CH1EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
+ }else{
+ /* reset the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~TIMER_CHCTL2_CH0EN);
+ /* reset the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) &=(uint32_t)(~(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP));
+ /* set the CH0P and CH0NP bits */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity;
+ /* reset the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0MS);
+ /* set the CH0MS bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) &=(uint32_t)(~TIMER_CHCTL0_CH0CAPFLT);
+ /* reset the CH0CAPFLT bit */
+ TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter;
+ /* set the CH0EN bit */
+ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
+ }
+ /* select TIMER input trigger source */
+ timer_input_trigger_source_select(timer_periph, extrigger);
+ /* reset the SMC bit */
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
+ /* set the SMC bit */
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+}
+
+/*!
+ \brief configure TIMER the external clock mode0
+ \param[in] timer_periph: TIMERx(x=0,1,2)
+ \param[in] extprescaler:
+ \arg TIMER_EXT_TRI_PSC_OFF: no divided
+ \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
+ \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
+ \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
+ \param[in] expolarity:
+ \arg TIMER_ETP_FALLING: active low or falling edge active
+ \arg TIMER_ETP_RISING: active high or rising edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter)
+{
+ /* configure TIMER external trigger input */
+ timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
+
+ /* reset the SMC bit */
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_SMC);
+ /* set the SMC bit */
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
+
+ /* reset the TRGS bit */
+ TIMER_SMCFG(timer_periph) &=(uint32_t)(~TIMER_SMCFG_TRGS);
+ /* set the TRGS bit */
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_TRGSEL_ETIFP;
+}
+
+/*!
+ \brief configure TIMER the external clock mode1
+ \param[in] timer_periph: TIMERx(x=0,1,2)
+ \param[in] extprescaler:
+ \arg TIMER_EXT_TRI_PSC_OFF: no divided
+ \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
+ \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
+ \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
+ \param[in] expolarity:
+ \arg TIMER_ETP_FALLING: active low or falling edge active
+ \arg TIMER_ETP_RISING: active high or rising edge active
+ \param[in] extfilter: a value between 0 and 15
+ \param[out] none
+ \retval none
+*/
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
+ uint32_t expolarity, uint32_t extfilter)
+{
+ /* configure TIMER external trigger input */
+ timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter);
+
+ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+ \brief disable TIMER the external clock mode1
+ \param[in] timer_periph: TIMERx(x=0..4,7)
+ \param[out] none
+ \retval none
+*/
+void timer_external_clock_mode1_disable(uint32_t timer_periph)
+{
+ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
+}
+
+/*!
+ \brief configure TIMER13 channel0 remap function
+ \param[in] timer_periph: TIMERx(x=13)
+ \param[in] channel:
+ \arg TIMER_CH_0: TIMER channel0(TIMERx(x=13))
+ \param[in] remap:
+ \arg TIMER_IRMP_CI0_RMP_GPIO: channel 0 input is connected to GPIO
+ \arg TIMER_IRMP_CI0_RTCCLK: channel 0 input is connected to the RTCCLK
+ \arg TIMER_IRMP_CI0_HXTALDIV32: channel 0 input is connected to HXTAL/32 clock
+ \arg TIMER_IRMP_CI0_CKOUTSEL: channel 0 input is connected to CKOUTSEL
+ \param[out] none
+ \retval none
+*/
+void timer_channel_remap_config(uint32_t timer_periph, uint16_t channel, uint32_t remap)
+{
+ if(TIMER_CH_0 == channel){
+ TIMER_IRMP(timer_periph) = (uint32_t)remap;
+ }
+}
+
+#ifdef GD32F170_190
+
+/*!
+ \brief configure TIMER cc register selection
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] ccsel:
+ \arg TIMER_CHVSEL_DISABLE: write CHxVAL register selection disable
+ \arg TIMER_CHVSEL_ENABLE: write CHxVAL register selection enable
+ \param[out] none
+ \retval none
+*/
+void timer_write_cc_register_config(uint32_t timer_periph, uint32_t ccsel)
+{
+ if(ccsel){
+ TIMER_CFG(timer_periph) |= (uint32_t)ccsel;
+ }else{
+ TIMER_CFG(timer_periph) &= (uint32_t)ccsel;
+ }
+}
+
+/*!
+ \brief configure TIMER output value selection
+ \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
+ \param[in] outsel:
+ \arg TIMER_OUTSEL_DISABLE: output value selection disable
+ \arg TIMER_OUTSEL_ENABLE: output value selection enable
+ \param[out] none
+ \retval none
+*/
+void timer_output_value_selection_config(uint32_t timer_periph, uint32_t outsel)
+{
+ if(outsel){
+ TIMER_CFG(timer_periph) |= (uint32_t)outsel;
+ }else{
+ TIMER_CFG(timer_periph) &= (uint32_t)outsel;
+ }
+}
+
+#endif /* GD32F170_190 */
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_usart.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_usart.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_usart.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_usart.c
index f4e1ef59..08410fde 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_usart.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_usart.c
@@ -1,1162 +1,1162 @@
-/*!
- \file gd32f1x0_usart.c
- \brief USART driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.1, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_usart.h"
-#include "gd32f1x0_rcu.h"
-
-/*!
- \brief reset USART
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_deinit(uint32_t usart_periph)
-{
- switch(usart_periph){
- case USART0:
- rcu_periph_reset_enable(RCU_USART0RST);
- rcu_periph_reset_disable(RCU_USART0RST);
- break;
- case USART1:
- rcu_periph_reset_enable(RCU_USART1RST);
- rcu_periph_reset_disable(RCU_USART1RST);
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief configure USART baud rate value
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] baudval: baud rate value
- \param[out] none
- \retval none
-*/
-void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
-{
- uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
- switch(usart_periph){
- case USART0:
- uclk = rcu_clock_freq_get(CK_USART);
- break;
- case USART1:
- uclk = rcu_clock_freq_get(CK_APB1);
- break;
- default:
- break;
- }
- if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
- /* when oversampling by 8,configure the value of USART_BAUD */
- udiv = ((2U*uclk)+baudval/2U)/baudval;
- intdiv = udiv & 0xfff0U;
- fradiv = (udiv>>1U) & 0x7U;
- USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
- }else{
- /* when oversampling by 16,configure the value of USART_BAUD */
- udiv = (uclk+baudval/2U)/baudval;
- intdiv = udiv & 0xfff0U;
- fradiv = udiv & 0xfU;
- USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
- }
-}
-
-/*!
- \brief configure USART parity
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] paritycfg: USART parity configure
- \arg USART_PM_NONE: no parity
- \arg USART_PM_ODD: odd parity
- \arg USART_PM_EVEN: even parity
- \param[out] none
- \retval none
-*/
-void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* clear USART_CTL0 PM,PCEN bits */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
- /* configure USART parity mode */
- USART_CTL0(usart_periph) |= paritycfg;
-}
-
-/*!
- \brief configure USART word length
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] wlen: USART word length configure
- \arg USART_WL_8BIT: 8 bits
- \arg USART_WL_9BIT: 9 bits
- \param[out] none
- \retval none
-*/
-void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* clear USART_CTL0 WL bit */
- USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
- /* configure USART word length */
- USART_CTL0(usart_periph) |= wlen;
-}
-
-/*!
- \brief configure USART stop bit length
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] stblen: USART stop bit configure
- \arg USART_STB_1BIT: 1 bit
- \arg USART_STB_2BIT: 2 bits
- \arg USART_STB_1_5BIT: 1.5bit
- \param[out] none
- \retval none
-*/
-void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* clear USART_CTL1 STB bits */
- USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
- USART_CTL1(usart_periph) |= stblen;
-}
-
-/*!
- \brief enable USART
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_enable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) |= USART_CTL0_UEN;
-}
-
-/*!
- \brief disable USART
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_disable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-}
-
-/*!
- \brief configure USART transmitter
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] txconfig: enable or disable USART transmitter
- \arg USART_TRANSMIT_ENABLE: enable USART transmission
- \arg USART_TRANSMIT_DISABLE: enable USART transmission
- \param[out] none
- \retval none
-*/
-void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
-{
- USART_CTL0(usart_periph) &= ~USART_CTL0_TEN;
- /* configure transfer mode */
- USART_CTL0(usart_periph) |= txconfig;
-}
-
-/*!
- \brief configure USART receiver
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] rxconfig: enable or disable USART receiver
- \arg USART_RECEIVE_ENABLE: enable USART reception
- \arg USART_RECEIVE_DISABLE: disable USART reception
- \param[out] none
- \retval none
-*/
-void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
-{
- USART_CTL0(usart_periph) &= ~USART_CTL0_REN;
- /* configure receiver mode */
- USART_CTL0(usart_periph) |= rxconfig;
-}
-
-/*!
- \brief USART transmit data function
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] data: data of transmission
- \param[out] none
- \retval none
-*/
-void usart_data_transmit(uint32_t usart_periph, uint32_t data)
-{
- USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data);
-}
-
-/*!
- \brief USART receive data function
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval data of received
-*/
-uint16_t usart_data_receive(uint32_t usart_periph)
-{
- return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U));
-}
-
-/*!
- \brief data is transmitted/received with the LSB/MSB first
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] msbf: LSB/MSB
- \arg USART_MSBF_LSB: LSB first
- \arg USART_MSBF_MSB: MSB first
- \param[out] none
- \retval none
-*/
-void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* configure LSB or MSB first */
- USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF);
- USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf) ;
-}
-
-/*!
- \brief USART inverted configure
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] invertpara: refer to usart_invert_enum
- \param[out] none
- \retval none
-*/
-void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* inverted or not the specified signal */
- switch(invertpara){
- case USART_DINV_ENABLE:
- USART_CTL1(usart_periph) |= USART_CTL1_DINV;
- break;
- case USART_DINV_DISABLE:
- USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV);
- break;
- case USART_TXPIN_DISABLE:
- USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV);
- break;
- case USART_RXPIN_DISABLE:
- USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV);
- break;
- case USART_SWAP_DISABLE:
- USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP);
- break;
- case USART_TXPIN_ENABLE:
- USART_CTL1(usart_periph) |= USART_CTL1_TINV;
- break;
- case USART_RXPIN_ENABLE:
- USART_CTL1(usart_periph) |= USART_CTL1_RINV;
- break;
- case USART_SWAP_ENABLE:
- USART_CTL1(usart_periph) |= USART_CTL1_STRP;
- break;
- default:
- break;
- }
-}
-
-/*!
- \brief overrun function is enabled
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_overrun_enable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD);
-}
-
-/*!
- \brief overrun function is disabled
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_overrun_disable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL2(usart_periph) |= USART_CTL2_OVRD;
-}
-
-/*!
- \brief configure the USART oversample mode
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] oversamp: oversample value
- \arg USART_OVSMOD_8: oversampling by 8
- \arg USART_OVSMOD_16: oversampling by 16
- \param[out] none
- \retval none
-*/
-void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* clear OVSMOD bit */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD);
- USART_CTL0(usart_periph) |= oversamp;
-}
-
-/*!
- \brief sample bit method configure
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] osb: sample bit
- \arg USART_OSB_1BIT: 1 bit
- \arg USART_OSB_3BIT: 3 bits
- \param[out] none
- \retval none
-*/
-void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB);
- USART_CTL2(usart_periph) |= (osb);
-}
-
-/*!
- \brief auto baud rate detection enable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_autobaud_detection_enable(uint32_t usart_periph)
-{
- USART_CTL1(usart_periph) |= USART_CTL1_ABDEN;
-}
-
-/*!
- \brief auto baud rate detection disable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_autobaud_detection_disable(uint32_t usart_periph)
-{
- USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN);
-}
-
-/*!
- \brief auto baud rate detection mode configure
- \param[in] usart_periph: USARTx(x=0)
- \param[in] abdmod: auto baud rate detection mode
- \arg USART_ABDM_FTOR: falling edge to rising edge measurement
- \arg USART_ABDM_FTOF: falling edge to falling edge measurement
- \param[out] none
- \retval none
-*/
-void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod)
-{
- /* reset ABDM bits */
- USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM);
- USART_CTL1(usart_periph) |= (abdmod);
-}
-
-/*!
- \brief mute mode enable
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_mute_mode_enable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) |= USART_CTL0_MEN;
-}
-
-/*!
- \brief mute mode disable
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_mute_mode_disable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN);
-}
-
-/*!
- \brief wakeup method in mute mode configure
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] wmethod: two methods be used to enter or exit the mute mode
- \arg USART_WM_IDLE: idle line
- \arg USART_WM_ADDR: address mark
- \param[out] none
- \retval none
-*/
-void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
- USART_CTL0(usart_periph) |= wmethod;
-}
-
-/*!
- \brief address detection mode configure
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] addmod: address detection mode
- \arg USART_ADDM_4BIT: 4 bits
- \arg USART_ADDM_FULLBIT: full bits
- \param[out] none
- \retval none
-*/
-void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM);
- USART_CTL1(usart_periph) |= (USART_CTL1_ADDM & (addmod));
-}
-
-/*!
- \brief address of the USART terminal
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] addr: 0x00-0xFF, address of USART terminal
- \param[out] none
- \retval none
-*/
-void usart_address_config(uint32_t usart_periph, uint8_t addr)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
- USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24));
-}
-
-/*!
- \brief receiver timeout enable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_receiver_timeout_enable(uint32_t usart_periph)
-{
- USART_CTL1(usart_periph) |= USART_CTL1_RTEN;
-}
-
-/*!
- \brief receiver timeout disable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_receiver_timeout_disable(uint32_t usart_periph)
-{
- USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN);
-}
-
-/*!
- \brief receiver timeout threshold configure
- \param[in] usart_periph: USARTx(x=0)
- \param[in] rtimeout: 0x000000-0xFFFFFF, receiver timeout value in terms of number of baud clocks
- \param[out] none
- \retval none
-*/
-void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout)
-{
- USART_RT(usart_periph) &= ~(USART_RT_RT);
- USART_RT(usart_periph) |= (rtimeout);
-}
-
-/*!
- \brief LIN mode enable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_lin_mode_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
-}
-
-/*!
- \brief LIN mode disable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_lin_mode_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
-}
-
-/*!
- \brief LIN break detection length
- \param[in] usart_periph: USARTx(x=0)
- \param[in] lblen: LIN break detection length
- \arg USART_LBLEN_10B: 10 bits break detection
- \arg USART_LBLEN_11B: 11 bits break detection
- \param[out] none
- \retval none
-*/
-void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & (lblen));
-}
-
-/*!
- \brief half-duplex enable
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_halfduplex_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
-}
-
-/*!
- \brief half-duplex disable
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_halfduplex_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
-}
-
-/*!
- \brief clock enable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_clock_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
-}
-
-/*!
- \brief clock disable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_clock_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
-}
-
-/*!
- \brief configure USART synchronous mode parameters
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] clen: last bit clock pulse
- \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin
- \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin
- \param[in] cph: clock phase
- \arg USART_CPH_1CK: first clock transition is the first data capture edge
- \arg USART_CPH_2CK: second clock transition is the first data capture edge
- \param[in] cpl: clock polarity
- \arg USART_CPL_LOW: steady low value on CK pin
- \arg USART_CPL_HIGH: steady high value on CK pin
- \param[out] none
- \retval none
-*/
-void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* reset USART_CTL1 CLEN,CPH,CPL bits */
- USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
-
- USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen);
- USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph);
- USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl);
-}
-
-/*!
- \brief smartcard mode enable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_smartcard_mode_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
-}
-
-/*!
- \brief smartcard mode disable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_smartcard_mode_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
-}
-
-/*!
- \brief NACK enable in smartcard mode
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
-}
-
-/*!
- \brief NACK disable in smartcard mode
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
-}
-
-/*!
- \brief guard time value configure in smartcard mode
- \param[in] usart_periph: USARTx(x=0)
- \param[in] guat: 0x00-0xFF
- \param[out] none
- \retval none
-*/
-void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_GP(usart_periph) &= ~(USART_GP_GUAT);
- USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
-}
-
-/*!
- \brief block length configure
- \param[in] usart_periph: USARTx(x=0)
- \param[in] bl: 0x00-0xFF
- \param[out] none
- \retval none
-*/
-void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
-{
- USART_RT(usart_periph) &= ~(USART_RT_BL);
- USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
-}
-
-/*!
- \brief smartcard auto-retry number configure
- \param[in] usart_periph: USARTx(x=0)
- \param[in] scrtnum: 0x0-0x7, smartcard auto-retry number
- \param[out] none
- \retval none
-*/
-void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM);
- USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & ((scrtnum) << 17));
-}
-
-/*!
- \brief IrDA mode enable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_irda_mode_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) |= USART_CTL2_IREN;
-}
-
-/*!
- \brief IrDA mode disable
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_irda_mode_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
-}
-
-/*!
- \brief IrDA low-power configure
- \param[in] usart_periph: USARTx(x=0)
- \param[in] irlp: IrDA low-power or normal
- \arg USART_IRLP_LOW: low-power
- \arg USART_IRLP_NORMAL: normal
- \param[out] none
- \retval none
-*/
-void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
-}
-
-/*!
- \brief configure the peripheral clock prescaler in USART IrDA low-power mode or in USART SmartCard mode
- \param[in] usart_periph: USARTx(x=0)
- \param[in] psc: 0x00-0xFF
- \param[out] none
- \retval none
-*/
-void usart_prescaler_config(uint32_t usart_periph, uint32_t psc)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_GP(usart_periph) &= ~(USART_GP_PSC);
- USART_GP(usart_periph) |= psc;
-}
-
-/*!
- \brief configure hardware flow control RTS
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] rtsconfig: enable or disable RTS
- \arg USART_RTS_ENABLE: enable RTS
- \arg USART_RTS_DISABLE: disable RTS
- \param[out] none
- \retval none
-*/
-void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
- USART_CTL2(usart_periph) |= rtsconfig;
-}
-
-/*!
- \brief configure hardware flow control CTS
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] ctsconfig: enable or disable CTS
- \arg USART_CTS_ENABLE: enable CTS
- \arg USART_CTS_DISABLE: disable CTS
- \param[out] none
- \retval none
-*/
-void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN;
- USART_CTL2(usart_periph) |= ctsconfig;
-}
-
-/*!
- \brief RS485 driver enable
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_rs485_driver_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) |= USART_CTL2_DEM;
-}
-
-/*!
- \brief RS485 driver disable
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_rs485_driver_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM);
-}
-
-/*!
- \brief driver enable assertion time configure
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] deatime: 0x00-0x1F
- \param[out] none
- \retval none
-*/
-void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA);
- USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21));
-}
-
-/*!
- \brief driver enable de-assertion time configure
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] dedtime: 0x00-0x1F
- \param[out] none
- \retval none
-*/
-void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
-
- USART_CTL0(usart_periph) &= ~(USART_CTL0_DED);
- USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16));
-}
-
-/*!
- \brief configure driver enable polarity mode
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] dep: DE signal
- \arg USART_DEP_HIGH: DE signal is active high
- \arg USART_DEP_LOW: DE signal is active low
- \param[out] none
- \retval none
-*/
-void usart_depolarity_config(uint32_t usart_periph, uint32_t dep)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* reset DEP bit */
- USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP);
- USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep);
-}
-
-/*!
- \brief configure USART DMA reception
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] dmacmd: enable or disable DMA for reception
- \arg USART_DENR_ENABLE: DMA enable for reception
- \arg USART_DENR_DISABLE: DMA disable for reception
- \param[out] none
- \retval none
-*/
-void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
-{
- USART_CTL2(usart_periph) &= ~USART_CTL2_DENR;
- /* configure DMA reception */
- USART_CTL2(usart_periph) |= dmacmd;
-}
-
-/*!
- \brief configure USART DMA transmission
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] dmacmd: enable or disable DMA for transmission
- \arg USART_DENT_ENABLE: DMA enable for transmission
- \arg USART_DENT_DISABLE: DMA disable for transmission
- \param[out] none
- \retval none
-*/
-void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
-{
- USART_CTL2(usart_periph) &= ~USART_CTL2_DENT;
- /* configure DMA transmission */
- USART_CTL2(usart_periph) |= dmacmd;
-}
-
-/*!
- \brief disable DMA on reception error
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_reception_error_dma_disable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL2(usart_periph) |= USART_CTL2_DDRE;
-}
-
-/*!
- \brief enable DMA on reception error
- \param[in] usart_periph: USARTx(x=0,1)
- \param[out] none
- \retval none
-*/
-void usart_reception_error_dma_enable(uint32_t usart_periph)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE);
-}
-
-/*!
- \brief USART be able to wake up the MCU from deep-sleep mode
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_wakeup_enable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) |= USART_CTL0_UESM;
-}
-
-/*!
- \brief USART be not able to wake up the MCU from deep-sleep mode
- \param[in] usart_periph: USARTx(x=0)
- \param[out] none
- \retval none
-*/
-void usart_wakeup_disable(uint32_t usart_periph)
-{
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM);
-}
-
-/*!
- \brief wakeup mode from deep-sleep mode
- \param[in] usart_periph: USARTx(x=0)
- \param[in] wum: wakeup mode
- \arg USART_WUM_ADDR: WUF active on address match
- \arg USART_WUM_STARTB: WUF active on start bit
- \arg USART_WUM_RBNE: WUF active on RBNE
- \param[out] none
- \retval none
-*/
-void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum)
-{
- /* disable USART */
- USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
- /* reset WUM bit */
- USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM);
- USART_CTL2(usart_periph) |= (USART_CTL2_WUM & (wum));
-}
-
-/*!
- \brief get flag in STAT register
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] flag: flag type
- \arg USART_FLAG_PERR: parity error flag
- \arg USART_FLAG_FERR: frame error flag
- \arg USART_FLAG_NERR: noise error flag
- \arg USART_FLAG_ORERR: overrun error
- \arg USART_FLAG_IDLE: idle line detected flag
- \arg USART_FLAG_RBNE: read data buffer not empty
- \arg USART_FLAG_TC: transmission completed
- \arg USART_FLAG_TBE: transmit data register empty
- \arg USART_FLAG_LBD: LIN break detected flag
- \arg USART_FLAG_CTSF: CTS change flag
- \arg USART_FLAG_CTS: CTS level
- \arg USART_FLAG_RT: receiver timeout flag
- \arg USART_FLAG_EB: end of block flag
- \arg USART_FLAG_ABDE: auto baudrate detection error
- \arg USART_FLAG_ABD: auto baudrate detection flag
- \arg USART_FLAG_BSY: busy flag
- \arg USART_FLAG_AM: address match flag
- \arg USART_FLAG_SB: send break flag
- \arg USART_FLAG_RWU: receiver wakeup from mute mode.
- \arg USART_FLAG_WU: wakeup from deep-sleep mode flag
- \arg USART_FLAG_TEA: transmit enable acknowledge flag
- \arg USART_FLAG_REA: receive enable acknowledge flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
-{
- if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear USART status
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] flag: flag type
- \arg USART_FLAG_PERR: parity error flag
- \arg USART_FLAG_FERR: frame error flag
- \arg USART_FLAG_NERR: noise detected flag
- \arg USART_FLAG_ORERR:overrun error flag
- \arg USART_FLAG_IDLE: idle line detected flag
- \arg USART_FLAG_TC: transmission complete flag
- \arg USART_FLAG_LBD: LIN break detected flag
- \arg USART_FLAG_CTSF: CTS change flag
- \arg USART_FLAG_RT: receiver timeout flag
- \arg USART_FLAG_EB: end of block flag
- \arg USART_FLAG_AM: address match flag
- \arg USART_FLAG_WU: wakeup from deep-sleep mode flag
- \param[out] none
- \retval none
-*/
-void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
-{
- USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
-}
-
-/*!
- \brief enable USART interrupt
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] inttype: interrupt type
- \arg USART_INT_IDLE: idle interrupt
- \arg USART_INT_RBNE: read data buffer not empty interrupt and
- overrun error interrupt enable interrupt
- \arg USART_INT_TC: transmission complete interrupt
- \arg USART_INT_TBE: transmit data register empty interrupt
- \arg USART_INT_PERR: parity error interrupt
- \arg USART_INT_AM: address match interrupt
- \arg USART_INT_RT: receiver timeout interrupt
- \arg USART_INT_EB: end of block interrupt
- \arg USART_INT_LBD: LIN break detection interrupt
- \arg USART_INT_ERR: error interrupt enable in multibuffer communication
- \arg USART_INT_CTS: CTS interrupt
- \arg USART_INT_WU: wakeup from deep-sleep mode interrupt
- \param[out] none
- \retval none
-*/
-void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype)
-{
- USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype));
-}
-
-/*!
- \brief disable USART interrupt
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] inttype: interrupt type
- \arg USART_INT_IDLE: idle interrupt
- \arg USART_INT_RBNE: read data buffer not empty interrupt and
- overrun error interrupt
- \arg USART_INT_TC: transmission complete interrupt
- \arg USART_INT_TBE: transmit data register empty interrupt
- \arg USART_INT_PERR: parity error interrupt
- \arg USART_INT_AM: address match interrupt
- \arg USART_INT_RT: receiver timeout interrupt
- \arg USART_INT_EB: end of block interrupt
- \arg USART_INT_LBD: LIN break detection interrupt
- \arg USART_INT_ERR: error interrupt enable in multibuffer communication
- \arg USART_INT_CTS: CTS interrupt
- \arg USART_INT_WU: wakeup from deep-sleep mode interrupt
- \param[out] none
- \retval none
-*/
-void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype)
-{
- USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype));
-}
-
-/*!
- \brief enable USART command
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] cmdtype: command type
- \arg USART_CMD_ABDCMD: auto baudrate detection command
- \arg USART_CMD_SBKCMD: send break command
- \arg USART_CMD_MMCMD: mute mode command
- \arg USART_CMD_RXFCMD: receive data flush command
- \arg USART_CMD_TXFCMD: transmit data flush request
- \param[out] none
- \retval none
-*/
-void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype)
-{
- USART_CMD(usart_periph) |= (cmdtype);
-}
-
-/*!
- \brief get USART interrupt and flag status
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum
- \arg USART_INT_FLAG_EB: end of block interrupt and flag
- \arg USART_INT_FLAG_RT: receiver timeout interrupt and flag
- \arg USART_INT_FLAG_AM: address match interrupt and flag
- \arg USART_INT_FLAG_PERR: parity error interrupt and flag
- \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
- \arg USART_INT_FLAG_TC: transmission complete interrupt and flag
- \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
- \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
- \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
- \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag
- \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag
- \arg USART_INT_FLAG_CTS: CTS interrupt and flag
- \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
- \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
- \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
-{
- uint32_t intenable = 0U, flagstatus = 0U;
- /* get the interrupt enable bit status */
- intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
- /* get the corresponding flag bit status */
- flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
-
- if(flagstatus && intenable){
- return SET;
- }else{
- return RESET;
- }
-}
-
-/*!
- \brief clear USART interrupt flag in STAT register
- \param[in] usart_periph: USARTx(x=0,1)
- \param[in] flag: USART interrupt flag
- \arg USART_INT_FLAG_PERR: parity error flag
- \arg USART_INT_FLAG_FERR: frame error flag
- \arg USART_INT_FLAG_NERR: noise detected flag
- \arg USART_INT_FLAG_ORERR:overrun error flag
- \arg USART_INT_FLAG_IDLE: idle line detected flag
- \arg USART_INT_FLAG_TC: transmission complete flag
- \arg USART_INT_FLAG_LBD: LIN break detected flag
- \arg USART_INT_FLAG_CTS: CTS change flag
- \arg USART_INT_FLAG_RT: receiver timeout flag
- \arg USART_INT_FLAG_EB: end of block flag
- \arg USART_INT_FLAG_AM: address match flag
- \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode flag
- \param[out] none
- \retval none
-*/
-void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
-{
- USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag));
-}
+/*!
+ \file gd32f1x0_usart.c
+ \brief USART driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.1, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_rcu.h"
+
+/*!
+ \brief reset USART
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_deinit(uint32_t usart_periph)
+{
+ switch(usart_periph){
+ case USART0:
+ rcu_periph_reset_enable(RCU_USART0RST);
+ rcu_periph_reset_disable(RCU_USART0RST);
+ break;
+ case USART1:
+ rcu_periph_reset_enable(RCU_USART1RST);
+ rcu_periph_reset_disable(RCU_USART1RST);
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief configure USART baud rate value
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] baudval: baud rate value
+ \param[out] none
+ \retval none
+*/
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
+{
+ uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
+ switch(usart_periph){
+ case USART0:
+ uclk = rcu_clock_freq_get(CK_USART);
+ break;
+ case USART1:
+ uclk = rcu_clock_freq_get(CK_APB1);
+ break;
+ default:
+ break;
+ }
+ if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){
+ /* when oversampling by 8,configure the value of USART_BAUD */
+ udiv = ((2U*uclk)+baudval/2U)/baudval;
+ intdiv = udiv & 0xfff0U;
+ fradiv = (udiv>>1U) & 0x7U;
+ USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
+ }else{
+ /* when oversampling by 16,configure the value of USART_BAUD */
+ udiv = (uclk+baudval/2U)/baudval;
+ intdiv = udiv & 0xfff0U;
+ fradiv = udiv & 0xfU;
+ USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
+ }
+}
+
+/*!
+ \brief configure USART parity
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] paritycfg: USART parity configure
+ \arg USART_PM_NONE: no parity
+ \arg USART_PM_ODD: odd parity
+ \arg USART_PM_EVEN: even parity
+ \param[out] none
+ \retval none
+*/
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* clear USART_CTL0 PM,PCEN bits */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
+ /* configure USART parity mode */
+ USART_CTL0(usart_periph) |= paritycfg;
+}
+
+/*!
+ \brief configure USART word length
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] wlen: USART word length configure
+ \arg USART_WL_8BIT: 8 bits
+ \arg USART_WL_9BIT: 9 bits
+ \param[out] none
+ \retval none
+*/
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* clear USART_CTL0 WL bit */
+ USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
+ /* configure USART word length */
+ USART_CTL0(usart_periph) |= wlen;
+}
+
+/*!
+ \brief configure USART stop bit length
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] stblen: USART stop bit configure
+ \arg USART_STB_1BIT: 1 bit
+ \arg USART_STB_2BIT: 2 bits
+ \arg USART_STB_1_5BIT: 1.5bit
+ \param[out] none
+ \retval none
+*/
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* clear USART_CTL1 STB bits */
+ USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
+ USART_CTL1(usart_periph) |= stblen;
+}
+
+/*!
+ \brief enable USART
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_enable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) |= USART_CTL0_UEN;
+}
+
+/*!
+ \brief disable USART
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_disable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+}
+
+/*!
+ \brief configure USART transmitter
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] txconfig: enable or disable USART transmitter
+ \arg USART_TRANSMIT_ENABLE: enable USART transmission
+ \arg USART_TRANSMIT_DISABLE: enable USART transmission
+ \param[out] none
+ \retval none
+*/
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
+{
+ USART_CTL0(usart_periph) &= ~USART_CTL0_TEN;
+ /* configure transfer mode */
+ USART_CTL0(usart_periph) |= txconfig;
+}
+
+/*!
+ \brief configure USART receiver
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] rxconfig: enable or disable USART receiver
+ \arg USART_RECEIVE_ENABLE: enable USART reception
+ \arg USART_RECEIVE_DISABLE: disable USART reception
+ \param[out] none
+ \retval none
+*/
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
+{
+ USART_CTL0(usart_periph) &= ~USART_CTL0_REN;
+ /* configure receiver mode */
+ USART_CTL0(usart_periph) |= rxconfig;
+}
+
+/*!
+ \brief USART transmit data function
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] data: data of transmission
+ \param[out] none
+ \retval none
+*/
+void usart_data_transmit(uint32_t usart_periph, uint32_t data)
+{
+ USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data);
+}
+
+/*!
+ \brief USART receive data function
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval data of received
+*/
+uint16_t usart_data_receive(uint32_t usart_periph)
+{
+ return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U));
+}
+
+/*!
+ \brief data is transmitted/received with the LSB/MSB first
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] msbf: LSB/MSB
+ \arg USART_MSBF_LSB: LSB first
+ \arg USART_MSBF_MSB: MSB first
+ \param[out] none
+ \retval none
+*/
+void usart_data_first_config(uint32_t usart_periph, uint32_t msbf)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* configure LSB or MSB first */
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF);
+ USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf) ;
+}
+
+/*!
+ \brief USART inverted configure
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] invertpara: refer to usart_invert_enum
+ \param[out] none
+ \retval none
+*/
+void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* inverted or not the specified signal */
+ switch(invertpara){
+ case USART_DINV_ENABLE:
+ USART_CTL1(usart_periph) |= USART_CTL1_DINV;
+ break;
+ case USART_DINV_DISABLE:
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV);
+ break;
+ case USART_TXPIN_DISABLE:
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV);
+ break;
+ case USART_RXPIN_DISABLE:
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV);
+ break;
+ case USART_SWAP_DISABLE:
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP);
+ break;
+ case USART_TXPIN_ENABLE:
+ USART_CTL1(usart_periph) |= USART_CTL1_TINV;
+ break;
+ case USART_RXPIN_ENABLE:
+ USART_CTL1(usart_periph) |= USART_CTL1_RINV;
+ break;
+ case USART_SWAP_ENABLE:
+ USART_CTL1(usart_periph) |= USART_CTL1_STRP;
+ break;
+ default:
+ break;
+ }
+}
+
+/*!
+ \brief overrun function is enabled
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_overrun_enable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD);
+}
+
+/*!
+ \brief overrun function is disabled
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_overrun_disable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL2(usart_periph) |= USART_CTL2_OVRD;
+}
+
+/*!
+ \brief configure the USART oversample mode
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] oversamp: oversample value
+ \arg USART_OVSMOD_8: oversampling by 8
+ \arg USART_OVSMOD_16: oversampling by 16
+ \param[out] none
+ \retval none
+*/
+void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* clear OVSMOD bit */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD);
+ USART_CTL0(usart_periph) |= oversamp;
+}
+
+/*!
+ \brief sample bit method configure
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] osb: sample bit
+ \arg USART_OSB_1BIT: 1 bit
+ \arg USART_OSB_3BIT: 3 bits
+ \param[out] none
+ \retval none
+*/
+void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB);
+ USART_CTL2(usart_periph) |= (osb);
+}
+
+/*!
+ \brief auto baud rate detection enable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_autobaud_detection_enable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) |= USART_CTL1_ABDEN;
+}
+
+/*!
+ \brief auto baud rate detection disable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_autobaud_detection_disable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN);
+}
+
+/*!
+ \brief auto baud rate detection mode configure
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] abdmod: auto baud rate detection mode
+ \arg USART_ABDM_FTOR: falling edge to rising edge measurement
+ \arg USART_ABDM_FTOF: falling edge to falling edge measurement
+ \param[out] none
+ \retval none
+*/
+void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod)
+{
+ /* reset ABDM bits */
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM);
+ USART_CTL1(usart_periph) |= (abdmod);
+}
+
+/*!
+ \brief mute mode enable
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_mute_mode_enable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) |= USART_CTL0_MEN;
+}
+
+/*!
+ \brief mute mode disable
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_mute_mode_disable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN);
+}
+
+/*!
+ \brief wakeup method in mute mode configure
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] wmethod: two methods be used to enter or exit the mute mode
+ \arg USART_WM_IDLE: idle line
+ \arg USART_WM_ADDR: address mark
+ \param[out] none
+ \retval none
+*/
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
+ USART_CTL0(usart_periph) |= wmethod;
+}
+
+/*!
+ \brief address detection mode configure
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] addmod: address detection mode
+ \arg USART_ADDM_4BIT: 4 bits
+ \arg USART_ADDM_FULLBIT: full bits
+ \param[out] none
+ \retval none
+*/
+void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM);
+ USART_CTL1(usart_periph) |= (USART_CTL1_ADDM & (addmod));
+}
+
+/*!
+ \brief address of the USART terminal
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] addr: 0x00-0xFF, address of USART terminal
+ \param[out] none
+ \retval none
+*/
+void usart_address_config(uint32_t usart_periph, uint8_t addr)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
+ USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24));
+}
+
+/*!
+ \brief receiver timeout enable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_receiver_timeout_enable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) |= USART_CTL1_RTEN;
+}
+
+/*!
+ \brief receiver timeout disable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_receiver_timeout_disable(uint32_t usart_periph)
+{
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN);
+}
+
+/*!
+ \brief receiver timeout threshold configure
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] rtimeout: 0x000000-0xFFFFFF, receiver timeout value in terms of number of baud clocks
+ \param[out] none
+ \retval none
+*/
+void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout)
+{
+ USART_RT(usart_periph) &= ~(USART_RT_RT);
+ USART_RT(usart_periph) |= (rtimeout);
+}
+
+/*!
+ \brief LIN mode enable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_lin_mode_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
+}
+
+/*!
+ \brief LIN mode disable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_lin_mode_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
+}
+
+/*!
+ \brief LIN break detection length
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] lblen: LIN break detection length
+ \arg USART_LBLEN_10B: 10 bits break detection
+ \arg USART_LBLEN_11B: 11 bits break detection
+ \param[out] none
+ \retval none
+*/
+void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & (lblen));
+}
+
+/*!
+ \brief half-duplex enable
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_halfduplex_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
+}
+
+/*!
+ \brief half-duplex disable
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_halfduplex_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
+}
+
+/*!
+ \brief clock enable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_clock_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
+}
+
+/*!
+ \brief clock disable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_clock_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
+}
+
+/*!
+ \brief configure USART synchronous mode parameters
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] clen: last bit clock pulse
+ \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin
+ \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin
+ \param[in] cph: clock phase
+ \arg USART_CPH_1CK: first clock transition is the first data capture edge
+ \arg USART_CPH_2CK: second clock transition is the first data capture edge
+ \param[in] cpl: clock polarity
+ \arg USART_CPL_LOW: steady low value on CK pin
+ \arg USART_CPL_HIGH: steady high value on CK pin
+ \param[out] none
+ \retval none
+*/
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* reset USART_CTL1 CLEN,CPH,CPL bits */
+ USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
+
+ USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen);
+ USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph);
+ USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl);
+}
+
+/*!
+ \brief smartcard mode enable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
+}
+
+/*!
+ \brief smartcard mode disable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
+}
+
+/*!
+ \brief NACK enable in smartcard mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
+}
+
+/*!
+ \brief NACK disable in smartcard mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
+}
+
+/*!
+ \brief guard time value configure in smartcard mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] guat: 0x00-0xFF
+ \param[out] none
+ \retval none
+*/
+void usart_guard_time_config(uint32_t usart_periph, uint32_t guat)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_GP(usart_periph) &= ~(USART_GP_GUAT);
+ USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8));
+}
+
+/*!
+ \brief block length configure
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] bl: 0x00-0xFF
+ \param[out] none
+ \retval none
+*/
+void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
+{
+ USART_RT(usart_periph) &= ~(USART_RT_BL);
+ USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24));
+}
+
+/*!
+ \brief smartcard auto-retry number configure
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] scrtnum: 0x0-0x7, smartcard auto-retry number
+ \param[out] none
+ \retval none
+*/
+void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM);
+ USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & ((scrtnum) << 17));
+}
+
+/*!
+ \brief IrDA mode enable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_irda_mode_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) |= USART_CTL2_IREN;
+}
+
+/*!
+ \brief IrDA mode disable
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_irda_mode_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
+}
+
+/*!
+ \brief IrDA low-power configure
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] irlp: IrDA low-power or normal
+ \arg USART_IRLP_LOW: low-power
+ \arg USART_IRLP_NORMAL: normal
+ \param[out] none
+ \retval none
+*/
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
+}
+
+/*!
+ \brief configure the peripheral clock prescaler in USART IrDA low-power mode or in USART SmartCard mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] psc: 0x00-0xFF
+ \param[out] none
+ \retval none
+*/
+void usart_prescaler_config(uint32_t usart_periph, uint32_t psc)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_GP(usart_periph) &= ~(USART_GP_PSC);
+ USART_GP(usart_periph) |= psc;
+}
+
+/*!
+ \brief configure hardware flow control RTS
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] rtsconfig: enable or disable RTS
+ \arg USART_RTS_ENABLE: enable RTS
+ \arg USART_RTS_DISABLE: disable RTS
+ \param[out] none
+ \retval none
+*/
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
+ USART_CTL2(usart_periph) |= rtsconfig;
+}
+
+/*!
+ \brief configure hardware flow control CTS
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] ctsconfig: enable or disable CTS
+ \arg USART_CTS_ENABLE: enable CTS
+ \arg USART_CTS_DISABLE: disable CTS
+ \param[out] none
+ \retval none
+*/
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN;
+ USART_CTL2(usart_periph) |= ctsconfig;
+}
+
+/*!
+ \brief RS485 driver enable
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_rs485_driver_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) |= USART_CTL2_DEM;
+}
+
+/*!
+ \brief RS485 driver disable
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_rs485_driver_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM);
+}
+
+/*!
+ \brief driver enable assertion time configure
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] deatime: 0x00-0x1F
+ \param[out] none
+ \retval none
+*/
+void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA);
+ USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21));
+}
+
+/*!
+ \brief driver enable de-assertion time configure
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] dedtime: 0x00-0x1F
+ \param[out] none
+ \retval none
+*/
+void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_DED);
+ USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16));
+}
+
+/*!
+ \brief configure driver enable polarity mode
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] dep: DE signal
+ \arg USART_DEP_HIGH: DE signal is active high
+ \arg USART_DEP_LOW: DE signal is active low
+ \param[out] none
+ \retval none
+*/
+void usart_depolarity_config(uint32_t usart_periph, uint32_t dep)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* reset DEP bit */
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP);
+ USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep);
+}
+
+/*!
+ \brief configure USART DMA reception
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] dmacmd: enable or disable DMA for reception
+ \arg USART_DENR_ENABLE: DMA enable for reception
+ \arg USART_DENR_DISABLE: DMA disable for reception
+ \param[out] none
+ \retval none
+*/
+void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
+{
+ USART_CTL2(usart_periph) &= ~USART_CTL2_DENR;
+ /* configure DMA reception */
+ USART_CTL2(usart_periph) |= dmacmd;
+}
+
+/*!
+ \brief configure USART DMA transmission
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] dmacmd: enable or disable DMA for transmission
+ \arg USART_DENT_ENABLE: DMA enable for transmission
+ \arg USART_DENT_DISABLE: DMA disable for transmission
+ \param[out] none
+ \retval none
+*/
+void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
+{
+ USART_CTL2(usart_periph) &= ~USART_CTL2_DENT;
+ /* configure DMA transmission */
+ USART_CTL2(usart_periph) |= dmacmd;
+}
+
+/*!
+ \brief disable DMA on reception error
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_reception_error_dma_disable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL2(usart_periph) |= USART_CTL2_DDRE;
+}
+
+/*!
+ \brief enable DMA on reception error
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[out] none
+ \retval none
+*/
+void usart_reception_error_dma_enable(uint32_t usart_periph)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE);
+}
+
+/*!
+ \brief USART be able to wake up the MCU from deep-sleep mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_wakeup_enable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) |= USART_CTL0_UESM;
+}
+
+/*!
+ \brief USART be not able to wake up the MCU from deep-sleep mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[out] none
+ \retval none
+*/
+void usart_wakeup_disable(uint32_t usart_periph)
+{
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM);
+}
+
+/*!
+ \brief wakeup mode from deep-sleep mode
+ \param[in] usart_periph: USARTx(x=0)
+ \param[in] wum: wakeup mode
+ \arg USART_WUM_ADDR: WUF active on address match
+ \arg USART_WUM_STARTB: WUF active on start bit
+ \arg USART_WUM_RBNE: WUF active on RBNE
+ \param[out] none
+ \retval none
+*/
+void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum)
+{
+ /* disable USART */
+ USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
+ /* reset WUM bit */
+ USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM);
+ USART_CTL2(usart_periph) |= (USART_CTL2_WUM & (wum));
+}
+
+/*!
+ \brief get flag in STAT register
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] flag: flag type
+ \arg USART_FLAG_PERR: parity error flag
+ \arg USART_FLAG_FERR: frame error flag
+ \arg USART_FLAG_NERR: noise error flag
+ \arg USART_FLAG_ORERR: overrun error
+ \arg USART_FLAG_IDLE: idle line detected flag
+ \arg USART_FLAG_RBNE: read data buffer not empty
+ \arg USART_FLAG_TC: transmission completed
+ \arg USART_FLAG_TBE: transmit data register empty
+ \arg USART_FLAG_LBD: LIN break detected flag
+ \arg USART_FLAG_CTSF: CTS change flag
+ \arg USART_FLAG_CTS: CTS level
+ \arg USART_FLAG_RT: receiver timeout flag
+ \arg USART_FLAG_EB: end of block flag
+ \arg USART_FLAG_ABDE: auto baudrate detection error
+ \arg USART_FLAG_ABD: auto baudrate detection flag
+ \arg USART_FLAG_BSY: busy flag
+ \arg USART_FLAG_AM: address match flag
+ \arg USART_FLAG_SB: send break flag
+ \arg USART_FLAG_RWU: receiver wakeup from mute mode.
+ \arg USART_FLAG_WU: wakeup from deep-sleep mode flag
+ \arg USART_FLAG_TEA: transmit enable acknowledge flag
+ \arg USART_FLAG_REA: receive enable acknowledge flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
+{
+ if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear USART status
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] flag: flag type
+ \arg USART_FLAG_PERR: parity error flag
+ \arg USART_FLAG_FERR: frame error flag
+ \arg USART_FLAG_NERR: noise detected flag
+ \arg USART_FLAG_ORERR:overrun error flag
+ \arg USART_FLAG_IDLE: idle line detected flag
+ \arg USART_FLAG_TC: transmission complete flag
+ \arg USART_FLAG_LBD: LIN break detected flag
+ \arg USART_FLAG_CTSF: CTS change flag
+ \arg USART_FLAG_RT: receiver timeout flag
+ \arg USART_FLAG_EB: end of block flag
+ \arg USART_FLAG_AM: address match flag
+ \arg USART_FLAG_WU: wakeup from deep-sleep mode flag
+ \param[out] none
+ \retval none
+*/
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
+{
+ USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag));
+}
+
+/*!
+ \brief enable USART interrupt
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] inttype: interrupt type
+ \arg USART_INT_IDLE: idle interrupt
+ \arg USART_INT_RBNE: read data buffer not empty interrupt and
+ overrun error interrupt enable interrupt
+ \arg USART_INT_TC: transmission complete interrupt
+ \arg USART_INT_TBE: transmit data register empty interrupt
+ \arg USART_INT_PERR: parity error interrupt
+ \arg USART_INT_AM: address match interrupt
+ \arg USART_INT_RT: receiver timeout interrupt
+ \arg USART_INT_EB: end of block interrupt
+ \arg USART_INT_LBD: LIN break detection interrupt
+ \arg USART_INT_ERR: error interrupt enable in multibuffer communication
+ \arg USART_INT_CTS: CTS interrupt
+ \arg USART_INT_WU: wakeup from deep-sleep mode interrupt
+ \param[out] none
+ \retval none
+*/
+void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype)
+{
+ USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype));
+}
+
+/*!
+ \brief disable USART interrupt
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] inttype: interrupt type
+ \arg USART_INT_IDLE: idle interrupt
+ \arg USART_INT_RBNE: read data buffer not empty interrupt and
+ overrun error interrupt
+ \arg USART_INT_TC: transmission complete interrupt
+ \arg USART_INT_TBE: transmit data register empty interrupt
+ \arg USART_INT_PERR: parity error interrupt
+ \arg USART_INT_AM: address match interrupt
+ \arg USART_INT_RT: receiver timeout interrupt
+ \arg USART_INT_EB: end of block interrupt
+ \arg USART_INT_LBD: LIN break detection interrupt
+ \arg USART_INT_ERR: error interrupt enable in multibuffer communication
+ \arg USART_INT_CTS: CTS interrupt
+ \arg USART_INT_WU: wakeup from deep-sleep mode interrupt
+ \param[out] none
+ \retval none
+*/
+void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype)
+{
+ USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype));
+}
+
+/*!
+ \brief enable USART command
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] cmdtype: command type
+ \arg USART_CMD_ABDCMD: auto baudrate detection command
+ \arg USART_CMD_SBKCMD: send break command
+ \arg USART_CMD_MMCMD: mute mode command
+ \arg USART_CMD_RXFCMD: receive data flush command
+ \arg USART_CMD_TXFCMD: transmit data flush request
+ \param[out] none
+ \retval none
+*/
+void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype)
+{
+ USART_CMD(usart_periph) |= (cmdtype);
+}
+
+/*!
+ \brief get USART interrupt and flag status
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum
+ \arg USART_INT_FLAG_EB: end of block interrupt and flag
+ \arg USART_INT_FLAG_RT: receiver timeout interrupt and flag
+ \arg USART_INT_FLAG_AM: address match interrupt and flag
+ \arg USART_INT_FLAG_PERR: parity error interrupt and flag
+ \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
+ \arg USART_INT_FLAG_TC: transmission complete interrupt and flag
+ \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
+ \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
+ \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
+ \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag
+ \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag
+ \arg USART_INT_FLAG_CTS: CTS interrupt and flag
+ \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
+ \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
+ \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
+{
+ uint32_t intenable = 0U, flagstatus = 0U;
+ /* get the interrupt enable bit status */
+ intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
+ /* get the corresponding flag bit status */
+ flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
+
+ if(flagstatus && intenable){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/*!
+ \brief clear USART interrupt flag in STAT register
+ \param[in] usart_periph: USARTx(x=0,1)
+ \param[in] flag: USART interrupt flag
+ \arg USART_INT_FLAG_PERR: parity error flag
+ \arg USART_INT_FLAG_FERR: frame error flag
+ \arg USART_INT_FLAG_NERR: noise detected flag
+ \arg USART_INT_FLAG_ORERR:overrun error flag
+ \arg USART_INT_FLAG_IDLE: idle line detected flag
+ \arg USART_INT_FLAG_TC: transmission complete flag
+ \arg USART_INT_FLAG_LBD: LIN break detected flag
+ \arg USART_INT_FLAG_CTS: CTS change flag
+ \arg USART_INT_FLAG_RT: receiver timeout flag
+ \arg USART_INT_FLAG_EB: end of block flag
+ \arg USART_INT_FLAG_AM: address match flag
+ \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode flag
+ \param[out] none
+ \retval none
+*/
+void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
+{
+ USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag));
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_wwdgt.c b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_wwdgt.c
similarity index 96%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_wwdgt.c
rename to HUGS/RTE/Device/GD32F130C8/gd32f1x0_wwdgt.c
index 2d45da1a..7a762cc2 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/gd32f1x0_wwdgt.c
+++ b/HUGS/RTE/Device/GD32F130C8/gd32f1x0_wwdgt.c
@@ -1,121 +1,121 @@
-/*!
- \file gd32f1x0_wwdgt.c
- \brief WWDGT driver
-*/
-
-/*
- Copyright (C) 2017 GigaDevice
-
- 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
- 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
- 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
- 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-*/
-
-#include "gd32f1x0_wwdgt.h"
-#include "gd32f1x0_rcu.h"
-
-/*!
- \brief reset the window watchdog timer configuration
- \param[in] none
- \param[out] none
- \retval none
-*/
-void wwdgt_deinit(void)
-{
- rcu_periph_reset_enable(RCU_WWDGTRST);
- rcu_periph_reset_disable(RCU_WWDGTRST);
-}
-
-/*!
- \brief configure the window watchdog timer counter value
- \param[in] counter_value: 0x00 - 0x7F
- \param[out] none
- \retval none
-*/
-void wwdgt_counter_update(uint16_t counter_value)
-{
- uint32_t reg = 0U;
-
- reg = WWDGT_CTL & (~WWDGT_CTL_CNT);
- reg |= (uint32_t)(CTL_CNT((uint32_t)counter_value));
-
- WWDGT_CTL = (uint32_t)reg;
-}
-
-/*!
- \brief start the window watchdog timer counter
- \param[in] none
- \param[out] none
- \retval none
-*/
-void wwdgt_enable(void)
-{
- WWDGT_CTL |= WWDGT_CTL_WDGTEN;
-}
-
-/*!
- \brief configure counter value, window value, and prescaler divider value
- \param[in] counter: 0x00 - 0x7F
- \param[in] window: 0x00 - 0x7F
- \param[in] prescaler: wwdgt prescaler value
- \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
- \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
- \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
- \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
- \param[out] none
- \retval none
-*/
-void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
-{
- uint32_t reg_cfg = 0U, reg_ctl = 0U;
-
- /* clear WIN and PSC bits, clear CNT bit */
- reg_cfg = WWDGT_CFG &(~(WWDGT_CFG_WIN | WWDGT_CFG_PSC));
- reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
-
- /* configure WIN and PSC bits, configure CNT bit */
- reg_cfg |= (uint32_t)(CFG_WIN(window));
- reg_cfg |= (uint32_t)(prescaler);
- reg_ctl |= (uint32_t)(CTL_CNT(counter));
-
- WWDGT_CFG = (uint32_t)reg_cfg;
- WWDGT_CTL = (uint32_t)reg_ctl;
-}
-
-/*!
- \brief enable early wakeup interrupt of WWDGT
- \param[in] none
- \param[out] none
- \retval none
-*/
-void wwdgt_interrupt_enable(void)
-{
- WWDGT_CFG |= WWDGT_CFG_EWIE;
-}
-
-/*!
- \brief check early wakeup interrupt state of WWDGT
- \param[in] none
- \param[out] none
- \retval FlagStatus: SET or RESET
-*/
-FlagStatus wwdgt_flag_get(void)
-{
- if(WWDGT_STAT & WWDGT_STAT_EWIF){
- return SET;
- }
-
- return RESET;
-}
-
-/*!
- \brief clear early wakeup interrupt state of WWDGT
- \param[in] none
- \param[out] none
- \retval none
-*/
-void wwdgt_flag_clear(void)
-{
- WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF);
-}
+/*!
+ \file gd32f1x0_wwdgt.c
+ \brief WWDGT driver
+*/
+
+/*
+ Copyright (C) 2017 GigaDevice
+
+ 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+ 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+ 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+ 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_rcu.h"
+
+/*!
+ \brief reset the window watchdog timer configuration
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_deinit(void)
+{
+ rcu_periph_reset_enable(RCU_WWDGTRST);
+ rcu_periph_reset_disable(RCU_WWDGTRST);
+}
+
+/*!
+ \brief configure the window watchdog timer counter value
+ \param[in] counter_value: 0x00 - 0x7F
+ \param[out] none
+ \retval none
+*/
+void wwdgt_counter_update(uint16_t counter_value)
+{
+ uint32_t reg = 0U;
+
+ reg = WWDGT_CTL & (~WWDGT_CTL_CNT);
+ reg |= (uint32_t)(CTL_CNT((uint32_t)counter_value));
+
+ WWDGT_CTL = (uint32_t)reg;
+}
+
+/*!
+ \brief start the window watchdog timer counter
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_enable(void)
+{
+ WWDGT_CTL |= WWDGT_CTL_WDGTEN;
+}
+
+/*!
+ \brief configure counter value, window value, and prescaler divider value
+ \param[in] counter: 0x00 - 0x7F
+ \param[in] window: 0x00 - 0x7F
+ \param[in] prescaler: wwdgt prescaler value
+ \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
+ \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
+ \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
+ \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
+ \param[out] none
+ \retval none
+*/
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
+{
+ uint32_t reg_cfg = 0U, reg_ctl = 0U;
+
+ /* clear WIN and PSC bits, clear CNT bit */
+ reg_cfg = WWDGT_CFG &(~(WWDGT_CFG_WIN | WWDGT_CFG_PSC));
+ reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT);
+
+ /* configure WIN and PSC bits, configure CNT bit */
+ reg_cfg |= (uint32_t)(CFG_WIN(window));
+ reg_cfg |= (uint32_t)(prescaler);
+ reg_ctl |= (uint32_t)(CTL_CNT(counter));
+
+ WWDGT_CFG = (uint32_t)reg_cfg;
+ WWDGT_CTL = (uint32_t)reg_ctl;
+}
+
+/*!
+ \brief enable early wakeup interrupt of WWDGT
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_interrupt_enable(void)
+{
+ WWDGT_CFG |= WWDGT_CFG_EWIE;
+}
+
+/*!
+ \brief check early wakeup interrupt state of WWDGT
+ \param[in] none
+ \param[out] none
+ \retval FlagStatus: SET or RESET
+*/
+FlagStatus wwdgt_flag_get(void)
+{
+ if(WWDGT_STAT & WWDGT_STAT_EWIF){
+ return SET;
+ }
+
+ return RESET;
+}
+
+/*!
+ \brief clear early wakeup interrupt state of WWDGT
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void wwdgt_flag_clear(void)
+{
+ WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF);
+}
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/startup_gd32f1x0.s b/HUGS/RTE/Device/GD32F130C8/startup_gd32f1x0.s
similarity index 97%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/startup_gd32f1x0.s
rename to HUGS/RTE/Device/GD32F130C8/startup_gd32f1x0.s
index 3118ed3e..21422d0d 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/startup_gd32f1x0.s
+++ b/HUGS/RTE/Device/GD32F130C8/startup_gd32f1x0.s
@@ -1,328 +1,328 @@
-;/*!
-; \file startup_gd32f1x0.s
-; \brief start up file
-;*/
-
-;/*
-; Copyright (C) 2017 GigaDevice
-
-; 2014-12-26, V1.0.0, firmware for GD32F1x0(x=3,5)
-; 2016-01-15, V2.0.0, firmware for GD32F1x0(x=3,5,7,9)
-; 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
-; 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
-;*/
-
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000400
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-; /* reset Vector Mapped to at Address 0 */
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
-; /* external interrupts handler */
- DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
- DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
- DCD RTC_IRQHandler ; 18:RTC through EXTI Line
- DCD FMC_IRQHandler ; 19:FMC
- DCD RCU_IRQHandler ; 20:RCU
- DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
- DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
- DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
- DCD TSI_IRQHandler ; 24:TSI
- DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
- DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
- DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
- DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1
- DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
- DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel
- DCD TIMER1_IRQHandler ; 31:TIMER1
- DCD TIMER2_IRQHandler ; 32:TIMER2
- DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC
- DCD 0 ; Reserved
- DCD TIMER13_IRQHandler ; 35:TIMER13
- DCD TIMER14_IRQHandler ; 36:TIMER14
- DCD TIMER15_IRQHandler ; 37:TIMER15
- DCD TIMER16_IRQHandler ; 38:TIMER16
- DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
- DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
- DCD SPI0_IRQHandler ; 41:SPI0
- DCD SPI1_IRQHandler ; 42:SPI1
- DCD USART0_IRQHandler ; 43:USART0
- DCD USART1_IRQHandler ; 44:USART1
- DCD 0 ; Reserved
- DCD CEC_IRQHandler ; 46:CEC
- DCD 0 ; Reserved
- DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
- DCD 0 ; Reserved
- DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
- DCD I2C2_EV_IRQHandler ; 51:I2C2 Event
- DCD I2C2_ER_IRQHandler ; 52:I2C2 Error
- DCD USBD_LP_IRQHandler ; 53:USBD LP
- DCD USBD_HP_IRQHandler ; 54:USBD HP
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD USBDWakeUp_IRQHandler ; 58:USBD Wakeup
- DCD CAN0_TX_IRQHandler ; 59:CAN0 TX
- DCD CAN0_RX0_IRQHandler ; 60:CAN0 RX0
- DCD CAN0_RX1_IRQHandler ; 61:CAN0 RX1
- DCD CAN0_SCE_IRQHandler ; 62:CAN0 SCE
- DCD SLCD_IRQHandler ; 63:SLCD
- DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI2_IRQHandler ; 67:SPI2
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN1_TX_IRQHandler ; 86:CAN1 TX
- DCD CAN1_RX0_IRQHandler ; 87:CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; 88:CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; 89:CAN1 SCE
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-;/* reset Handler */
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-;/* dummy Exception Handlers */
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler\
- PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler\
- PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-; /* external interrupts handler */
- EXPORT WWDGT_IRQHandler [WEAK]
- EXPORT LVD_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT RCU_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT TSI_IRQHandler [WEAK]
- EXPORT DMA_Channel0_IRQHandler [WEAK]
- EXPORT DMA_Channel1_2_IRQHandler [WEAK]
- EXPORT DMA_Channel3_4_IRQHandler [WEAK]
- EXPORT ADC_CMP_IRQHandler [WEAK]
- EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIMER0_Channel_IRQHandler [WEAK]
- EXPORT TIMER1_IRQHandler [WEAK]
- EXPORT TIMER2_IRQHandler [WEAK]
- EXPORT TIMER5_DAC_IRQHandler [WEAK]
- EXPORT TIMER13_IRQHandler [WEAK]
- EXPORT TIMER14_IRQHandler [WEAK]
- EXPORT TIMER15_IRQHandler [WEAK]
- EXPORT TIMER16_IRQHandler [WEAK]
- EXPORT I2C0_EV_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART0_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
- EXPORT I2C0_ER_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT USBD_LP_IRQHandler [WEAK]
- EXPORT USBD_HP_IRQHandler [WEAK]
- EXPORT USBDWakeUp_IRQHandler [WEAK]
- EXPORT CAN0_TX_IRQHandler [WEAK]
- EXPORT CAN0_RX0_IRQHandler [WEAK]
- EXPORT CAN0_RX1_IRQHandler [WEAK]
- EXPORT CAN0_SCE_IRQHandler [WEAK]
- EXPORT SLCD_IRQHandler [WEAK]
- EXPORT DMA_Channel5_6_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
-
-;/* external interrupts handler */
-WWDGT_IRQHandler
-LVD_IRQHandler
-RTC_IRQHandler
-FMC_IRQHandler
-RCU_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSI_IRQHandler
-DMA_Channel0_IRQHandler
-DMA_Channel1_2_IRQHandler
-DMA_Channel3_4_IRQHandler
-ADC_CMP_IRQHandler
-TIMER0_BRK_UP_TRG_COM_IRQHandler
-TIMER0_Channel_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER5_DAC_IRQHandler
-TIMER13_IRQHandler
-TIMER14_IRQHandler
-TIMER15_IRQHandler
-TIMER16_IRQHandler
-I2C0_EV_IRQHandler
-I2C1_EV_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-USART0_IRQHandler
-USART1_IRQHandler
-CEC_IRQHandler
-I2C0_ER_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-USBD_LP_IRQHandler
-USBD_HP_IRQHandler
-USBDWakeUp_IRQHandler
-CAN0_TX_IRQHandler
-CAN0_RX0_IRQHandler
-CAN0_RX1_IRQHandler
-CAN0_SCE_IRQHandler
-SLCD_IRQHandler
-DMA_Channel5_6_IRQHandler
-SPI2_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
- B .
- ENDP
-
- ALIGN
-
-; user Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
-
- END
+;/*!
+; \file startup_gd32f1x0.s
+; \brief start up file
+;*/
+
+;/*
+; Copyright (C) 2017 GigaDevice
+
+; 2014-12-26, V1.0.0, firmware for GD32F1x0(x=3,5)
+; 2016-01-15, V2.0.0, firmware for GD32F1x0(x=3,5,7,9)
+; 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+; 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD RTC_IRQHandler ; 18:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 19:FMC
+ DCD RCU_IRQHandler ; 20:RCU
+ DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
+ DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
+ DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
+ DCD TSI_IRQHandler ; 24:TSI
+ DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
+ DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
+ DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
+ DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1
+ DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
+ DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel
+ DCD TIMER1_IRQHandler ; 31:TIMER1
+ DCD TIMER2_IRQHandler ; 32:TIMER2
+ DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC
+ DCD 0 ; Reserved
+ DCD TIMER13_IRQHandler ; 35:TIMER13
+ DCD TIMER14_IRQHandler ; 36:TIMER14
+ DCD TIMER15_IRQHandler ; 37:TIMER15
+ DCD TIMER16_IRQHandler ; 38:TIMER16
+ DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
+ DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
+ DCD SPI0_IRQHandler ; 41:SPI0
+ DCD SPI1_IRQHandler ; 42:SPI1
+ DCD USART0_IRQHandler ; 43:USART0
+ DCD USART1_IRQHandler ; 44:USART1
+ DCD 0 ; Reserved
+ DCD CEC_IRQHandler ; 46:CEC
+ DCD 0 ; Reserved
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD 0 ; Reserved
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD I2C2_EV_IRQHandler ; 51:I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 52:I2C2 Error
+ DCD USBD_LP_IRQHandler ; 53:USBD LP
+ DCD USBD_HP_IRQHandler ; 54:USBD HP
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USBDWakeUp_IRQHandler ; 58:USBD Wakeup
+ DCD CAN0_TX_IRQHandler ; 59:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 60:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 61:CAN0 RX1
+ DCD CAN0_SCE_IRQHandler ; 62:CAN0 SCE
+ DCD SLCD_IRQHandler ; 63:SLCD
+ DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD CAN1_TX_IRQHandler ; 86:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 87:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 88:CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; 89:CAN1 SCE
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_IRQHandler [WEAK]
+ EXPORT EXTI0_1_IRQHandler [WEAK]
+ EXPORT EXTI2_3_IRQHandler [WEAK]
+ EXPORT EXTI4_15_IRQHandler [WEAK]
+ EXPORT TSI_IRQHandler [WEAK]
+ EXPORT DMA_Channel0_IRQHandler [WEAK]
+ EXPORT DMA_Channel1_2_IRQHandler [WEAK]
+ EXPORT DMA_Channel3_4_IRQHandler [WEAK]
+ EXPORT ADC_CMP_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER5_DAC_IRQHandler [WEAK]
+ EXPORT TIMER13_IRQHandler [WEAK]
+ EXPORT TIMER14_IRQHandler [WEAK]
+ EXPORT TIMER15_IRQHandler [WEAK]
+ EXPORT TIMER16_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT USBD_LP_IRQHandler [WEAK]
+ EXPORT USBD_HP_IRQHandler [WEAK]
+ EXPORT USBDWakeUp_IRQHandler [WEAK]
+ EXPORT CAN0_TX_IRQHandler [WEAK]
+ EXPORT CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_SCE_IRQHandler [WEAK]
+ EXPORT SLCD_IRQHandler [WEAK]
+ EXPORT DMA_Channel5_6_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSI_IRQHandler
+DMA_Channel0_IRQHandler
+DMA_Channel1_2_IRQHandler
+DMA_Channel3_4_IRQHandler
+ADC_CMP_IRQHandler
+TIMER0_BRK_UP_TRG_COM_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER5_DAC_IRQHandler
+TIMER13_IRQHandler
+TIMER14_IRQHandler
+TIMER15_IRQHandler
+TIMER16_IRQHandler
+I2C0_EV_IRQHandler
+I2C1_EV_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+CEC_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+USBD_LP_IRQHandler
+USBD_HP_IRQHandler
+USBDWakeUp_IRQHandler
+CAN0_TX_IRQHandler
+CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_SCE_IRQHandler
+SLCD_IRQHandler
+DMA_Channel5_6_IRQHandler
+SPI2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+ B .
+ ENDP
+
+ ALIGN
+
+; user Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/system_gd32f1x0.c b/HUGS/RTE/Device/GD32F130C8/system_gd32f1x0.c
similarity index 95%
rename from HoverBoardGigaDevice/RTE/Device/GD32F130C8/system_gd32f1x0.c
rename to HUGS/RTE/Device/GD32F130C8/system_gd32f1x0.c
index 784a75da..586c9118 100644
--- a/HoverBoardGigaDevice/RTE/Device/GD32F130C8/system_gd32f1x0.c
+++ b/HUGS/RTE/Device/GD32F130C8/system_gd32f1x0.c
@@ -1,333 +1,333 @@
-/*!
- \file system_gd32f1x0.c
- \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for
- GD32F1x0 Device Series
-*/
-
-/* Copyright (c) 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
-
-#include "gd32f1x0.h"
-
-/* system frequency define */
-#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
-#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
-#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
-
-/* select a system clock by uncommenting the following line */
-//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
-//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
-//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
-#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
-
-#define SEL_IRC8M 0x00
-#define SEL_HXTAL 0x01
-#define SEL_PLL 0x02
-
-/* set the system clock frequency and declare the system clock configuration function */
-#ifdef __SYSTEM_CLOCK_8M_HXTAL
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
-static void system_clock_8m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
-static void system_clock_72m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
-static void system_clock_72m_irc8m(void);
-#else
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
-static void system_clock_8m_irc8m(void);
-#endif /* __SYSTEM_CLOCK_8M_HXTAL */
-
-/* configure the system clock */
-static void system_clock_config(void);
-
-/*!
- \brief setup the microcontroller system, initialize the system
- \param[in] none
- \param[out] none
- \retval none
-*/
-void SystemInit (void)
-{
- /* enable IRC8M */
- RCU_CTL0 |= RCU_CTL0_IRC8MEN;
- while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
- }
- /* reset RCU */
-#ifdef GD32F130_150
- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
- RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
-#elif defined (GD32F170_190)
- RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
- RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
-#endif /* GD32F130_150 */
- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
-#ifdef GD32F130_150
- RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
-#endif /* GD32F130_150 */
- RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
- RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
- RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
-#ifdef GD32F130_150
- RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
-#elif defined (GD32F170_190)
- RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
- RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
- RCU_CFG3 &= ~RCU_CFG3_CKOUT1SRC;
- RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
-#endif /* GD32F130_150 */
- RCU_INT = 0x00000000U;
-
- /* configure system clock */
- system_clock_config();
-}
-
-/*!
- \brief configure the system clock
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_config(void)
-{
-#ifdef __SYSTEM_CLOCK_8M_HXTAL
- system_clock_8m_hxtal();
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
- system_clock_72m_hxtal();
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
- system_clock_72m_irc8m();
-#else
- system_clock_8m_irc8m();
-#endif /* __SYSTEM_CLOCK_8M_HXTAL */
-}
-
-#ifdef __SYSTEM_CLOCK_8M_HXTAL
-/*!
- \brief configure the system clock to 8M by HXTAL
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_8m_hxtal(void)
-{
- uint32_t timeout = 0;
-
- /* enable HXTAL */
- RCU_CTL0 |= RCU_CTL0_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- while((0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++));
-
- /* if fail */
- if(0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB))
- return;
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-
- /* select HXTAL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
-
- /* wait until HXTAL is selected as system clock */
- while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL));
-}
-
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-/*!
- \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_72m_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL0 |= RCU_CTL0_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do{
- timeout++;
- stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
- }
- while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
- return;
- }
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-
- /* PLL = HXTAL * 9 = 72 MHz */
- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
- RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
-
- /* enable PLL */
- RCU_CTL0 |= RCU_CTL0_PLLEN;
-
- /* wait until PLL is stable */
- while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
- /* wait until PLL is selected as system clock */
- while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
-/*!
- \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_72m_irc8m(void)
-{
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
- /* PLL = (IRC8M/2) * 18 = 72 MHz */
- RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
- RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
-
- /* enable PLL */
- RCU_CTL0 |= RCU_CTL0_PLLEN;
-
- /* wait until PLL is stable */
- while(0 == (RCU_CTL0 & RCU_CTL0_PLLSTB));
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
- /* wait until PLL is selected as system clock */
- while(0 == (RCU_CFG0 & RCU_SCSS_PLL));
-}
-
-#else
-/*!
- \brief configure the system clock to 8M by IRC8M
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_8m_irc8m(void)
-{
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-
- /* select IRC8M as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
-
- /* wait until IRC8M is selected as system clock */
- while(0 != (RCU_CFG0 & RCU_SCSS_IRC8M));
-}
-#endif /* __SYSTEM_CLOCK_8M_HXTAL */
-
-/*!
- \brief update the SystemCoreClock with current core clock retrieved from cpu registers
- \param[in] none
- \param[out] none
- \retval none
-*/
-void SystemCoreClockUpdate (void)
-{
- uint32_t sws = 0U;
- uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
- /* exponent of AHB clock divider */
- const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
- sws = GET_BITS(RCU_CFG0, 2, 3);
- switch(sws){
- /* IRC8M is selected as CK_SYS */
- case SEL_IRC8M:
- SystemCoreClock = IRC8M_VALUE;
- break;
- /* HXTAL is selected as CK_SYS */
- case SEL_HXTAL:
- SystemCoreClock = HXTAL_VALUE;
- break;
- /* PLL is selected as CK_SYS */
- case SEL_PLL:
- /* get the value of PLLMF[3:0] */
- pllmf = GET_BITS(RCU_CFG0, 18, 21);
- pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
- /* high 16 bits */
- if(1U == pllmf4){
- pllmf += 17U;
- }else{
- pllmf += 2U;
- }
- /* PLL clock source selection, HXTAL or IRC8M/2 */
- pllsel = GET_BITS(RCU_CFG0, 16, 16);
- if(0U != pllsel){
- prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
- SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
- }else{
- SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
- }
- break;
- /* IRC8M is selected as CK_SYS */
- default:
- SystemCoreClock = IRC8M_VALUE;
- break;
- }
- /* calculate AHB clock frequency */
- idx = GET_BITS(RCU_CFG0, 4, 7);
- clk_exp = ahb_exp[idx];
- SystemCoreClock >>= clk_exp;
-}
+/*!
+ \file system_gd32f1x0.c
+ \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for
+ GD32F1x0 Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#include "gd32f1x0.h"
+
+/* system frequency define */
+#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
+#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
+#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
+
+/* select a system clock by uncommenting the following line */
+//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
+//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
+#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
+
+#define SEL_IRC8M 0x00
+#define SEL_HXTAL 0x01
+#define SEL_PLL 0x02
+
+/* set the system clock frequency and declare the system clock configuration function */
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
+static void system_clock_8m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
+static void system_clock_72m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
+static void system_clock_72m_irc8m(void);
+#else
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
+static void system_clock_8m_irc8m(void);
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+
+/* configure the system clock */
+static void system_clock_config(void);
+
+/*!
+ \brief setup the microcontroller system, initialize the system
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void SystemInit (void)
+{
+ /* enable IRC8M */
+ RCU_CTL0 |= RCU_CTL0_IRC8MEN;
+ while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
+ }
+ /* reset RCU */
+#ifdef GD32F130_150
+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+ RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
+#elif defined (GD32F170_190)
+ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
+ RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
+#endif /* GD32F130_150 */
+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
+#ifdef GD32F130_150
+ RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
+#endif /* GD32F130_150 */
+ RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
+ RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
+ RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
+#ifdef GD32F130_150
+ RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
+#elif defined (GD32F170_190)
+ RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
+ RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
+ RCU_CFG3 &= ~RCU_CFG3_CKOUT1SRC;
+ RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
+#endif /* GD32F130_150 */
+ RCU_INT = 0x00000000U;
+
+ /* configure system clock */
+ system_clock_config();
+}
+
+/*!
+ \brief configure the system clock
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_config(void)
+{
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+ system_clock_8m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+ system_clock_72m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+ system_clock_72m_irc8m();
+#else
+ system_clock_8m_irc8m();
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+}
+
+#ifdef __SYSTEM_CLOCK_8M_HXTAL
+/*!
+ \brief configure the system clock to 8M by HXTAL
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_8m_hxtal(void)
+{
+ uint32_t timeout = 0;
+
+ /* enable HXTAL */
+ RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ while((0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++));
+
+ /* if fail */
+ if(0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB))
+ return;
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+
+ /* select HXTAL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+
+ /* wait until HXTAL is selected as system clock */
+ while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL));
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+/*!
+ \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_72m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL0 |= RCU_CTL0_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do{
+ timeout++;
+ stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
+ }
+ while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
+ return;
+ }
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+
+ /* PLL = HXTAL * 9 = 72 MHz */
+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
+ RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
+
+ /* enable PLL */
+ RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+ /* wait until PLL is stable */
+ while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+ /* wait until PLL is selected as system clock */
+ while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
+/*!
+ \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_72m_irc8m(void)
+{
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+ /* PLL = (IRC8M/2) * 18 = 72 MHz */
+ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
+ RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
+
+ /* enable PLL */
+ RCU_CTL0 |= RCU_CTL0_PLLEN;
+
+ /* wait until PLL is stable */
+ while(0 == (RCU_CTL0 & RCU_CTL0_PLLSTB));
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+ /* wait until PLL is selected as system clock */
+ while(0 == (RCU_CFG0 & RCU_SCSS_PLL));
+}
+
+#else
+/*!
+ \brief configure the system clock to 8M by IRC8M
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_8m_irc8m(void)
+{
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+
+ /* select IRC8M as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
+
+ /* wait until IRC8M is selected as system clock */
+ while(0 != (RCU_CFG0 & RCU_SCSS_IRC8M));
+}
+#endif /* __SYSTEM_CLOCK_8M_HXTAL */
+
+/*!
+ \brief update the SystemCoreClock with current core clock retrieved from cpu registers
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t sws = 0U;
+ uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
+ /* exponent of AHB clock divider */
+ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+ sws = GET_BITS(RCU_CFG0, 2, 3);
+ switch(sws){
+ /* IRC8M is selected as CK_SYS */
+ case SEL_IRC8M:
+ SystemCoreClock = IRC8M_VALUE;
+ break;
+ /* HXTAL is selected as CK_SYS */
+ case SEL_HXTAL:
+ SystemCoreClock = HXTAL_VALUE;
+ break;
+ /* PLL is selected as CK_SYS */
+ case SEL_PLL:
+ /* get the value of PLLMF[3:0] */
+ pllmf = GET_BITS(RCU_CFG0, 18, 21);
+ pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
+ /* high 16 bits */
+ if(1U == pllmf4){
+ pllmf += 17U;
+ }else{
+ pllmf += 2U;
+ }
+ /* PLL clock source selection, HXTAL or IRC8M/2 */
+ pllsel = GET_BITS(RCU_CFG0, 16, 16);
+ if(0U != pllsel){
+ prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
+ SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
+ }else{
+ SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
+ }
+ break;
+ /* IRC8M is selected as CK_SYS */
+ default:
+ SystemCoreClock = IRC8M_VALUE;
+ break;
+ }
+ /* calculate AHB clock frequency */
+ idx = GET_BITS(RCU_CFG0, 4, 7);
+ clk_exp = ahb_exp[idx];
+ SystemCoreClock >>= clk_exp;
+}
diff --git a/HUGS/RTE/_Target_1/RTE_Components.h b/HUGS/RTE/_Target_1/RTE_Components.h
new file mode 100644
index 00000000..48da42f2
--- /dev/null
+++ b/HUGS/RTE/_Target_1/RTE_Components.h
@@ -0,0 +1,49 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'HUGS'
+ * Target: 'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "gd32f1x0.h"
+
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:ADC:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_ADC
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:DMA:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_DMA
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:FWDGT:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_FWDGT
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:GPIO:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_GPIO
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:I2C:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_I2C
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:MCUDBG:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_DBG
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:MISC:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_MISC
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:OPA:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_OPA
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:PMU:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_PMU
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:RCU:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_RCU
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:SYSCFG:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_SYSCFG
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:TIMER:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_TIMER
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:USART:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_USART
+/* GigaDevice::Device:GD32F1x0_StdPeripherals:WWDGT:3.1.0 */
+#define RTE_DEVICE_STDPERIPHERALS_WWDGT
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/HUGS/Src/bldc.c b/HUGS/Src/bldc.c
new file mode 100644
index 00000000..7fb4a980
--- /dev/null
+++ b/HUGS/Src/bldc.c
@@ -0,0 +1,530 @@
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+#include "../Inc/setup.h"
+#include "../Inc/defines.h"
+#include "../Inc/config.h"
+
+#include "../Inc/bldc.h"
+
+#define FULL_PHASE 360
+#define PHASE_Y_OFFSET (0)
+#define PHASE_B_OFFSET (FULL_PHASE / 3)
+#define PHASE_G_OFFSET (FULL_PHASE * 2 / 3)
+#define TRANSITION_ANGLE 233
+
+// Internal constants
+const int16_t pwm_res = 72000000 / 2 / PWM_FREQ; // = 2000
+const int32_t WHEEL_PERIMETER = 530 ; // mm
+const int32_t SPEED_TICKS_FACTOR = 188444 ; // Divide factor by speed to get ticks per cycle, or visa versa.
+const int32_t SINE_TICKS_FACTOR = 3010 ; // Divide factor by speed to get ticks per degree.
+const int32_t MIN_SPEED = 5 ; // min usable speed in mm/S
+const int32_t MAX_PHASE_PERIOD = SPEED_TICKS_FACTOR / MIN_SPEED ; // one phase count @ MIN_SPEED
+const float MM_PER_CYCLE_FLOAT = 5.888; // (530 / 90)
+
+//----------------------------------------------------------------------------
+// Sinusoidal Power Commutation table (one degree increments. * 1000)
+//----------------------------------------------------------------------------
+const int16_t sineTable[FULL_PHASE] = {0, 31, 63, 94, 117, 148, 180, 211, 242, 266, 297, 328, 359, 391, 414, 445, 477, 500, 531, 563, 586, 617, 648, 672, 703, 727, 758, 781, 813, 836, 859, 867, 875, 883, 891, 898, 906, 914, 922, 930, 938, 938, 945, 953, 953, 961, 969, 969, 977, 977, 977, 984, 984, 984, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 984, 984, 984, 977, 977, 977, 969, 969, 961, 953, 953, 945, 938, 938, 930, 922, 914, 906, 898, 891, 883, 875, 867, 859, 867, 875, 883, 891, 898, 906, 914, 922, 930, 938, 938, 945, 953, 953, 961, 969, 969, 977, 977, 977, 984, 984, 984, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 992, 984, 984, 984, 977, 977, 977, 969, 969, 961, 953, 953, 945, 938, 938, 930, 922, 914, 906, 898, 891, 883, 875, 867, 859, 836, 813, 781, 758, 727, 703, 672, 648, 617, 586, 563, 531, 500, 477, 445, 414, 391, 359, 328, 297, 266, 242, 211, 180, 148, 117, 94, 63, 31, 0, -31, -63, -94, -117, -148, -180, -211, -242, -266, -297, -328, -359, -391, -414, -445, -477, -500, -531, -563, -586, -617, -648, -672, -703, -727, -758, -781, -813, -836, -859, -867, -875, -883, -891, -898, -906, -914, -922, -930, -938, -938, -945, -953, -953, -961, -969, -969, -977, -977, -977, -984, -984, -984, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -984, -984, -984, -977, -977, -977, -969, -969, -961, -953, -953, -945, -938, -938, -930, -922, -914, -906, -898, -891, -883, -875, -867, -859, -867, -875, -883, -891, -898, -906, -914, -922, -930, -938, -938, -945, -953, -953, -961, -969, -969, -977, -977, -977, -984, -984, -984, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -992, -984, -984, -984, -977, -977, -977, -969, -969, -961, -953, -953, -945, -938, -938, -930, -922, -914, -906, -898, -891, -883, -875, -867, -859, -836, -813, -781, -758, -727, -703, -672, -648, -617, -586, -563, -531, -500, -477, -445, -414, -391, -359, -328, -297, -266, -242, -211, -180, -148, -117, -94, -63, -31};
+
+//----------------------------------------------------------------------------
+// Commutation table Phase increments
+//----------------------------------------------------------------------------
+const uint8_t hall_to_pos[8] =
+{
+ // Note: Changed Comutation numbers 1-based to 0 based.
+ // annotation: for example SA=0 means hall sensor pulls SA down to Ground
+ 6, // hall position [0] - No function (access from 0-5)
+ 2, // hall position [1] (SA=1, SB=0, SC=0) -> PWM-position 2
+ 4, // hall position [2] (SA=0, SB=1, SC=0) -> PWM-position 4
+ 3, // hall position [3] (SA=1, SB=1, SC=0) -> PWM-position 3
+ 0, // hall position [4] (SA=0, SB=0, SC=1) -> PWM-position 0
+ 1, // hall position [5] (SA=1, SB=0, SC=1) -> PWM-position 1
+ 5, // hall position [6] (SA=0, SB=1, SC=1) -> PWM-position 5
+ 6, // hall position [7] - No function (access from 0-5)
+};
+
+uint16_t batteryVoltagemV = 40000;
+uint16_t currentDCmA = 0;
+int32_t cycles = 0;
+int32_t speedCounter = 0;
+int32_t phasePeriod = 0;
+int8_t stepDir = 0; // determined rotation direction
+int8_t speedDir = 0; // commanded rotation direction
+int8_t controlMode = 0; // 1,2 or 3
+uint8_t speedMode = DEFAULT_SPEED_MODE; // Desired Closed Loop Speed Mode. 0 = PF, 1 = STEP, 2 = Dual
+uint8_t maxStepSpeed = DEFAULT_MAX_STEP_SPEED; //
+
+int16_t outF = 0;
+int16_t outP = 0;
+int16_t outI = 0;
+
+int32_t speedError = 0;
+int32_t errorIntegral = 0; // PID components scaled up by 15 bits
+
+bool stepperMode = FALSE;
+bool phaseRestart = FALSE;
+int32_t stepperPeriod = 0;
+int32_t stepperTicks = 0;
+
+int16_t step_y = PHASE_Y_OFFSET;
+int16_t step_b = PHASE_B_OFFSET;
+int16_t step_g = PHASE_G_OFFSET;
+
+int y = 0; // yellow = phase A
+int b = 0; // blue = phase B
+int g = 0; // green = phase C
+
+// Timeoutvariable set by timeout timer
+extern FlagStatus timedOut;
+
+// Variables to be set from the main routine
+int16_t bldcInputPwm = 0;
+FlagStatus bldcEnable = RESET;
+int32_t speedSetpoint = 0;
+int32_t lastSpeedSetpoint = 0;
+bool closedLoopSpeed = FALSE;
+
+// ADC buffer to be filled by DMA
+adc_buf_t adc_buffer;
+
+// Internal calculation variables
+uint8_t pos;
+uint8_t lastPos;
+
+FlagStatus buzzerToggle = RESET;
+uint8_t buzzerFreq = 0;
+uint8_t buzzerPattern = 0;
+uint16_t buzzerTimer = 0;
+int16_t offsetcount = 0;
+int16_t offsetdc = 2000;
+
+// Low Pass Filter Regs
+int32_t realSpeedFilterReg = 0;
+int16_t realSpeedmmPS = 0;
+
+int32_t PWMFilterReg = 0;
+int16_t bldcFilteredPwm = 0;
+
+
+//----------------------------------------------------------------------------
+// Block PWM calculation based on position
+//----------------------------------------------------------------------------
+__INLINE void blockPWM(int pwm, int pwmPos, int *y, int *b, int *g)
+{
+ // Note: These now cycle from 0 to 5 with positive applied PWM
+ switch(pwmPos)
+ {
+ case 0:
+ *y = 0;
+ *b = -pwm;
+ *g = pwm;
+ break;
+ case 1:
+ *y = pwm;
+ *b = -pwm;
+ *g = 0;
+ break;
+ case 2:
+ *y = pwm;
+ *b = 0;
+ *g = -pwm;
+ break;
+ case 3:
+ *y = 0;
+ *b = pwm;
+ *g = -pwm;
+ break;
+ case 4:
+ *y = -pwm;
+ *b = pwm;
+ *g = 0;
+ break;
+ case 5:
+ *y = -pwm;
+ *b = 0;
+ *g = pwm;
+ break;
+ default:
+ *y = 0;
+ *b = 0;
+ *g = 0;
+ }
+}
+
+//----------------------------------------------------------------------------
+// Set motor enable
+//----------------------------------------------------------------------------
+void SetEnable(FlagStatus setEnable)
+{
+ if (!bldcEnable || !setEnable) {
+ closedLoopSpeed = FALSE;
+ }
+ bldcEnable = setEnable;
+}
+
+//----------------------------------------------------------------------------
+// Set speed -5000 to 5000
+//----------------------------------------------------------------------------
+void SetSpeed(int16_t speed)
+{
+ // Keep driver alive
+ if (abs16(speed) >= 10) {
+ resetInactivityTimer();
+ }
+
+ closedLoopSpeed = TRUE;
+ speedSetpoint = CLAMP(speed, -5000, 5000);
+
+ if (speed > 0)
+ speedDir = 1;
+ else if (speed < 0)
+ speedDir = -1;
+ else {
+ speedDir = 0;
+ controlMode = 0;
+ }
+
+ // Do we need stepper mode?
+ if ( (speedMode == SPEED_MODE_PF) ||
+ ((speedMode == SPEED_MODE_DUAL) && (abs16(speedSetpoint) > maxStepSpeed))
+ ) {
+ stepperMode = FALSE;
+ phaseRestart = FALSE;
+ } else {
+
+ // do we need to defer switching to stepper to get synched?
+ // we do this is we are currently in closed loop and are slowing down.
+ // If we don't do this, the wheel jumps forward or back
+ if (controlMode == 3) {
+ phaseRestart = TRUE;
+ } else {
+ stepperMode = TRUE; // Turn on stepper now
+ }
+
+ stepperPeriod = SINE_TICKS_FACTOR / abs16(speedSetpoint) ;
+ }
+}
+
+//----------------------------------------------------------------------------
+// Set power -1000 to 1000
+//----------------------------------------------------------------------------
+void SetPower(int16_t power)
+{
+ // Keep driver alive
+ if (abs16(power) > 5) {
+ resetInactivityTimer();
+ }
+ closedLoopSpeed = FALSE;
+ stepperMode = FALSE;
+ speedSetpoint = 0;
+
+ if (power == 0)
+ controlMode = 0;
+
+ // stepperTicks = 0;
+ SetPWM(power);
+}
+
+//----------------------------------------------------------------------------
+// Set pwm -1000 to 1000
+//----------------------------------------------------------------------------
+void SetPWM(int16_t setPwm)
+{
+ bldcInputPwm = CLAMP(setPwm, -1000, 1000);
+}
+
+//----------------------------------------------------------------------------
+// Get pwm -1000 to 1000
+//----------------------------------------------------------------------------
+int16_t GetPWM()
+{
+ return bldcFilteredPwm ;
+}
+
+//----------------------------------------------------------------------------
+// Get speed in mm/Sec
+//----------------------------------------------------------------------------
+int16_t GetSpeed()
+{
+ return realSpeedmmPS ;
+}
+
+//----------------------------------------------------------------------------
+// Get speed in mm/Sec
+//----------------------------------------------------------------------------
+void CalculateSpeed()
+{
+ int16_t speed;
+
+ if (phasePeriod == MAX_PHASE_PERIOD ) {
+ speed = 0 ;
+ }
+ else{
+ speed = (SPEED_TICKS_FACTOR / phasePeriod) * stepDir ;
+ }
+
+ // Calculate low-pass filter for phase Period
+ realSpeedFilterReg = realSpeedFilterReg - (realSpeedFilterReg >> SPEED_FILTER_SHIFT) + speed;
+ realSpeedmmPS = realSpeedFilterReg >> SPEED_FILTER_SHIFT;
+}
+
+//----------------------------------------------------------------------------
+// Get position in mm
+//----------------------------------------------------------------------------
+int32_t GetPosition(void) {
+ return (int32_t)((float)cycles * MM_PER_CYCLE_FLOAT) ;
+}
+
+//----------------------------------------------------------------------------
+// Calculation-Routine for BLDC => calculates with 32kHz (was 16 kHz)
+// Written so there are no function calls requiring stack protection.
+//----------------------------------------------------------------------------
+void CalculateBLDC(void)
+{
+ int8_t stepDif;
+
+ // Create square wave for buzzer
+ buzzerTimer++;
+ if (buzzerFreq != 0 && (buzzerTimer / 5000) % (buzzerPattern + 1) == 0){
+ if (buzzerTimer % buzzerFreq == 0){
+ buzzerToggle = buzzerToggle == RESET ? SET : RESET; // toggle variable
+ gpio_bit_write(BUZZER_PORT, BUZZER_PIN, buzzerToggle);
+ }
+ } else {
+ gpio_bit_write(BUZZER_PORT, BUZZER_PIN, RESET);
+ }
+
+ // Calibrate ADC offsets for the first 1000 cycles
+ if (offsetcount < 1000) {
+ offsetcount++;
+ offsetdc = (adc_buffer.current_dc + offsetdc) / 2;
+ return;
+ }
+
+ // Calculate battery voltage & current every 100 cycles
+ if (buzzerTimer % 100 == 0) {
+ uint16_t tempV = (uint16_t)(((uint32_t)adc_buffer.v_batt * ADC_BATTERY_MICRO_VOLT) / 1000);
+ uint16_t tempI = (uint16_t)((ABS((adc_buffer.current_dc - offsetdc) * MOTOR_AMP_CONV_DC_MICRO_AMP)) / 1000);
+
+ batteryVoltagemV += ((tempV - batteryVoltagemV) / 100);
+ currentDCmA += ((tempI - currentDCmA) / 100);
+ }
+
+ // Disable PWM when current limit is reached (current chopping), enable is not set or timeout is reached
+ if (currentDCmA > DC_CUR_LIMIT_MA || bldcEnable == RESET || timedOut == SET) {
+ timer_automatic_output_disable(TIMER_BLDC);
+ } else {
+ timer_automatic_output_enable(TIMER_BLDC);
+ }
+
+ // Get current commutation position
+ pos = hallToPos();
+
+ // Are we switching phase steps? If so, time to calculate phase period
+ if (pos != lastPos) {
+ phasePeriod = speedCounter;
+ speedCounter = 0;
+
+ // Check direction of rotation
+ stepDif = pos - lastPos;
+ if ((stepDif == 1) || (stepDif == -5))
+ stepDir = 1;
+ else if ((stepDif == -1) || (stepDif == 5))
+ stepDir = -1;
+
+ // Integrate steps to measure distance
+ cycles += stepDir;
+
+ // if we are waiting for a phase restart, load new angle.
+ if (phaseRestart) {
+ phaseRestart = FALSE;
+ stepperMode = TRUE;
+
+ setPhaseAngle(getTransitionAngle());
+ }
+ }
+
+ // Accumulate counters for speed and phase duration
+ // Increments with 31.25 us
+ if(speedCounter < MAX_PHASE_PERIOD) { // No speed less than MIN_SPEED
+ speedCounter += 1;
+ } else {
+ phasePeriod = MAX_PHASE_PERIOD; // MIN_SPEED phase duration
+ realSpeedmmPS = 0;
+ }
+
+ // ======================================================================================
+ // Determine desired phase commutation and PWM based on operational mode
+ // Three conditions are:
+ // 1) Open loop power
+ // 2) Closed Loop Stepping (Slow Speed)
+ // 3) Closed Loop Running (PIDF), (Fast Speed)
+ // ======================================================================================
+
+ if (closedLoopSpeed) {
+
+ if (speedSetpoint == 0){
+ SetPWM(0) ;
+ } else {
+
+ // determine speed error and set power level
+ SetPWM(runPID());
+
+ }
+
+ // Calculate low-pass filter for pwm value (we don't always need it. but best to keep running.)
+ PWMFilterReg = PWMFilterReg - (PWMFilterReg >> PWM_FILTER_SHIFT) + bldcInputPwm;
+ bldcFilteredPwm = PWMFilterReg >> PWM_FILTER_SHIFT;
+
+ if (stepperMode) {
+ // 2) Closed Loop Stepping (Slow Speed)
+ controlMode = 2;
+ stepperTicks++;
+
+ // Are we moving to the next angle?
+ if (stepperTicks >= stepperPeriod) {
+ setPhaseAngle(step_y + speedDir);
+ stepperTicks = 0;
+ }
+
+ // Get three PWM values from sine table
+ y = sineTable[step_y] >> 3;
+ b = sineTable[step_g] >> 3;
+ g = sineTable[step_b] >> 3;
+
+ } else {
+ // 3) Closed Loop Running (PIDF), (Fast Speed)
+ controlMode = 3;
+
+ // Update PWM channels based on position y(ellow), b(lue), g(reen)
+ blockPWM(bldcFilteredPwm, pos, &y, &b, &g);
+ }
+ } else {
+ // 1) Open loop power, so just apply filtered PWM to correct phases
+ controlMode = 1;
+
+ // Calculate low-pass filter for pwm value
+ PWMFilterReg = PWMFilterReg - (PWMFilterReg >> PWM_FILTER_SHIFT) + bldcInputPwm;
+ bldcFilteredPwm = PWMFilterReg >> PWM_FILTER_SHIFT;
+
+ // Update PWM channels based on position y(ellow), b(lue), g(reen)
+ blockPWM(bldcFilteredPwm, pos, &y, &b, &g);
+ }
+
+ // Set PWM output (pwm_res/2 is the mean value, setvalue has to be between 10 and pwm_res-10)
+ timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, CLAMP(g + pwm_res / 2, 10, pwm_res-10));
+ timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, CLAMP(b + pwm_res / 2, 10, pwm_res-10));
+ timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, CLAMP(y + pwm_res / 2, 10, pwm_res-10));
+
+ // Safe last position
+ lastPos = pos;
+}
+
+
+// PIDF coefficients are all scaled up by 15 bits (32768)
+const int32_t KF = (int32_t)(32768.0 * 0.16) ;
+const int32_t KFO = (int32_t)(32768.0 * 28.0) ;
+const int32_t KP = (int32_t)(32768.0 * 0.2) ;
+const int32_t KI = (int32_t)(32768.0 * 0.00005) ;
+const int32_t ILIMIT = (int32_t)(32768.0 * 150) ;
+
+
+int16_t runPID() {
+ speedError = (speedSetpoint - realSpeedmmPS) ;
+
+ // Determine Feed Forward and Proportional terms
+ outF = ((speedSetpoint * KF) + (speedDir * KFO)) >> 15 ;
+ outP = (speedError * KP) >> 15;
+
+ // reset integral term if speed request near zero, or has changed signs.
+ // otherwise intergrate error
+ if ((abs32(speedSetpoint) < MIN_SPEED) ||
+ ((speedSetpoint * lastSpeedSetpoint) < 0)) {
+ errorIntegral = 0;
+ } else {
+ errorIntegral += (speedError * KI) ;
+ errorIntegral = CLAMP(errorIntegral, (-ILIMIT), ILIMIT); // do not let integral wind up too much
+ }
+ outI = errorIntegral >> 15;
+
+ lastSpeedSetpoint = speedSetpoint;
+
+ // Combine terms to form output
+ return (outF + outP + outI) ;
+}
+
+uint8_t hallToPos() {
+
+ // Read hall sensors
+ uint8_t hall_a = gpio_input_bit_get(HALL_A_PORT, HALL_A_PIN);
+ uint8_t hall_b = gpio_input_bit_get(HALL_B_PORT, HALL_B_PIN);
+ uint8_t hall_c = gpio_input_bit_get(HALL_C_PORT, HALL_C_PIN);
+
+ // Determine current position based on hall sensors
+ uint8_t hall = (hall_a * 1) + (hall_b * 2) + (hall_c * 4);
+
+ return hall_to_pos[hall];
+}
+
+int16_t getTransitionAngle() {
+ int16_t Yangle ;
+
+ if (speedDir > 0)
+ Yangle = (pos * 60) + TRANSITION_ANGLE;
+ else
+ Yangle = (pos * 60) + 180 - TRANSITION_ANGLE;
+
+ return (Yangle);
+}
+
+
+void setPhaseAngle(int16_t Yangle) {
+
+ step_y = Yangle + PHASE_Y_OFFSET;
+ step_b = Yangle + PHASE_B_OFFSET;
+ step_g = Yangle + PHASE_G_OFFSET;
+
+ // wrap into 0 359 range
+ step_y = (step_y + FULL_PHASE) % FULL_PHASE;
+ step_b = (step_b + FULL_PHASE) % FULL_PHASE;
+ step_g = (step_g + FULL_PHASE) % FULL_PHASE;
+}
+
+
+int16_t abs16 (int16_t value) {
+ if (value < 0)
+ value = -value;
+
+ return value;
+}
+
+int32_t abs32 (int32_t value) {
+ if (value < 0)
+ value = -value;
+
+ return value;
+}
diff --git a/HoverBoardGigaDevice/Src/comms.c b/HUGS/Src/comms.c
similarity index 69%
rename from HoverBoardGigaDevice/Src/comms.c
rename to HUGS/Src/comms.c
index 5f912971..a25ce255 100644
--- a/HoverBoardGigaDevice/Src/comms.c
+++ b/HUGS/Src/comms.c
@@ -1,72 +1,67 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-
-//----------------------------------------------------------------------------
-// Send buffer via USART
-//----------------------------------------------------------------------------
-void SendBuffer(uint32_t usart_periph, uint8_t buffer[], uint8_t length)
-{
- uint8_t index = 0;
-
- for(; index < length; index++)
- {
- usart_data_transmit(usart_periph, buffer[index]);
- while (usart_flag_get(usart_periph, USART_FLAG_TC) == RESET) {}
- }
-}
-
-//----------------------------------------------------------------------------
-// Calculate CRC
-//----------------------------------------------------------------------------
-uint16_t CalcCRC(uint8_t *ptr, int count)
-{
- uint16_t crc;
- uint8_t i;
- crc = 0;
- while (--count >= 0)
- {
- crc = crc ^ (uint16_t) *ptr++ << 8;
- i = 8;
- do
- {
- if (crc & 0x8000)
- {
- crc = crc << 1 ^ 0x1021;
- }
- else
- {
- crc = crc << 1;
- }
- } while(--i);
- }
- return (crc);
-}
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+
+//----------------------------------------------------------------------------
+// Send buffer via USART
+//----------------------------------------------------------------------------
+void SendBuffer(uint32_t usart_periph, uint8_t buffer[], uint8_t length)
+{
+ uint8_t index = 0;
+
+ for(; index < length; index++)
+ {
+ usart_data_transmit(usart_periph, buffer[index]);
+ while (usart_flag_get(usart_periph, USART_FLAG_TC) == RESET) {}
+ }
+}
+
+//----------------------------------------------------------------------------
+// Calculate CRC
+//----------------------------------------------------------------------------
+uint16_t CalcCRC(uint8_t *ptr, int count)
+{
+ uint16_t crc;
+ uint8_t i;
+ crc = 0;
+ while (--count >= 0)
+ {
+ crc = crc ^ (uint16_t) *ptr++ << 8;
+ i = 8;
+ do
+ {
+ if (crc & 0x8000)
+ {
+ crc = crc << 1 ^ 0x1021;
+ }
+ else
+ {
+ crc = crc << 1;
+ }
+ } while(--i);
+ }
+ return (crc);
+}
diff --git a/HUGS/Src/commsHUGS.c b/HUGS/Src/commsHUGS.c
new file mode 100644
index 00000000..6117b369
--- /dev/null
+++ b/HUGS/Src/commsHUGS.c
@@ -0,0 +1,395 @@
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+#include "../Inc/it.h"
+#include "../Inc/comms.h"
+#include "../Inc/commsHUGS.h"
+#include "../Inc/setup.h"
+#include "../Inc/config.h"
+#include "../Inc/defines.h"
+#include "../Inc/bldc.h"
+#include "stdio.h"
+#include "string.h"
+
+#define HUGS_MAX_DATA 9 // Max variable Data Length'
+#define HUGS_EOM_OFFSET 7 // Location of EOM char based on variable data length
+#define USART_HUGS_TX_BYTES (HUGS_MAX_DATA + 8) // Max buffeer size including
+#define USART_HUGS_RX_BYTES (HUGS_MAX_DATA + 8) // start '/' and stop character '\n'
+
+static bool sHUGSRecord = FALSE;
+
+extern uint8_t usartHUGS_rx_buf[USART_HUGS_RX_BUFFERSIZE];
+static uint8_t sUSARTHUGSRecordBuffer[USART_HUGS_RX_BYTES];
+static uint8_t sUSARTHUGSRecordBufferCounter = 0;
+
+extern uint16_t batteryVoltagemV;
+extern uint16_t currentDCmA ;
+extern int16_t realSpeedmmPS ;
+extern int32_t phasePeriod ;
+extern int32_t cycles ;
+extern int8_t controlMode ;
+extern uint8_t speedMode ;
+extern uint8_t maxStepSpeed ;
+extern int16_t outF ;
+extern int16_t outP ;
+extern int16_t outI ;
+extern int32_t phasePeriod ;
+
+
+bool CheckUSARTHUGSInput(uint8_t USARTBuffer[]);
+void SendHUGSReply(void);
+uint16_t CalcCRC(uint8_t *ptr, int count);
+void ShutOff(void);
+
+// Variables updated by HUGS Message
+bool HUGS_ESTOP = FALSE;
+uint16_t HUGS_WatchDog = 1000 ; // TIMEOUT_MS;
+uint8_t HUGS_Destination = 0;
+uint8_t HUGS_Sequence = 0;
+CMD_ID HUGS_CommandID = NOP;
+RSP_ID HUGS_ResponseID = NOR;
+
+
+void SetESTOP(void) {
+ HUGS_ESTOP = TRUE;
+}
+
+//----------------------------------------------------------------------------
+// Update USART HUGS input
+//----------------------------------------------------------------------------
+void UpdateUSARTHUGSInput(void)
+{
+ uint8_t character = usartHUGS_rx_buf[0];
+ uint8_t length;
+
+ // Start character is captured, start record
+ if (!sHUGSRecord && (character == '/'))
+ {
+ sUSARTHUGSRecordBufferCounter = 0;
+ sHUGSRecord = TRUE;
+ }
+
+ // Process the new charcter
+ if (sHUGSRecord)
+ {
+ sUSARTHUGSRecordBuffer[sUSARTHUGSRecordBufferCounter] = character;
+ sUSARTHUGSRecordBufferCounter++;
+
+ // Check to see if we know the length yet
+ if (sUSARTHUGSRecordBufferCounter > 1) {
+
+ // Check for an invalid length, or a completed message
+ if ((length = sUSARTHUGSRecordBuffer[1]) > HUGS_MAX_DATA){
+ // Bad data length
+ sUSARTHUGSRecordBufferCounter = 0;
+ sHUGSRecord = FALSE;
+ }
+ else if (sUSARTHUGSRecordBufferCounter > (length + HUGS_EOM_OFFSET))
+ {
+ // Check input
+ if (CheckUSARTHUGSInput (sUSARTHUGSRecordBuffer)) {
+ // A complete message was found. Reset buffer and status
+ sUSARTHUGSRecordBufferCounter = 0;
+ sHUGSRecord = FALSE;
+ } else {
+ // Message was invalid. it could have been a bad SOM
+ // check to see if the buffer holds another SOM (/)
+ int slider = 0;
+ int ch;
+
+ for (ch = 1; ch < sUSARTHUGSRecordBufferCounter; ch++) {
+ if (sUSARTHUGSRecordBuffer[ch] == '/') {
+ slider = ch;
+ break;
+ }
+ }
+
+ if (slider > 0) {
+ // push the buffer back
+ sUSARTHUGSRecordBufferCounter -= slider;
+ memcpy(sUSARTHUGSRecordBuffer, sUSARTHUGSRecordBuffer + slider, sUSARTHUGSRecordBufferCounter);
+ } else {
+ sUSARTHUGSRecordBufferCounter = 0;
+ sHUGSRecord = FALSE;
+ }
+ }
+ }
+ }
+ }
+}
+
+//----------------------------------------------------------------------------
+// Check USART HUGS input
+//----------------------------------------------------------------------------
+bool CheckUSARTHUGSInput(uint8_t USARTBuffer[])
+{
+ // Auxiliary variables
+ uint16_t crc;
+ uint8_t length = USARTBuffer[1];
+
+ // Check start and stop character
+ if ( USARTBuffer[0] != '/' ||
+ USARTBuffer[length + HUGS_EOM_OFFSET ] != '\n')
+ {
+ return FALSE;
+ }
+
+ // Calculate CRC (first bytes up to, not including crc)
+ crc = CalcCRC(USARTBuffer, length + 5 );
+
+ // Check CRC
+ if ( USARTBuffer[length + 5] != (crc & 0xFF) ||
+ USARTBuffer[length + 6] != ((crc >> 8) & 0xFF) )
+ {
+ return FALSE;
+ }
+
+ // command is valid. Process it now
+ HUGS_Destination = USARTBuffer[2] & 0x0F;
+ HUGS_Sequence = (USARTBuffer[2] >> 4) & 0x0F;
+ HUGS_CommandID = (CMD_ID)USARTBuffer[3] ;
+ HUGS_ResponseID = (RSP_ID)USARTBuffer[4] ;
+
+ switch(HUGS_CommandID) {
+ case ENA:
+ SetEnable(SET);
+ break;
+
+ case DIS:
+ SetEnable(RESET);
+ break;
+
+ case POW:
+ SetEnable(SET);
+ SetPower((int16_t)((uint16_t)USARTBuffer[6] << 8) + (uint16_t)USARTBuffer[5]);
+ break;
+
+ case DOG:
+ // save the new watchdog count (in ms)
+ HUGS_WatchDog = ((uint16_t)USARTBuffer[6] << 8) + (uint16_t)USARTBuffer[5];
+ break;
+
+ case MOD:
+ // save the new speed Mode
+ speedMode = USARTBuffer[5];
+ maxStepSpeed = USARTBuffer[6];
+ break;
+
+ case RES:
+ // reset the current wheel position
+ cycles = 0;
+ break;
+
+ case SPE:
+ // Set the constant Speed (in mm/s)
+ SetEnable(SET);
+ SetSpeed((int16_t)((uint16_t)USARTBuffer[6] << 8) + (uint16_t)USARTBuffer[5]);
+ break;
+
+ case XXX:
+ // powerdown
+ SetPower(0);
+ SetESTOP();
+ HUGS_ResponseID = STOP;
+ break;
+
+ default:
+ break;
+ }
+
+ // Send answer
+ if (HUGS_ResponseID != NOR) {
+ SendHUGSReply();
+ }
+
+ // Reset the pwm timout to avoid stopping motors
+ ResetTimeout();
+
+ return TRUE;
+}
+
+
+//----------------------------------------------------------------------------
+// Send reply frame via USART
+//----------------------------------------------------------------------------
+void SendHUGSReply()
+{
+ uint8_t length = 1;
+ uint16_t crc = 0;
+ uint8_t buffer[USART_HUGS_TX_BYTES];
+ int32_t positionMm;
+ uint8_t bitStatus = HUGS_ESTOP ? 0x01 : 0x00;
+ int16_t tempInt = 0;
+ int32_t tempLong = 0;
+
+ bitStatus |= (controlMode << 1);
+
+ buffer[0] = '/';
+ buffer[1] = 1;
+ buffer[2] = HUGS_Sequence << 4;
+ buffer[3] = RSP;
+ buffer[4] = HUGS_ResponseID;
+ buffer[5] = bitStatus;
+
+ switch(HUGS_ResponseID) {
+ case SSPE:
+ length = 3;
+ buffer[6] = realSpeedmmPS & 0xFF ;
+ buffer[7] = realSpeedmmPS >> 8;
+ break;
+
+ case SPOS:
+ length = 5;
+ positionMm = GetPosition() ;
+ buffer[6] = (positionMm) & 0xFF;
+ buffer[7] = (positionMm >> 8) & 0xFF;
+ buffer[8] = (positionMm >> 16) & 0xFF;
+ buffer[9] = (positionMm >> 24) & 0xFF;
+ break;
+
+ case SVOL:
+ length = 3;
+ buffer[6] = batteryVoltagemV & 0xFF ;
+ buffer[7] = batteryVoltagemV >> 8;
+ break;
+
+ case SAMP:
+ length = 3;
+ buffer[6] = currentDCmA & 0xFF ;
+ buffer[7] = currentDCmA >> 8;
+ break;
+
+ case SPOW:
+ length = 3;
+ tempInt = GetPWM();
+ buffer[6] = tempInt & 0xFF ;
+ buffer[7] = tempInt >> 8;
+
+ break;
+
+ case SDOG:
+ length = 3;
+ buffer[6] = HUGS_WatchDog & 0xFF ;
+ buffer[7] = HUGS_WatchDog >> 8;
+ break;
+
+ case SMOD:
+ length = 3;
+ buffer[6] = speedMode ;
+ buffer[7] = maxStepSpeed ;
+
+ break;
+
+ case SFPI:
+ length = 7;
+ buffer[6] = outF & 0xFF ;
+ buffer[7] = outF >> 8;
+ buffer[8] = outP & 0xFF ;
+ buffer[9] = outP >> 8;
+ buffer[10] = outI & 0xFF ;
+ buffer[11] = outI >> 8;
+
+ break;
+
+ case SMOT:
+ length = 9;
+ tempInt = GetPWM();
+ positionMm = GetPosition() ;
+
+ buffer[6] = realSpeedmmPS & 0xFF ;
+ buffer[7] = realSpeedmmPS >> 8;
+
+ tempLong = positionMm;
+ buffer[8] = (tempLong) & 0xFF;
+ buffer[9] = (tempLong >> 8) & 0xFF;
+ buffer[10] = (tempLong >> 16) & 0xFF;
+ buffer[11] = (tempLong >> 24) & 0xFF;
+
+ buffer[12] = tempInt & 0xFF ;
+ buffer[13] = tempInt >> 8;
+ break;
+
+ case STOP:
+ length = 1;
+ break;
+
+ default:
+ break;
+ }
+
+ buffer[1] = length;
+
+ // Calculate CRC
+ crc = CalcCRC(buffer, length + 5);
+ buffer[length + 5] = crc & 0xFF;
+ buffer[length + 6] = (crc >> 8) & 0xFF;
+ buffer[length + 7] = '\n';
+
+ SendBuffer(USART_HUGS, buffer, length + 8);
+}
+
+//----------------------------------------------------------------------------
+// Send command via USART (Presumably to SLAVE)
+//----------------------------------------------------------------------------
+void SendHUGSCmd(CMD_ID SlaveCmd, int16_t value)
+{
+ int8_t length = -1;
+ uint16_t crc = 0;
+ uint8_t buffer[USART_HUGS_TX_BYTES];
+
+ switch(SlaveCmd) {
+ case SPE:
+ length = 2;
+ buffer[5] = value & 0xFF ;
+ buffer[6] = value >> 8;
+ break;
+
+ case XXX:
+ length = 0;
+ break;
+
+ default:
+ break;
+ }
+
+ // Only send a cmd if we have recognized the command and set a valid length
+ if (length >= 0) {
+ buffer[0] = '/';
+ buffer[1] = length;
+ buffer[2] = 0;
+ buffer[3] = SlaveCmd;
+ buffer[4] = NOR;
+
+ // Calculate CRC
+ crc = CalcCRC(buffer, length + 5);
+ buffer[length + 5] = crc & 0xFF;
+ buffer[length + 6] = (crc >> 8) & 0xFF;
+ buffer[length + 7] = '\n';
+
+ SendBuffer(USART_HUGS, buffer, length + 8);
+ }
+}
+
diff --git a/HUGS/Src/commsSteering.c b/HUGS/Src/commsSteering.c
new file mode 100644
index 00000000..29a4eee4
--- /dev/null
+++ b/HUGS/Src/commsSteering.c
@@ -0,0 +1,211 @@
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+#include "../Inc/it.h"
+#include "../Inc/comms.h"
+#include "../Inc/commsHUGS.h"
+#include "../Inc/commsSteering.h"
+#include "../Inc/setup.h"
+#include "../Inc/config.h"
+#include "../Inc/defines.h"
+#include "../Inc/bldc.h"
+#include "stdio.h"
+#include "string.h"
+
+#define STEER_MAX_DATA 4 // Max variable Data Length'
+#define STEER_EOM_OFFSET 7 // Location of EOM char based on variable data length
+#define USART_STEER_RX_BYTES (STEER_MAX_DATA + 8) // start '/' and stop character '\n'
+#define USART_STEER_TX_BYTES 2 // Max buffeer size including
+
+extern uint8_t usartSteer_COM_rx_buf[USART_STEER_COM_RX_BUFFERSIZE];
+
+static bool sSteerRecord = FALSE;
+static uint8_t sUSARTSteerRecordBuffer[USART_STEER_RX_BYTES];
+static uint8_t sUSARTSteerRecordBufferCounter = 0;
+static uint8_t steerReply[USART_STEER_TX_BYTES] = {'/', '\n'};
+
+CMD_ID Steer_CommandID = NOP;
+RSP_ID Steer_ResponseID = NOR;
+
+bool CheckUSARTSteerInput(uint8_t u8USARTBuffer[]);
+
+
+//----------------------------------------------------------------------------
+// Update USART steer input
+//----------------------------------------------------------------------------
+void UpdateUSARTSteerInput(void)
+{
+ uint8_t character = usartSteer_COM_rx_buf[0];
+ uint8_t length;
+
+
+ // Start character is captured, start record
+ if (!sSteerRecord && (character == '/'))
+ {
+ sUSARTSteerRecordBufferCounter = 0;
+ sSteerRecord = TRUE;
+ }
+
+ // Process the new charcter
+ if (sSteerRecord)
+ {
+ sUSARTSteerRecordBuffer[sUSARTSteerRecordBufferCounter] = character;
+ sUSARTSteerRecordBufferCounter++;
+
+ // Check to see if we know the length yet
+ if (sUSARTSteerRecordBufferCounter > 1) {
+
+ // Check for an invalid length, or a completed message
+ if ((length = sUSARTSteerRecordBuffer[1]) > STEER_MAX_DATA){
+ // Bad data length
+ sUSARTSteerRecordBufferCounter = 0;
+ sSteerRecord = FALSE;
+ }
+ else if (sUSARTSteerRecordBufferCounter > (length + STEER_EOM_OFFSET))
+ {
+
+ // Check input using HUGS message processing
+ if (CheckUSARTSteerInput (sUSARTSteerRecordBuffer)) {
+
+ // FOR TEST PURPOSES
+ // SendBuffer(USART_STEER_COM, sUSARTSteerRecordBuffer, sUSARTSteerRecordBufferCounter);
+
+ // A complete message was found. Reset buffer and status
+ sUSARTSteerRecordBufferCounter = 0;
+ sSteerRecord = FALSE;
+ } else {
+ // Message was invalid. it could have been a bad SOM
+ // check to see if the buffer holds another SOM (/)
+ int slider = 0;
+ int ch;
+
+ for (ch = 1; ch < sUSARTSteerRecordBufferCounter; ch++) {
+ if (sUSARTSteerRecordBuffer[ch] == '/') {
+ slider = ch;
+ break;
+ }
+ }
+
+ if (slider > 0) {
+ // push the buffer back
+ sUSARTSteerRecordBufferCounter -= slider;
+ memcpy(sUSARTSteerRecordBuffer, sUSARTSteerRecordBuffer + slider, sUSARTSteerRecordBufferCounter);
+ } else {
+ sUSARTSteerRecordBufferCounter = 0;
+ sSteerRecord = FALSE;
+ }
+ }
+ }
+ }
+ }
+
+}
+
+//----------------------------------------------------------------------------
+// Check USART steer input
+//----------------------------------------------------------------------------
+bool CheckUSARTSteerInput(uint8_t USARTBuffer[])
+{
+ // Auxiliary variables
+ uint16_t crc;
+ uint8_t length = USARTBuffer[1];
+ int16_t turn_mmPS;
+ int16_t left_mmPS;
+ int16_t right_mmPS;
+ int16_t smax;
+
+
+ // Check start and stop character
+ if ( USARTBuffer[0] != '/' ||
+ USARTBuffer[length + STEER_EOM_OFFSET ] != '\n')
+ {
+ return FALSE;
+ }
+
+ // Calculate CRC (first bytes up to, not including crc)
+ crc = CalcCRC(USARTBuffer, length + 5 );
+
+ // Check CRC
+ if ( USARTBuffer[length + 5] != (crc & 0xFF) ||
+ USARTBuffer[length + 6] != ((crc >> 8) & 0xFF) )
+ {
+ return FALSE;
+ }
+
+ // command is valid. Process it now
+ Steer_CommandID = (CMD_ID)USARTBuffer[3] ;
+ Steer_ResponseID = (RSP_ID)USARTBuffer[4] ;
+
+ switch(Steer_CommandID) {
+ case DSPE:
+
+ // Set the constant Speed (in mm/s)
+ SetEnable(SET);
+
+ left_mmPS = (int16_t)((uint16_t)USARTBuffer[6] << 8) + (uint16_t)USARTBuffer[5];
+ right_mmPS = left_mmPS;
+
+ turn_mmPS = (int16_t)((float)((int16_t)((uint16_t)USARTBuffer[8] << 8) + (uint16_t)USARTBuffer[7]) * MM_PER_DEGREE);
+
+ left_mmPS += turn_mmPS;
+ right_mmPS -= turn_mmPS;
+
+ // normalize so no speed is > +/-TOP_SPEED
+ smax = max(abs16(left_mmPS), abs16(right_mmPS));
+
+ if (smax > MAX_SPEED) {
+ left_mmPS = (left_mmPS * MAX_SPEED) / smax;
+ right_mmPS = (right_mmPS * MAX_SPEED) / smax;
+ }
+
+ SendHUGSCmd(SPE, -left_mmPS) ;
+ SetSpeed(right_mmPS);
+ break;
+
+ case XXX:
+ // powerdown
+ SendHUGSCmd(SPE, 0) ;
+ SendHUGSCmd(XXX, 0) ;
+ SetPower(0);
+ SetESTOP();
+ break;
+
+ default:
+ break;
+ }
+
+ // Send keep-alive reply
+ SendBuffer(USART_STEER_COM, steerReply, sizeof(steerReply));
+
+ // Reset the pwm timout to avoid stopping motors
+ ResetTimeout();
+
+ return TRUE;
+}
+
+int16_t max(int16_t a, int16_t b){
+ return (a >= b)? a : b;
+}
diff --git a/HoverBoardGigaDevice/Src/it.c b/HUGS/Src/it.c
similarity index 75%
rename from HoverBoardGigaDevice/Src/it.c
rename to HUGS/Src/it.c
index 5a60db36..48c0142a 100644
--- a/HoverBoardGigaDevice/Src/it.c
+++ b/HUGS/Src/it.c
@@ -1,274 +1,244 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/it.h"
-#include "../Inc/defines.h"
-#include "../Inc/config.h"
-#include "../Inc/bldc.h"
-#include "../Inc/led.h"
-#include "../Inc/commsMasterSlave.h"
-#include "../Inc/commsSteering.h"
-#include "../Inc/commsBluetooth.h"
-
-uint32_t msTicks;
-uint32_t timeoutCounter_ms = 0;
-FlagStatus timedOut = SET;
-
-#ifdef SLAVE
-uint32_t hornCounter_ms = 0;
-#endif
-
-extern int32_t steer;
-extern int32_t speed;
-extern FlagStatus activateWeakening;
-extern FlagStatus beepsBackwards;
-
-//----------------------------------------------------------------------------
-// SysTick_Handler
-//----------------------------------------------------------------------------
-void SysTick_Handler(void)
-{
- msTicks++;
-}
-
-//----------------------------------------------------------------------------
-// Resets the timeout to zero
-//----------------------------------------------------------------------------
-void ResetTimeout(void)
-{
- timeoutCounter_ms = 0;
-}
-
-//----------------------------------------------------------------------------
-// Timer13_Update_Handler
-// Is called when upcouting of timer13 is finished and the UPDATE-flag is set
-// -> period of timer13 running with 1kHz -> interrupt every 1ms
-//----------------------------------------------------------------------------
-void TIMER13_IRQHandler(void)
-{
- if (timeoutCounter_ms > TIMEOUT_MS)
- {
- // First timeout reset all process values
- if (timedOut == RESET)
- {
-#ifdef MASTER
- steer = 0;
- speed = 0;
- beepsBackwards = RESET;
-#endif
-#ifdef SLAVE
- SetPWM(0);
-#endif
- }
-
- timedOut = SET;
- }
- else
- {
- timedOut = RESET;
- timeoutCounter_ms++;
- }
-
-#ifdef SLAVE
- if (hornCounter_ms >= 2000)
- {
- // Avoid horn to be activated longer than 2 seconds
- SetUpperLEDMaster(RESET);
- }
- else if (hornCounter_ms < 2000)
- {
- hornCounter_ms++;
- }
-
- // Update LED program
- CalculateLEDProgram();
-#endif
-
- // Clear timer update interrupt flag
- timer_interrupt_flag_clear(TIMER13, TIMER_INT_UP);
-}
-
-//----------------------------------------------------------------------------
-// Timer0_Update_Handler
-// Is called when upcouting of timer0 is finished and the UPDATE-flag is set
-// AND when downcouting of timer0 is finished and the UPDATE-flag is set
-// -> pwm of timer0 running with 16kHz -> interrupt every 31,25us
-//----------------------------------------------------------------------------
-void TIMER0_BRK_UP_TRG_COM_IRQHandler(void)
-{
- // Start ADC conversion
- adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
-
- // Clear timer update interrupt flag
- timer_interrupt_flag_clear(TIMER_BLDC, TIMER_INT_UP);
-}
-
-//----------------------------------------------------------------------------
-// This function handles DMA_Channel0_IRQHandler interrupt
-// Is called, when the ADC scan sequence is finished
-// -> ADC is triggered from timer0-update-interrupt -> every 31,25us
-//----------------------------------------------------------------------------
-void DMA_Channel0_IRQHandler(void)
-{
- // Calculate motor PWMs
- CalculateBLDC();
-
- #ifdef SLAVE
- // Calculates RGB LED
- CalculateLEDPWM();
- #endif
-
- if (dma_interrupt_flag_get(DMA_CH0, DMA_INT_FLAG_FTF))
- {
- dma_interrupt_flag_clear(DMA_CH0, DMA_INT_FLAG_FTF);
- }
-}
-
-
-//----------------------------------------------------------------------------
-// This function handles DMA_Channel1_2_IRQHandler interrupt
-// Is asynchronously called when USART0 RX finished
-//----------------------------------------------------------------------------
-void DMA_Channel1_2_IRQHandler(void)
-{
- // USART steer/bluetooth RX
- if (dma_interrupt_flag_get(DMA_CH2, DMA_INT_FLAG_FTF))
- {
-#ifdef MASTER
- // Update USART steer input mechanism
- UpdateUSARTSteerInput();
-#endif
-#ifdef SLAVE
- // Update USART bluetooth input mechanism
- UpdateUSARTBluetoothInput();
-#endif
- dma_interrupt_flag_clear(DMA_CH2, DMA_INT_FLAG_FTF);
- }
-}
-
-
-//----------------------------------------------------------------------------
-// This function handles DMA_Channel3_4_IRQHandler interrupt
-// Is asynchronously called when USART_SLAVE RX finished
-//----------------------------------------------------------------------------
-void DMA_Channel3_4_IRQHandler(void)
-{
- // USART master slave RX
- if (dma_interrupt_flag_get(DMA_CH4, DMA_INT_FLAG_FTF))
- {
- // Update USART master slave input mechanism
- UpdateUSARTMasterSlaveInput();
-
- dma_interrupt_flag_clear(DMA_CH4, DMA_INT_FLAG_FTF);
- }
-}
-
-//----------------------------------------------------------------------------
-// Returns number of milliseconds since system start
-//----------------------------------------------------------------------------
-uint32_t millis()
-{
- return msTicks;
-}
-
-//----------------------------------------------------------------------------
-// Delays number of tick Systicks (happens every 10 ms)
-//----------------------------------------------------------------------------
-void Delay (uint32_t dlyTicks)
-{
- uint32_t curTicks;
-
- curTicks = msTicks;
- while ((msTicks - curTicks) < dlyTicks)
- {
- __NOP();
- }
-}
-
-//----------------------------------------------------------------------------
-// This function handles Non maskable interrupt.
-//----------------------------------------------------------------------------
-void NMI_Handler(void)
-{
-}
-
-//----------------------------------------------------------------------------
-// This function handles Hard fault interrupt.
-//----------------------------------------------------------------------------
-void HardFault_Handler(void)
-{
- while(1) {}
-}
-
-//----------------------------------------------------------------------------
-// This function handles Memory management fault.
-//----------------------------------------------------------------------------
-void MemManage_Handler(void)
-{
- while(1) {}
-}
-
-//----------------------------------------------------------------------------
-// This function handles Prefetch fault, memory access fault.
-//----------------------------------------------------------------------------
-void BusFault_Handler(void)
-{
- while(1) {}
-}
-
-//----------------------------------------------------------------------------
-// This function handles Undefined instruction or illegal state.
-//----------------------------------------------------------------------------
-void UsageFault_Handler(void)
-{
- while(1) {}
-}
-
-//----------------------------------------------------------------------------
-// This function handles System service call via SWI instruction.
-//----------------------------------------------------------------------------
-void SVC_Handler(void)
-{
-}
-
-//----------------------------------------------------------------------------
-// This function handles Debug monitor.
-//----------------------------------------------------------------------------
-void DebugMon_Handler(void)
-{
-}
-
-//----------------------------------------------------------------------------
-// This function handles Pendable request for system service.
-//----------------------------------------------------------------------------
-void PendSV_Handler(void)
-{
-}
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+#include "../Inc/it.h"
+#include "../Inc/defines.h"
+#include "../Inc/config.h"
+#include "../Inc/bldc.h"
+#include "../Inc/led.h"
+#include "../Inc/commsHUGS.h"
+#include "../Inc/commsSteering.h"
+
+uint32_t msTicks = 0;
+uint32_t sysTicks = 0;
+uint32_t driveSafeMs = 0;
+FlagStatus timedOut = SET;
+bool msToggle = FALSE;
+
+extern FlagStatus activateWeakening;
+extern int16_t HUGS_WatchDog;
+
+//----------------------------------------------------------------------------
+// SysTick_Handler (Fires every 10 mS)
+//----------------------------------------------------------------------------
+void SysTick_Handler(void)
+{
+ sysTicks++;
+}
+
+//----------------------------------------------------------------------------
+// Resets the drive timeout to zero
+//----------------------------------------------------------------------------
+void ResetTimeout(void)
+{
+ driveSafeMs = 0;
+}
+
+//----------------------------------------------------------------------------
+// Timer13_Update_Handler
+// Is called when upcouting of timer13 is finished and the UPDATE-flag is set
+// -> period of timer13 running with 2kHz -> interrupt every 500 uS
+//----------------------------------------------------------------------------
+void TIMER13_IRQHandler(void)
+{
+ msToggle = msToggle ? FALSE : TRUE;
+
+ if (msToggle) {
+ msTicks++;
+
+ // Update speed value
+ CalculateSpeed();
+
+ if (driveSafeMs > HUGS_WatchDog)
+ {
+ // First timeout reset all process values
+ if (timedOut == RESET)
+ {
+ SetPower(0);
+ }
+
+ timedOut = SET;
+ }
+ else
+ {
+ timedOut = RESET;
+ driveSafeMs++;
+ }
+ }
+
+ // Clear timer update interrupt flag
+ timer_interrupt_flag_clear(TIMER13, TIMER_INT_UP);
+}
+
+//----------------------------------------------------------------------------
+// Timer0_Update_Handler
+// Is called when upcouting of timer0 is finished and the UPDATE-flag is set
+// AND when downcouting of timer0 is finished and the UPDATE-flag is set
+// -> pwm of timer0 running with 16kHz -> interrupt every 31,25us
+//----------------------------------------------------------------------------
+void TIMER0_BRK_UP_TRG_COM_IRQHandler(void)
+{
+ // Start ADC conversion
+ adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+
+ // Clear timer update interrupt flag
+ timer_interrupt_flag_clear(TIMER_BLDC, TIMER_INT_UP);
+}
+
+//----------------------------------------------------------------------------
+// This function handles DMA_Channel0_IRQHandler interrupt
+// Is called, when the ADC scan sequence is finished
+// -> ADC is triggered from timer0-update-interrupt -> every 31,25us
+//----------------------------------------------------------------------------
+void DMA_Channel0_IRQHandler(void)
+{
+ // Calculate motor PWMs
+ CalculateBLDC();
+
+ #ifdef SLAVE
+ // Calculates RGB LED
+ CalculateLEDPWM();
+ #endif
+
+ if (dma_interrupt_flag_get(DMA_CH0, DMA_INT_FLAG_FTF))
+ {
+ dma_interrupt_flag_clear(DMA_CH0, DMA_INT_FLAG_FTF);
+ }
+}
+
+
+//----------------------------------------------------------------------------
+// This function handles DMA_Channel1_2_IRQHandler interrupt
+// Is asynchronously called when USART0 RX finished
+//----------------------------------------------------------------------------
+void DMA_Channel1_2_IRQHandler(void)
+{
+ // USART steer/bluetooth RX
+ if (dma_interrupt_flag_get(DMA_CH2, DMA_INT_FLAG_FTF))
+ {
+ // Update USART steer input mechanism
+ UpdateUSARTSteerInput();
+ dma_interrupt_flag_clear(DMA_CH2, DMA_INT_FLAG_FTF);
+ }
+}
+
+
+//----------------------------------------------------------------------------
+// This function handles DMA_Channel3_4_IRQHandler interrupt
+// Is asynchronously called when USART_SLAVE RX finished
+//----------------------------------------------------------------------------
+void DMA_Channel3_4_IRQHandler(void)
+{
+ // USART master slave RX
+ if (dma_interrupt_flag_get(DMA_CH4, DMA_INT_FLAG_FTF))
+ {
+ // Update USART master slave input mechanism
+ UpdateUSARTHUGSInput();
+ dma_interrupt_flag_clear(DMA_CH4, DMA_INT_FLAG_FTF);
+ }
+}
+
+//----------------------------------------------------------------------------
+// Returns number of milliseconds since system start
+//----------------------------------------------------------------------------
+uint32_t millis()
+{
+ return msTicks;
+}
+
+//----------------------------------------------------------------------------
+// Delays number of mSec
+//----------------------------------------------------------------------------
+void Delay (uint32_t dlyTicks)
+{
+ uint32_t curTicks;
+
+ curTicks = msTicks;
+ while ((msTicks - curTicks) < dlyTicks)
+ {
+ __NOP();
+ }
+}
+
+//----------------------------------------------------------------------------
+// This function handles Non maskable interrupt.
+//----------------------------------------------------------------------------
+void NMI_Handler(void)
+{
+}
+
+//----------------------------------------------------------------------------
+// This function handles Hard fault interrupt.
+//----------------------------------------------------------------------------
+void HardFault_Handler(void)
+{
+ while(1) {}
+}
+
+//----------------------------------------------------------------------------
+// This function handles Memory management fault.
+//----------------------------------------------------------------------------
+void MemManage_Handler(void)
+{
+ while(1) {}
+}
+
+//----------------------------------------------------------------------------
+// This function handles Prefetch fault, memory access fault.
+//----------------------------------------------------------------------------
+void BusFault_Handler(void)
+{
+ while(1) {}
+}
+
+//----------------------------------------------------------------------------
+// This function handles Undefined instruction or illegal state.
+//----------------------------------------------------------------------------
+void UsageFault_Handler(void)
+{
+ while(1) {}
+}
+
+//----------------------------------------------------------------------------
+// This function handles System service call via SWI instruction.
+//----------------------------------------------------------------------------
+void SVC_Handler(void)
+{
+}
+
+//----------------------------------------------------------------------------
+// This function handles Debug monitor.
+//----------------------------------------------------------------------------
+void DebugMon_Handler(void)
+{
+}
+
+//----------------------------------------------------------------------------
+// This function handles Pendable request for system service.
+//----------------------------------------------------------------------------
+void PendSV_Handler(void)
+{
+}
diff --git a/HoverBoardGigaDevice/Src/led.c b/HUGS/Src/led.c
similarity index 90%
rename from HoverBoardGigaDevice/Src/led.c
rename to HUGS/Src/led.c
index 1270ed57..4ecbf9b4 100644
--- a/HoverBoardGigaDevice/Src/led.c
+++ b/HUGS/Src/led.c
@@ -1,393 +1,388 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/led.h"
-#include "../Inc/defines.h"
-
-// Only slave has LED mechanism
-#ifdef SLAVE
-
-// Lookuptable for brightness
-static unsigned char su8BrightnessTable[64] =
- {0,0,1,1,1,2,2,2,2,2,2,3,3,3,3,4,4,4,5,5,6,
- 6,7,8,8,9,10,11,12,13,14,15,17,18,20,22,24,
- 26,28,31,34,37,40,44,48,52,57,62,68,74,81,89,
- 97,106,116,126,138,150,164,179,196,214,234,255};
-
-// Variables for RGB output
-uint8_t counter_Red = 0;
-uint8_t counter_Green = 0;
-uint8_t counter_Blue = 0;
-uint8_t setValue_Red = 0;
-uint8_t setValue_Green = 0;
-uint8_t setValue_Blue = 0;
-
-// Variables for HSB calculation
-static uint16_t hueValue = 0;
-static uint8_t saturationValue = 128;
-static uint8_t brightnessValue = 63;
-
-// Variable for LED-program
-static LED_PROGRAM sLEDProgram = LED_OFF;
-
-// Variables for effects
-static uint16_t speedFading = 150; // Fading-Delay
-static uint16_t speedBlink = 1274; // Blink-Delay
-static uint16_t speedStrobe = 40; // Strobe-Delay
-
-// Counter for effects
-static uint16_t fadingCounter = 0;
-static uint16_t blinkCounter = 0;
-static uint16_t strobeCounter = 0;
-static FlagStatus strobeToggle = RESET;
-
-// Prototypes
-uint8_t HSBtoRed(uint16_t hue, uint8_t sat);
-uint8_t HSBtoGreen(uint16_t hue, uint8_t sat);
-uint8_t HSBtoBlue(uint16_t hue, uint8_t sat);
-
-//----------------------------------------------------------------------------
-// Update RGB LED output with 16kHz
-//----------------------------------------------------------------------------
-void CalculateLEDPWM(void)
-{
- // Upcounting with overflow
- counter_Red++;
- counter_Green++;
- counter_Blue++;
-
- // Set LEDs
- gpio_bit_write(UPPER_LED_PORT, UPPER_LED_PIN, counter_Red >= setValue_Red ? RESET : SET);
- gpio_bit_write(LOWER_LED_PORT, LOWER_LED_PIN, counter_Green >= setValue_Green ? RESET : SET);
- gpio_bit_write(MOSFET_OUT_PORT, MOSFET_OUT_PIN, counter_Blue >= setValue_Blue ? RESET : SET);
-}
-
-//----------------------------------------------------------------------------
-// Update RGB LED program every 1ms
-//----------------------------------------------------------------------------
-void CalculateLEDProgram(void)
-{
- if (GetRGBProgram() == LED_HSB_FADE)
- {
- fadingCounter++;
- if(fadingCounter >= GetSpeedFading())
- {
- fadingCounter = 0;
- SetHSBHue(GetHSBHue()+1);
- }
- }
- if (GetRGBProgram() == LED_HSB_BLINK)
- {
- blinkCounter++;
- if(blinkCounter >= GetSpeedBlink())
- {
- blinkCounter = 0;
- SetHSBHue(GetHSBHue()+50);
- }
- }
- if(GetRGBProgram() == LED_HSB_STROBE)
- {
- strobeCounter++;
- if(strobeCounter >= GetSpeedStrobe())
- {
- strobeCounter = 0;
- if(strobeToggle == RESET)
- {
- strobeToggle = SET;
- SetHSBBrightness(0);
- }
- else
- {
- strobeToggle = RESET;
- SetHSBBrightness(63);
- }
- }
- }
-}
-
-//----------------------------------------------------------------------------
-// Sets LED program
-//----------------------------------------------------------------------------
-void SetRGBProgram(LED_PROGRAM Program)
-{
- // Check program count
- if(!(Program < COUNT_PROGRAMS))
- {
- Program = LED_OFF;
- }
-
- // Save program for later
- sLEDProgram = Program;
-
- switch(Program)
- {
- case LED_HSB:
- case LED_HSB_BLINK:
- case LED_HSB_FADE:
- case LED_HSB_STROBE:
- SetHSBHue(hueValue);
- SetHSBSaturation(saturationValue);
- SetHSBBrightness(brightnessValue);
- break;
- case LED_OFF:
- default:
- setValue_Red = 0;
- setValue_Green = 0;
- setValue_Blue = 0;
- break;
- }
-}
-
-//----------------------------------------------------------------------------
-// Gets LED program
-//----------------------------------------------------------------------------
-LED_PROGRAM GetRGBProgram(void)
-{
- return sLEDProgram;
-}
-
-//----------------------------------------------------------------------------
-// Sets hue from 0-764
-//----------------------------------------------------------------------------
-void SetHSBHue(uint16_t hue)
-{
- uint8_t brightness = 0;
-
- // Save hue for later
- if (hue > 764)
- {
- hueValue = 0;
- }
- else
- {
- hueValue = hue;
- }
-
- // Calculate brightness with the lookuptable
- brightness = su8BrightnessTable[brightnessValue]; //input: 0..63 output: 0..255
-
- // Calculate RGB values
- setValue_Red = ((brightness + 1) * HSBtoRed(hueValue, saturationValue)) >> 8;
- setValue_Green = ((brightness + 1) * HSBtoGreen(hueValue, saturationValue)) >> 8;
- setValue_Blue = ((brightness + 1) * HSBtoBlue(hueValue, saturationValue)) >> 8;
-}
-
-//----------------------------------------------------------------------------
-// Gets hue from 0-764
-//----------------------------------------------------------------------------
-uint16_t GetHSBHue(void)
-{
- return hueValue;
-}
-
-//----------------------------------------------------------------------------
-// Sets saturation from 0-128
-//----------------------------------------------------------------------------
-void SetHSBSaturation(uint8_t saturation)
-{
- uint8_t brightness = 0;
-
- // Save Saturation for later
- saturationValue = MAX(saturation, 128);
-
- // Calculate brightness with the lookuptable
- brightness = su8BrightnessTable[brightnessValue]; //input: 0..63 output: 0..255
-
- // Calculate RGB values
- setValue_Red = ((brightness + 1) * HSBtoRed(hueValue, saturationValue)) >> 8;
- setValue_Green = ((brightness + 1) * HSBtoGreen(hueValue, saturationValue)) >> 8;
- setValue_Blue = ((brightness + 1) * HSBtoBlue(hueValue, saturationValue)) >> 8;
-}
-
-//----------------------------------------------------------------------------
-// Gets saturation from 0-128
-//----------------------------------------------------------------------------
-uint8_t GetHSBSaturation(void)
-{
- return saturationValue;
-}
-
-//----------------------------------------------------------------------------
-// Sets brightness from 0-63
-//----------------------------------------------------------------------------
-void SetHSBBrightness(uint8_t brightnessVal)
-{
- uint8_t brightness = 0;
-
- // Save brightness for later
- brightnessValue = MAX(brightnessVal, 63);
-
- // Calculate brightness with the lookuptable
- brightness = su8BrightnessTable[brightnessValue]; //input: 0..63 output: 0..255
-
- // Calculate RGB values
- setValue_Red = ((brightness + 1) * HSBtoRed(hueValue, saturationValue)) >> 8;
- setValue_Green = ((brightness + 1) * HSBtoGreen(hueValue, saturationValue)) >> 8;
- setValue_Blue = ((brightness + 1) * HSBtoBlue(hueValue, saturationValue)) >> 8;
-}
-
-//----------------------------------------------------------------------------
-// Gets brightness from 0-63
-//----------------------------------------------------------------------------
-uint8_t GetHSBBrightness(void)
-{
- return brightnessValue;
-}
-
-//----------------------------------------------------------------------------
-// Sets fading speed from 200-1000
-//----------------------------------------------------------------------------
-void SetSpeedFading(uint16_t speed)
-{
- speedFading = CLAMP(speed, 200, 1000);
-}
-
-//----------------------------------------------------------------------------
-// Gets fading speed from 200-1000
-//----------------------------------------------------------------------------
-uint16_t GetSpeedFading(void)
-{
- return speedFading;
-}
-
-//----------------------------------------------------------------------------
-// Sets blink speed from 700-2400
-//----------------------------------------------------------------------------
-void SetSpeedBlink(uint16_t speed)
-{
- speedBlink = CLAMP(speed, 700, 2400);
-}
-
-//----------------------------------------------------------------------------
-// Gets blink speed from 700-2400
-//----------------------------------------------------------------------------
-uint16_t GetSpeedBlink(void)
-{
- return speedBlink;
-}
-
-//----------------------------------------------------------------------------
-// Sets strobe speed from 0-1000
-//----------------------------------------------------------------------------
-void SetSpeedStrobe(uint16_t speed)
-{
- speedStrobe = CLAMP(speed, 40, 400);
-}
-
-//----------------------------------------------------------------------------
-// Gets strobe speed from 0-1000
-//----------------------------------------------------------------------------
-uint16_t GetSpeedStrobe(void)
-{
- return speedStrobe;
-}
-
-//----------------------------------------------------------------------------
-// Hue to red
-//----------------------------------------------------------------------------
-uint8_t HSBtoRed(uint16_t hue, uint8_t sat)
-{
- unsigned char red_val = 0;
-
- if (hue > 764)
- {
- hue = 0;
- }
- if (hue < 255)
- {
- red_val = (10880 - sat * (hue - 170)) >> 7;
- }
- else if (hue < 510)
- {
- red_val = (10880 - sat * 85) >> 7;
- }
- else
- {
- red_val = (10880 - sat * (595 - hue)) >> 7;
- }
-
- return red_val;
-}
-
-//----------------------------------------------------------------------------
-// Hue to green
-//----------------------------------------------------------------------------
-uint8_t HSBtoGreen(uint16_t hue, uint8_t sat)
-{
- uint8_t green_val = 0;
-
- if (hue > 764)
- {
- hue = 0;
- }
- if (hue < 255)
- {
- green_val = (10880 - sat * (85 - hue)) >> 7;
- }
- else if (hue < 510)
- {
- green_val = (10880 - sat * (hue - 425)) >> 7;
- }
- else
- {
- green_val = (10880 - sat * 85) >> 7;
- }
-
- return green_val;
-}
-
-//----------------------------------------------------------------------------
-// Hue to blue
-//----------------------------------------------------------------------------
-uint8_t HSBtoBlue(uint16_t hue, uint8_t sat)
-{
- uint8_t blue_val = 0;
-
- if (hue > 764)
- {
- hue = 0;
- }
- if (hue < 255)
- {
- blue_val = (10880 - sat * 85) >> 7;
- }
- else if (hue < 510)
- {
- blue_val = (10880 - sat * (340 - hue)) >> 7;
- }
- else
- {
- blue_val = (10880 - sat * (hue - 680)) >> 7;
- }
-
- return blue_val;
-}
-#endif
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+#include "../Inc/led.h"
+#include "../Inc/defines.h"
+
+// Only slave has LED mechanism
+#ifdef SLAVE
+
+// Lookuptable for brightness
+static unsigned char su8BrightnessTable[64] =
+ {0,0,1,1,1,2,2,2,2,2,2,3,3,3,3,4,4,4,5,5,6,
+ 6,7,8,8,9,10,11,12,13,14,15,17,18,20,22,24,
+ 26,28,31,34,37,40,44,48,52,57,62,68,74,81,89,
+ 97,106,116,126,138,150,164,179,196,214,234,255};
+
+// Variables for RGB output
+uint8_t counter_Red = 0;
+uint8_t counter_Green = 0;
+uint8_t counter_Blue = 0;
+uint8_t setValue_Red = 0;
+uint8_t setValue_Green = 0;
+uint8_t setValue_Blue = 0;
+
+// Variables for HSB calculation
+static uint16_t hueValue = 0;
+static uint8_t saturationValue = 128;
+static uint8_t brightnessValue = 63;
+
+// Variable for LED-program
+static LED_PROGRAM sLEDProgram = LED_OFF;
+
+// Variables for effects
+static uint16_t speedFading = 150; // Fading-Delay
+static uint16_t speedBlink = 1274; // Blink-Delay
+static uint16_t speedStrobe = 40; // Strobe-Delay
+
+// Counter for effects
+static uint16_t fadingCounter = 0;
+static uint16_t blinkCounter = 0;
+static uint16_t strobeCounter = 0;
+static FlagStatus strobeToggle = RESET;
+
+// Prototypes
+uint8_t HSBtoRed(uint16_t hue, uint8_t sat);
+uint8_t HSBtoGreen(uint16_t hue, uint8_t sat);
+uint8_t HSBtoBlue(uint16_t hue, uint8_t sat);
+
+//----------------------------------------------------------------------------
+// Update RGB LED output with 16kHz
+//----------------------------------------------------------------------------
+void CalculateLEDPWM(void)
+{
+ // Upcounting with overflow
+ counter_Red++;
+ counter_Green++;
+ counter_Blue++;
+
+ // Set LEDs
+ gpio_bit_write(UPPER_LED_PORT, UPPER_LED_PIN, counter_Red >= setValue_Red ? RESET : SET);
+ gpio_bit_write(LOWER_LED_PORT, LOWER_LED_PIN, counter_Green >= setValue_Green ? RESET : SET);
+ gpio_bit_write(MOSFET_OUT_PORT, MOSFET_OUT_PIN, counter_Blue >= setValue_Blue ? RESET : SET);
+}
+
+//----------------------------------------------------------------------------
+// Update RGB LED program every 1ms
+//----------------------------------------------------------------------------
+void CalculateLEDProgram(void)
+{
+ if (GetRGBProgram() == LED_HSB_FADE)
+ {
+ fadingCounter++;
+ if(fadingCounter >= GetSpeedFading())
+ {
+ fadingCounter = 0;
+ SetHSBHue(GetHSBHue()+1);
+ }
+ }
+ if (GetRGBProgram() == LED_HSB_BLINK)
+ {
+ blinkCounter++;
+ if(blinkCounter >= GetSpeedBlink())
+ {
+ blinkCounter = 0;
+ SetHSBHue(GetHSBHue()+50);
+ }
+ }
+ if(GetRGBProgram() == LED_HSB_STROBE)
+ {
+ strobeCounter++;
+ if(strobeCounter >= GetSpeedStrobe())
+ {
+ strobeCounter = 0;
+ if(strobeToggle == RESET)
+ {
+ strobeToggle = SET;
+ SetHSBBrightness(0);
+ }
+ else
+ {
+ strobeToggle = RESET;
+ SetHSBBrightness(63);
+ }
+ }
+ }
+}
+
+//----------------------------------------------------------------------------
+// Sets LED program
+//----------------------------------------------------------------------------
+void SetRGBProgram(LED_PROGRAM Program)
+{
+ // Check program count
+ if(!(Program < COUNT_PROGRAMS))
+ {
+ Program = LED_OFF;
+ }
+
+ // Save program for later
+ sLEDProgram = Program;
+
+ switch(Program)
+ {
+ case LED_HSB:
+ case LED_HSB_BLINK:
+ case LED_HSB_FADE:
+ case LED_HSB_STROBE:
+ SetHSBHue(hueValue);
+ SetHSBSaturation(saturationValue);
+ SetHSBBrightness(brightnessValue);
+ break;
+ case LED_OFF:
+ default:
+ setValue_Red = 0;
+ setValue_Green = 0;
+ setValue_Blue = 0;
+ break;
+ }
+}
+
+//----------------------------------------------------------------------------
+// Gets LED program
+//----------------------------------------------------------------------------
+LED_PROGRAM GetRGBProgram(void)
+{
+ return sLEDProgram;
+}
+
+//----------------------------------------------------------------------------
+// Sets hue from 0-764
+//----------------------------------------------------------------------------
+void SetHSBHue(uint16_t hue)
+{
+ uint8_t brightness = 0;
+
+ // Save hue for later
+ if (hue > 764)
+ {
+ hueValue = 0;
+ }
+ else
+ {
+ hueValue = hue;
+ }
+
+ // Calculate brightness with the lookuptable
+ brightness = su8BrightnessTable[brightnessValue]; //input: 0..63 output: 0..255
+
+ // Calculate RGB values
+ setValue_Red = ((brightness + 1) * HSBtoRed(hueValue, saturationValue)) >> 8;
+ setValue_Green = ((brightness + 1) * HSBtoGreen(hueValue, saturationValue)) >> 8;
+ setValue_Blue = ((brightness + 1) * HSBtoBlue(hueValue, saturationValue)) >> 8;
+}
+
+//----------------------------------------------------------------------------
+// Gets hue from 0-764
+//----------------------------------------------------------------------------
+uint16_t GetHSBHue(void)
+{
+ return hueValue;
+}
+
+//----------------------------------------------------------------------------
+// Sets saturation from 0-128
+//----------------------------------------------------------------------------
+void SetHSBSaturation(uint8_t saturation)
+{
+ uint8_t brightness = 0;
+
+ // Save Saturation for later
+ saturationValue = MAX(saturation, 128);
+
+ // Calculate brightness with the lookuptable
+ brightness = su8BrightnessTable[brightnessValue]; //input: 0..63 output: 0..255
+
+ // Calculate RGB values
+ setValue_Red = ((brightness + 1) * HSBtoRed(hueValue, saturationValue)) >> 8;
+ setValue_Green = ((brightness + 1) * HSBtoGreen(hueValue, saturationValue)) >> 8;
+ setValue_Blue = ((brightness + 1) * HSBtoBlue(hueValue, saturationValue)) >> 8;
+}
+
+//----------------------------------------------------------------------------
+// Gets saturation from 0-128
+//----------------------------------------------------------------------------
+uint8_t GetHSBSaturation(void)
+{
+ return saturationValue;
+}
+
+//----------------------------------------------------------------------------
+// Sets brightness from 0-63
+//----------------------------------------------------------------------------
+void SetHSBBrightness(uint8_t brightnessVal)
+{
+ uint8_t brightness = 0;
+
+ // Save brightness for later
+ brightnessValue = MAX(brightnessVal, 63);
+
+ // Calculate brightness with the lookuptable
+ brightness = su8BrightnessTable[brightnessValue]; //input: 0..63 output: 0..255
+
+ // Calculate RGB values
+ setValue_Red = ((brightness + 1) * HSBtoRed(hueValue, saturationValue)) >> 8;
+ setValue_Green = ((brightness + 1) * HSBtoGreen(hueValue, saturationValue)) >> 8;
+ setValue_Blue = ((brightness + 1) * HSBtoBlue(hueValue, saturationValue)) >> 8;
+}
+
+//----------------------------------------------------------------------------
+// Gets brightness from 0-63
+//----------------------------------------------------------------------------
+uint8_t GetHSBBrightness(void)
+{
+ return brightnessValue;
+}
+
+//----------------------------------------------------------------------------
+// Sets fading speed from 200-1000
+//----------------------------------------------------------------------------
+void SetSpeedFading(uint16_t speed)
+{
+ speedFading = CLAMP(speed, 200, 1000);
+}
+
+//----------------------------------------------------------------------------
+// Gets fading speed from 200-1000
+//----------------------------------------------------------------------------
+uint16_t GetSpeedFading(void)
+{
+ return speedFading;
+}
+
+//----------------------------------------------------------------------------
+// Sets blink speed from 700-2400
+//----------------------------------------------------------------------------
+void SetSpeedBlink(uint16_t speed)
+{
+ speedBlink = CLAMP(speed, 700, 2400);
+}
+
+//----------------------------------------------------------------------------
+// Gets blink speed from 700-2400
+//----------------------------------------------------------------------------
+uint16_t GetSpeedBlink(void)
+{
+ return speedBlink;
+}
+
+//----------------------------------------------------------------------------
+// Sets strobe speed from 0-1000
+//----------------------------------------------------------------------------
+void SetSpeedStrobe(uint16_t speed)
+{
+ speedStrobe = CLAMP(speed, 40, 400);
+}
+
+//----------------------------------------------------------------------------
+// Gets strobe speed from 0-1000
+//----------------------------------------------------------------------------
+uint16_t GetSpeedStrobe(void)
+{
+ return speedStrobe;
+}
+
+//----------------------------------------------------------------------------
+// Hue to red
+//----------------------------------------------------------------------------
+uint8_t HSBtoRed(uint16_t hue, uint8_t sat)
+{
+ unsigned char red_val = 0;
+
+ if (hue > 764)
+ {
+ hue = 0;
+ }
+ if (hue < 255)
+ {
+ red_val = (10880 - sat * (hue - 170)) >> 7;
+ }
+ else if (hue < 510)
+ {
+ red_val = (10880 - sat * 85) >> 7;
+ }
+ else
+ {
+ red_val = (10880 - sat * (595 - hue)) >> 7;
+ }
+
+ return red_val;
+}
+
+//----------------------------------------------------------------------------
+// Hue to green
+//----------------------------------------------------------------------------
+uint8_t HSBtoGreen(uint16_t hue, uint8_t sat)
+{
+ uint8_t green_val = 0;
+
+ if (hue > 764)
+ {
+ hue = 0;
+ }
+ if (hue < 255)
+ {
+ green_val = (10880 - sat * (85 - hue)) >> 7;
+ }
+ else if (hue < 510)
+ {
+ green_val = (10880 - sat * (hue - 425)) >> 7;
+ }
+ else
+ {
+ green_val = (10880 - sat * 85) >> 7;
+ }
+
+ return green_val;
+}
+
+//----------------------------------------------------------------------------
+// Hue to blue
+//----------------------------------------------------------------------------
+uint8_t HSBtoBlue(uint16_t hue, uint8_t sat)
+{
+ uint8_t blue_val = 0;
+
+ if (hue > 764)
+ {
+ hue = 0;
+ }
+ if (hue < 255)
+ {
+ blue_val = (10880 - sat * 85) >> 7;
+ }
+ else if (hue < 510)
+ {
+ blue_val = (10880 - sat * (340 - hue)) >> 7;
+ }
+ else
+ {
+ blue_val = (10880 - sat * (hue - 680)) >> 7;
+ }
+
+ return blue_val;
+}
+#endif
diff --git a/HUGS/Src/main.c b/HUGS/Src/main.c
new file mode 100644
index 00000000..4e931a52
--- /dev/null
+++ b/HUGS/Src/main.c
@@ -0,0 +1,228 @@
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* Overall Project Revision History
+* Rev Date Description
+* 2.0 5/8/2020 Switch to HUGS 2.0 (Little Endian)
+* Change speeds over to mm/s
+* 2.1 5/14/2020 Added Motion Response.
+*/
+
+#define ARM_MATH_CM3
+
+#include "gd32f1x0.h"
+
+#include "../Inc/setup.h"
+#include "../Inc/defines.h"
+#include "../Inc/config.h"
+#include "../Inc/it.h"
+#include "../Inc/bldc.h"
+#include "../Inc/comms.h"
+#include "../Inc/commsHUGS.h"
+#include "../Inc/commsSteering.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "string.h"
+#include
+
+FlagStatus activateWeakening = RESET; // global variable for weakening
+
+extern uint16_t batteryVoltagemV; // global variable for battery voltage
+
+extern FlagStatus timedOut; // Timeoutvariable set by timeout timer
+
+extern bool HUGS_ESTOP;
+
+extern uint8_t buzzerFreq; // global variable for the buzzer pitch. can be 1, 2, 3, 4, 5, 6, 7...
+extern uint8_t buzzerPattern; // global variable for the buzzer pattern. can be 1, 2, 3, 4, 5, 6, 7...
+
+uint32_t inactivityTimer = 0; // Inactivity counter ms From last command
+
+void ShowBatteryState(uint32_t pin);
+void ShutOff(void);
+
+//----------------------------------------------------------------------------
+// MAIN function
+//----------------------------------------------------------------------------
+int main (void)
+{
+ //SystemClock_Config();
+ SystemCoreClockUpdate();
+ SysTick_Config(SystemCoreClock / 100);
+
+ // Init watchdog
+ if (Watchdog_init() == ERROR)
+ {
+ // If an error accours with watchdog initialization do not start device
+ while(1);
+ }
+
+ // Init Interrupts
+ Interrupt_init();
+
+ // Init timeout timer
+ TimeoutTimer_init();
+
+ // Init GPIOs
+ GPIO_init();
+
+ // Activate self hold direct after GPIO-init
+ gpio_bit_write(SELF_HOLD_PORT, SELF_HOLD_PIN, SET);
+
+ // Init usart master slave
+ USART_HUGS_init();
+
+ // Init ADC
+ ADC_init();
+
+ // Init PWM
+ PWM_init();
+
+ // Device has 1,6 seconds to do all the initialization
+ // afterwards watchdog will be fired
+ fwdgt_counter_reload();
+
+ // Init usart steer/bluetooth
+ USART_Steer_COM_init();
+
+ // Startup-Sound. This plays for 1 second
+ buzzerFreq = 7;
+ Delay(1000);
+ fwdgt_counter_reload();
+ buzzerFreq = 0;
+
+ // Wait until button is pressed ????
+ while (gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN))
+ {
+ // Reload watchdog while button is pressed
+ fwdgt_counter_reload();
+ }
+
+ while(1)
+ {
+ // Shut device if ESTOP requested or when button is pressed
+ if (HUGS_ESTOP || gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN))
+ {
+ ShutOff();
+ }
+
+ // Shut off device after INACTIVITY_TIMEOUT in minutes
+ if (inactivityTimer++ > INACTIVITY_COUNTER)
+ {
+ ShutOff();
+ } else if (inactivityTimer > INACTIVITY_WARNING) {
+ buzzerFreq = 8;
+ buzzerPattern = 8;
+ } else {
+
+ // Show green battery symbol when battery level BAT_LOW_LVL1 is reached
+ if (batteryVoltagemV > BAT_LOW_LVL1_MV)
+ {
+ // Show green battery light
+ ShowBatteryState(LED_GREEN);
+ buzzerFreq = 0;
+ }
+ // Make silent sound and show orange battery symbol when battery level BAT_LOW_LVL2 is reached
+ else if (batteryVoltagemV > BAT_LOW_LVL2_MV && batteryVoltagemV < BAT_LOW_LVL1_MV)
+ {
+ // Show orange battery light
+ ShowBatteryState(LED_ORANGE);
+ buzzerFreq = 5;
+ buzzerPattern = 8;
+ }
+ // Make even more sound and show red battery symbol when battery level BAT_LOW_DEAD is reached
+ else if (batteryVoltagemV > BAT_LOW_DEAD_MV && batteryVoltagemV < BAT_LOW_LVL2_MV)
+ {
+ // Show red battery light
+ ShowBatteryState(LED_RED);
+ buzzerFreq = 5;
+ buzzerPattern = 1;
+ }
+ else
+ {
+ ShutOff();
+ }
+ }
+
+
+ Delay(DELAY_IN_MAIN_LOOP);
+
+ // Reload watchdog (watchdog fires after 1,6 seconds)
+ fwdgt_counter_reload();
+ }
+}
+
+//----------------------------------------------------------------------------
+// Turns the device off
+//----------------------------------------------------------------------------
+void ShutOff(void)
+{
+ int index = 0;
+ buzzerPattern = 0;
+
+ // Reload watchdog (watchdog fires after 1,6 seconds)
+ fwdgt_counter_reload();
+
+ // Ensure that drive is off and estop status set.
+ SetPWM(0);
+ HUGS_ESTOP = TRUE;
+ SetEnable(RESET);
+ SendHUGSReply(); // Transfer ESTOP to Controller
+ SendHUGSCmd(XXX, 0); // Tell possible slave to stop as well.
+
+
+ // Play shutdown sound
+ for (index = 0; index < 8; index++)
+ {
+ buzzerFreq = index;
+ Delay(100);
+ }
+ buzzerFreq = 0;
+
+ // Disable usart
+ usart_deinit(USART_HUGS);
+
+ // Turn off power
+ gpio_bit_write(SELF_HOLD_PORT, SELF_HOLD_PIN, RESET);
+ while(1)
+ {
+ // Reload watchdog until device is off
+ fwdgt_counter_reload();
+ }
+}
+
+//----------------------------------------------------------------------------
+// Shows the battery state on the LEDs
+//----------------------------------------------------------------------------
+void ShowBatteryState(uint32_t pin)
+{
+ gpio_bit_write(LED_GREEN_PORT, LED_GREEN, pin == LED_GREEN ? SET : RESET);
+ gpio_bit_write(LED_ORANGE_PORT, LED_ORANGE, pin == LED_ORANGE ? SET : RESET);
+ gpio_bit_write(LED_RED_PORT, LED_RED, pin == LED_RED ? SET : RESET);
+}
+
+
+void resetInactivityTimer(void) {
+ inactivityTimer = 0;
+}
diff --git a/HoverBoardGigaDevice/Src/setup.c b/HUGS/Src/setup.c
similarity index 87%
rename from HoverBoardGigaDevice/Src/setup.c
rename to HUGS/Src/setup.c
index 80fbaef5..430cb780 100644
--- a/HoverBoardGigaDevice/Src/setup.c
+++ b/HUGS/Src/setup.c
@@ -1,497 +1,490 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/setup.h"
-#include "../Inc/defines.h"
-#include "../Inc/config.h"
-#include "../Inc/it.h"
-
-#define TIMEOUT_FREQ 1000
-
-// timeout timer parameter structs
-timer_parameter_struct timeoutTimer_paramter_struct;
-
-// PWM timer Parameter structs
-timer_parameter_struct timerBldc_paramter_struct;
-timer_break_parameter_struct timerBldc_break_parameter_struct;
-timer_oc_parameter_struct timerBldc_oc_parameter_struct;
-
-// DMA (USART) structs
-dma_parameter_struct dma_init_struct_usart;
-uint8_t usartMasterSlave_rx_buf[USART_MASTERSLAVE_RX_BUFFERSIZE];
-uint8_t usartSteer_COM_rx_buf[USART_STEER_COM_RX_BUFFERSIZE];
-
-// DMA (ADC) structs
-dma_parameter_struct dma_init_struct_adc;
-extern adc_buf_t adc_buffer;
-
-//----------------------------------------------------------------------------
-// Initializes the interrupts
-//----------------------------------------------------------------------------
-void Interrupt_init(void)
-{
- // Set IRQ priority configuration
- nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0);
-}
-
-//----------------------------------------------------------------------------
-// Initializes the watchdog
-//----------------------------------------------------------------------------
-ErrStatus Watchdog_init(void)
-{
- // Check if the system has resumed from FWDGT reset
- if (RESET != rcu_flag_get(RCU_FLAG_FWDGTRST))
- {
- // FWDGTRST flag set
- rcu_all_reset_flag_clear();
- }
-
- // Clock source is IRC40K (40 kHz)
- // Prescaler is 16
- // Reload value is 4096 (0x0FFF)
- // Watchdog fires after 1638.4 ms
- if (fwdgt_config(0x0FFF, FWDGT_PSC_DIV16) != SUCCESS ||
- fwdgt_window_value_config(0x0FFF) != SUCCESS)
- {
- return ERROR;
- }
-
- // Enable free watchdog timer
- fwdgt_enable();
-
- return SUCCESS;
-}
-
-//----------------------------------------------------------------------------
-// Initializes the timeout timer
-//----------------------------------------------------------------------------
-void TimeoutTimer_init(void)
-{
- // Enable timer clock
- rcu_periph_clock_enable(RCU_TIMER13);
-
- // Initial deinitialize of the timer
- timer_deinit(TIMER13);
-
- // Set up the basic parameter struct for the timer
- // Update event will be fired every 1ms
- timeoutTimer_paramter_struct.counterdirection = TIMER_COUNTER_UP;
- timeoutTimer_paramter_struct.prescaler = 0;
- timeoutTimer_paramter_struct.alignedmode = TIMER_COUNTER_CENTER_DOWN;
- timeoutTimer_paramter_struct.period = 72000000 / 2 / TIMEOUT_FREQ;
- timeoutTimer_paramter_struct.clockdivision = TIMER_CKDIV_DIV1;
- timeoutTimer_paramter_struct.repetitioncounter = 0;
- timer_auto_reload_shadow_disable(TIMER13);
- timer_init(TIMER13, &timeoutTimer_paramter_struct);
-
- // Enable TIMER_INT_UP interrupt and set priority
- nvic_irq_enable(TIMER13_IRQn, 0, 0);
- timer_interrupt_enable(TIMER13, TIMER_INT_UP);
-
- // Enable timer
- timer_enable(TIMER13);
-}
-
-//----------------------------------------------------------------------------
-// Initializes the GPIOs
-//----------------------------------------------------------------------------
-void GPIO_init(void)
-{
- // Enable all GPIO clocks
- rcu_periph_clock_enable(RCU_GPIOA);
- rcu_periph_clock_enable(RCU_GPIOB);
- rcu_periph_clock_enable(RCU_GPIOC);
- rcu_periph_clock_enable(RCU_GPIOF);
-
- // Init green LED
- gpio_mode_set(LED_GREEN_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LED_GREEN);
- gpio_output_options_set(LED_GREEN_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LED_GREEN);
-
- // Init red LED
- gpio_mode_set(LED_RED_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LED_RED);
- gpio_output_options_set(LED_RED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LED_RED);
-
- // Init orange LED
- gpio_mode_set(LED_ORANGE_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LED_ORANGE);
- gpio_output_options_set(LED_ORANGE_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LED_ORANGE);
-
- // Init UPPER/LOWER LED
- gpio_mode_set(UPPER_LED_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,UPPER_LED_PIN);
- gpio_output_options_set(UPPER_LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, UPPER_LED_PIN);
- gpio_mode_set(LOWER_LED_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LOWER_LED_PIN);
- gpio_output_options_set(LOWER_LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LOWER_LED_PIN);
-
- // Init mosfet output
- gpio_mode_set(MOSFET_OUT_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MOSFET_OUT_PIN);
- gpio_output_options_set(MOSFET_OUT_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, MOSFET_OUT_PIN);
-
- // Init HAL input
- gpio_mode_set(HALL_A_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_A_PIN);
- gpio_mode_set(HALL_B_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_B_PIN);
- gpio_mode_set(HALL_C_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_C_PIN);
-
- // Init USART_MASTERSLAVE
- gpio_mode_set(USART_MASTERSLAVE_TX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_MASTERSLAVE_TX_PIN);
- gpio_mode_set(USART_MASTERSLAVE_RX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_MASTERSLAVE_RX_PIN);
- gpio_output_options_set(USART_MASTERSLAVE_TX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_MASTERSLAVE_TX_PIN);
- gpio_output_options_set(USART_MASTERSLAVE_RX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_MASTERSLAVE_RX_PIN);
- gpio_af_set(USART_MASTERSLAVE_TX_PORT, GPIO_AF_1, USART_MASTERSLAVE_TX_PIN);
- gpio_af_set(USART_MASTERSLAVE_RX_PORT, GPIO_AF_1, USART_MASTERSLAVE_RX_PIN);
-
- // Init ADC pins
- gpio_mode_set(VBATT_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, VBATT_PIN);
- gpio_mode_set(CURRENT_DC_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, CURRENT_DC_PIN);
- gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_6);
- gpio_mode_set(GPIOB, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0);
-
- // Init debug pin
- gpio_mode_set(DEBUG_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, DEBUG_PIN);
- gpio_output_options_set(DEBUG_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, DEBUG_PIN);
-
- // Init emergency shutdown pin
- gpio_mode_set(TIMER_BLDC_EMERGENCY_SHUTDOWN_PORT , GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_EMERGENCY_SHUTDOWN_PIN);
- gpio_af_set(TIMER_BLDC_EMERGENCY_SHUTDOWN_PORT, GPIO_AF_2, TIMER_BLDC_EMERGENCY_SHUTDOWN_PIN);
-
- // Init PWM output Pins (Configure as alternate functions, push-pull, no pullup)
- gpio_mode_set(TIMER_BLDC_GH_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_GH_PIN);
- gpio_mode_set(TIMER_BLDC_BH_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_BH_PIN);
- gpio_mode_set(TIMER_BLDC_YH_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_YH_PIN);
- gpio_mode_set(TIMER_BLDC_GL_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_GL_PIN);
- gpio_mode_set(TIMER_BLDC_BL_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_BL_PIN);
- gpio_mode_set(TIMER_BLDC_YL_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_YL_PIN);
-
- gpio_output_options_set(TIMER_BLDC_GH_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_GH_PIN);
- gpio_output_options_set(TIMER_BLDC_BH_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_BH_PIN);
- gpio_output_options_set(TIMER_BLDC_YH_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_YH_PIN);
- gpio_output_options_set(TIMER_BLDC_GL_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_GL_PIN);
- gpio_output_options_set(TIMER_BLDC_BL_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_BL_PIN);
- gpio_output_options_set(TIMER_BLDC_YL_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_YL_PIN);
-
- gpio_af_set(TIMER_BLDC_GH_PORT, GPIO_AF_2, TIMER_BLDC_GH_PIN);
- gpio_af_set(TIMER_BLDC_BH_PORT, GPIO_AF_2, TIMER_BLDC_BH_PIN);
- gpio_af_set(TIMER_BLDC_YH_PORT, GPIO_AF_2, TIMER_BLDC_YH_PIN);
- gpio_af_set(TIMER_BLDC_GL_PORT, GPIO_AF_2, TIMER_BLDC_GL_PIN);
- gpio_af_set(TIMER_BLDC_BL_PORT, GPIO_AF_2, TIMER_BLDC_BL_PIN);
- gpio_af_set(TIMER_BLDC_YL_PORT, GPIO_AF_2, TIMER_BLDC_YL_PIN);
-
- // Init self hold
- gpio_mode_set(SELF_HOLD_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SELF_HOLD_PIN);
- gpio_output_options_set(SELF_HOLD_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, SELF_HOLD_PIN);
-
- // Init USART0
- gpio_mode_set(USART_STEER_COM_TX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_STEER_COM_TX_PIN);
- gpio_mode_set(USART_STEER_COM_RX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_STEER_COM_RX_PIN);
- gpio_output_options_set(USART_STEER_COM_TX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_STEER_COM_TX_PIN);
- gpio_output_options_set(USART_STEER_COM_RX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_STEER_COM_RX_PIN);
- gpio_af_set(USART_STEER_COM_TX_PORT, GPIO_AF_0, USART_STEER_COM_TX_PIN);
- gpio_af_set(USART_STEER_COM_RX_PORT, GPIO_AF_0, USART_STEER_COM_RX_PIN);
-
-#ifdef MASTER
- // Init buzzer
- gpio_mode_set(BUZZER_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, BUZZER_PIN);
- gpio_output_options_set(BUZZER_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, BUZZER_PIN);
-
- // Init button
- gpio_mode_set(BUTTON_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, BUTTON_PIN);
-
- // Init charge state
- gpio_mode_set(CHARGE_STATE_PORT, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, CHARGE_STATE_PIN);
-#endif
-}
-
-//----------------------------------------------------------------------------
-// Initializes the PWM
-//----------------------------------------------------------------------------
-void PWM_init(void)
-{
- // Enable timer clock
- rcu_periph_clock_enable(RCU_TIMER_BLDC);
-
- // Initial deinitialize of the timer
- timer_deinit(TIMER_BLDC);
-
- // Set up the basic parameter struct for the timer
- timerBldc_paramter_struct.counterdirection = TIMER_COUNTER_UP;
- timerBldc_paramter_struct.prescaler = 0;
- timerBldc_paramter_struct.alignedmode = TIMER_COUNTER_CENTER_DOWN;
- timerBldc_paramter_struct.period = 72000000 / 2 / PWM_FREQ;
- timerBldc_paramter_struct.clockdivision = TIMER_CKDIV_DIV1;
- timerBldc_paramter_struct.repetitioncounter = 0;
- timer_auto_reload_shadow_disable(TIMER_BLDC);
-
- // Initialize timer with basic parameter struct
- timer_init(TIMER_BLDC, &timerBldc_paramter_struct);
-
- // Deactivate output channel fastmode
- timer_channel_output_fast_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_OC_FAST_DISABLE);
- timer_channel_output_fast_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_OC_FAST_DISABLE);
- timer_channel_output_fast_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_OC_FAST_DISABLE);
-
- // Deactivate output channel shadow function
- timer_channel_output_shadow_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_OC_SHADOW_DISABLE);
- timer_channel_output_shadow_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_OC_SHADOW_DISABLE);
- timer_channel_output_shadow_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_OC_SHADOW_DISABLE);
-
- // Set output channel PWM type to PWM1
- timer_channel_output_mode_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_OC_MODE_PWM1);
- timer_channel_output_mode_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_OC_MODE_PWM1);
- timer_channel_output_mode_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_OC_MODE_PWM1);
-
- // Initialize pulse length with value 0 (pulse duty factor = zero)
- timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, 0);
- timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, 0);
- timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, 0);
-
- // Set up the output channel parameter struct
- timerBldc_oc_parameter_struct.ocpolarity = TIMER_OC_POLARITY_HIGH;
- timerBldc_oc_parameter_struct.ocnpolarity = TIMER_OCN_POLARITY_LOW;
- timerBldc_oc_parameter_struct.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
- timerBldc_oc_parameter_struct.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH;
-
- // Configure all three output channels with the output channel parameter struct
- timer_channel_output_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, &timerBldc_oc_parameter_struct);
- timer_channel_output_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, &timerBldc_oc_parameter_struct);
- timer_channel_output_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, &timerBldc_oc_parameter_struct);
-
- // Set up the break parameter struct
- timerBldc_break_parameter_struct.runoffstate = TIMER_ROS_STATE_ENABLE;
- timerBldc_break_parameter_struct.ideloffstate = TIMER_IOS_STATE_DISABLE;
- timerBldc_break_parameter_struct.protectmode = TIMER_CCHP_PROT_OFF;
- timerBldc_break_parameter_struct.deadtime = DEAD_TIME;
- timerBldc_break_parameter_struct.breakstate = TIMER_BREAK_ENABLE;
- timerBldc_break_parameter_struct.breakpolarity = TIMER_BREAK_POLARITY_LOW;
- timerBldc_break_parameter_struct.outputautostate = TIMER_OUTAUTO_ENABLE;
-
- // Configure the timer with the break parameter struct
- timer_break_config(TIMER_BLDC, &timerBldc_break_parameter_struct);
-
- // Disable until all channels are set for PWM output
- timer_disable(TIMER_BLDC);
-
- // Enable all three channels for PWM output
- timer_channel_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_CCX_ENABLE);
- timer_channel_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_CCX_ENABLE);
- timer_channel_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_CCX_ENABLE);
-
- // Enable all three complemenary channels for PWM output
- timer_channel_complementary_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_CCXN_ENABLE);
- timer_channel_complementary_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_CCXN_ENABLE);
- timer_channel_complementary_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_CCXN_ENABLE);
-
- // Enable TIMER_INT_UP interrupt and set priority
- nvic_irq_enable(TIMER0_BRK_UP_TRG_COM_IRQn, 0, 0);
- timer_interrupt_enable(TIMER_BLDC, TIMER_INT_UP);
-
- // Enable the timer and start PWM
- timer_enable(TIMER_BLDC);
-}
-
-//----------------------------------------------------------------------------
-// Initializes the ADC
-//----------------------------------------------------------------------------
-void ADC_init(void)
-{
- // Enable ADC and DMA clock
- rcu_periph_clock_enable(RCU_ADC);
- rcu_periph_clock_enable(RCU_DMA);
-
- // Configure ADC clock (APB2 clock is DIV1 -> 72MHz, ADC clock is DIV6 -> 12MHz)
- rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
-
- // Interrupt channel 0 enable
- nvic_irq_enable(DMA_Channel0_IRQn, 1, 0);
-
- // Initialize DMA channel 0 for ADC
- dma_deinit(DMA_CH0);
- dma_init_struct_adc.direction = DMA_PERIPHERAL_TO_MEMORY;
- dma_init_struct_adc.memory_addr = (uint32_t)&adc_buffer;
- dma_init_struct_adc.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
- dma_init_struct_adc.memory_width = DMA_MEMORY_WIDTH_16BIT;
- dma_init_struct_adc.number = 2;
- dma_init_struct_adc.periph_addr = (uint32_t)&ADC_RDATA;
- dma_init_struct_adc.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
- dma_init_struct_adc.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
- dma_init_struct_adc.priority = DMA_PRIORITY_ULTRA_HIGH;
- dma_init(DMA_CH0, dma_init_struct_adc);
-
- // Configure DMA mode
- dma_circulation_enable(DMA_CH0);
- dma_memory_to_memory_disable(DMA_CH0);
-
- // Enable DMA transfer complete interrupt
- dma_interrupt_enable(DMA_CH0, DMA_CHXCTL_FTFIE);
-
- // At least clear number of remaining data to be transferred by the DMA
- dma_transfer_number_config(DMA_CH0, 2);
-
- // Enable DMA channel 0
- dma_channel_enable(DMA_CH0);
-
- adc_channel_length_config(ADC_REGULAR_CHANNEL, 2);
- adc_regular_channel_config(0, VBATT_CHANNEL, ADC_SAMPLETIME_13POINT5);
- adc_regular_channel_config(1, CURRENT_DC_CHANNEL, ADC_SAMPLETIME_13POINT5);
- adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
-
- // Set trigger of ADC
- adc_external_trigger_config(ADC_REGULAR_CHANNEL, ENABLE);
- adc_external_trigger_source_config(ADC_REGULAR_CHANNEL, ADC_EXTTRIG_REGULAR_SWRCST);
-
- // Disable the temperature sensor, Vrefint and vbat channel
- adc_tempsensor_vrefint_disable();
- adc_vbat_disable();
-
- // ADC analog watchdog disable
- adc_watchdog_disable();
-
- // Enable ADC (must be before calibration)
- adc_enable();
-
- // Calibrate ADC values
- adc_calibration_enable();
-
- // Enable DMA request
- adc_dma_mode_enable();
-
- // Set ADC to scan mode
- adc_special_function_config(ADC_SCAN_MODE, ENABLE);
-}
-
-//----------------------------------------------------------------------------
-// Initializes the usart master slave
-//----------------------------------------------------------------------------
-void USART_MasterSlave_init(void)
-{
- // Enable ADC and DMA clock
- rcu_periph_clock_enable(RCU_USART1);
- rcu_periph_clock_enable(RCU_DMA);
-
- // Init USART for 115200 baud, 8N1
- usart_baudrate_set(USART_MASTERSLAVE, 115200);
- usart_parity_config(USART_MASTERSLAVE, USART_PM_NONE);
- usart_word_length_set(USART_MASTERSLAVE, USART_WL_8BIT);
- usart_stop_bit_set(USART_MASTERSLAVE, USART_STB_1BIT);
- usart_oversample_config(USART_MASTERSLAVE, USART_OVSMOD_16);
-
- // Enable both transmitter and receiver
- usart_transmit_config(USART_MASTERSLAVE, USART_TRANSMIT_ENABLE);
- usart_receive_config(USART_MASTERSLAVE, USART_RECEIVE_ENABLE);
-
- // Enable USART
- usart_enable(USART_MASTERSLAVE);
-
- // Interrupt channel 3/4 enable
- nvic_irq_enable(DMA_Channel3_4_IRQn, 2, 0);
-
- // Initialize DMA channel 4 for USART_SLAVE RX
- dma_deinit(DMA_CH4);
- dma_init_struct_usart.direction = DMA_PERIPHERAL_TO_MEMORY;
- dma_init_struct_usart.memory_addr = (uint32_t)usartMasterSlave_rx_buf;
- dma_init_struct_usart.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
- dma_init_struct_usart.memory_width = DMA_MEMORY_WIDTH_8BIT;
- dma_init_struct_usart.number = USART_MASTERSLAVE_RX_BUFFERSIZE;
- dma_init_struct_usart.periph_addr = USART_MASTERSLAVE_DATA_RX_ADDRESS;
- dma_init_struct_usart.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
- dma_init_struct_usart.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
- dma_init_struct_usart.priority = DMA_PRIORITY_ULTRA_HIGH;
- dma_init(DMA_CH4, dma_init_struct_usart);
-
- // Configure DMA mode
- dma_circulation_enable(DMA_CH4);
- dma_memory_to_memory_disable(DMA_CH4);
-
- // USART DMA enable for transmission and receive
- usart_dma_receive_config(USART_MASTERSLAVE, USART_DENR_ENABLE);
-
- // Enable DMA transfer complete interrupt
- dma_interrupt_enable(DMA_CH4, DMA_CHXCTL_FTFIE);
-
- // At least clear number of remaining data to be transferred by the DMA
- dma_transfer_number_config(DMA_CH4, 1);
-
- // Enable dma receive channel
- dma_channel_enable(DMA_CH4);
-}
-
-//----------------------------------------------------------------------------
-// Initializes the usart steer/bluetooth
-//----------------------------------------------------------------------------
-void USART_Steer_COM_init(void)
-{
- // Enable ADC and DMA clock
- rcu_periph_clock_enable(RCU_USART0);
- rcu_periph_clock_enable(RCU_DMA);
-
- // Init USART for 19200 baud, 8N1
- usart_baudrate_set(USART_STEER_COM, 19200);
- usart_parity_config(USART_STEER_COM, USART_PM_NONE);
- usart_word_length_set(USART_STEER_COM, USART_WL_8BIT);
- usart_stop_bit_set(USART_STEER_COM, USART_STB_1BIT);
- usart_oversample_config(USART_STEER_COM, USART_OVSMOD_16);
-
- // Enable both transmitter and receiver
- usart_transmit_config(USART_STEER_COM, USART_TRANSMIT_ENABLE);
- usart_receive_config(USART_STEER_COM, USART_RECEIVE_ENABLE);
-
- // Enable USART
- usart_enable(USART_STEER_COM);
-
- // Interrupt channel 1/2 enable
- nvic_irq_enable(DMA_Channel1_2_IRQn, 2, 0);
-
- // Initialize DMA channel 2 for USART_STEER_COM RX
- dma_deinit(DMA_CH2);
- dma_init_struct_usart.direction = DMA_PERIPHERAL_TO_MEMORY;
- dma_init_struct_usart.memory_addr = (uint32_t)usartSteer_COM_rx_buf;
- dma_init_struct_usart.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
- dma_init_struct_usart.memory_width = DMA_MEMORY_WIDTH_8BIT;
- dma_init_struct_usart.number = USART_STEER_COM_RX_BUFFERSIZE;
- dma_init_struct_usart.periph_addr = USART_STEER_COM_DATA_RX_ADDRESS;
- dma_init_struct_usart.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
- dma_init_struct_usart.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
- dma_init_struct_usart.priority = DMA_PRIORITY_ULTRA_HIGH;
- dma_init(DMA_CH2, dma_init_struct_usart);
-
- // Configure DMA mode
- dma_circulation_enable(DMA_CH2);
- dma_memory_to_memory_disable(DMA_CH2);
-
- // USART DMA enable for transmission and receive
- usart_dma_receive_config(USART_STEER_COM, USART_DENR_ENABLE);
-
- // Enable DMA transfer complete interrupt
- dma_interrupt_enable(DMA_CH2, DMA_CHXCTL_FTFIE);
-
- // At least clear number of remaining data to be transferred by the DMA
- dma_transfer_number_config(DMA_CH2, 1);
-
- // Enable dma receive channel
- dma_channel_enable(DMA_CH2);
-}
+/*
+* This file is part of the Hoverboard Utility Gateway System (HUGS) project.
+*
+* The HUGS project goal is to enable Hoverboards, or Hoverboard drive components
+* to be re-purposed to provide low-cost mobility to other systems, such
+* as assistive devices for the disabled, general purpose robots or other
+* labor saving devices.
+*
+* Copyright (C) 2020 Phil Malone
+* Copyright (C) 2018 Florian Staeblein
+* Copyright (C) 2018 Jakob Broemauer
+* Copyright (C) 2018 Kai Liebich
+* Copyright (C) 2018 Christoph Lehnert
+*
+* This program is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include "gd32f1x0.h"
+#include "../Inc/setup.h"
+#include "../Inc/defines.h"
+#include "../Inc/config.h"
+#include "../Inc/it.h"
+
+#define TIMEOUT_FREQ 1000
+
+// timeout timer parameter structs
+timer_parameter_struct timeoutTimer_paramter_struct;
+
+// PWM timer Parameter structs
+timer_parameter_struct timerBldc_paramter_struct;
+timer_break_parameter_struct timerBldc_break_parameter_struct;
+timer_oc_parameter_struct timerBldc_oc_parameter_struct;
+
+// DMA (USART) structs
+dma_parameter_struct dma_init_struct_usart;
+uint8_t usartHUGS_rx_buf[USART_HUGS_RX_BUFFERSIZE];
+uint8_t usartSteer_COM_rx_buf[USART_STEER_COM_RX_BUFFERSIZE];
+
+// DMA (ADC) structs
+dma_parameter_struct dma_init_struct_adc;
+extern adc_buf_t adc_buffer;
+
+//----------------------------------------------------------------------------
+// Initializes the interrupts
+//----------------------------------------------------------------------------
+void Interrupt_init(void)
+{
+ // Set IRQ priority configuration
+ nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0);
+}
+
+//----------------------------------------------------------------------------
+// Initializes the watchdog
+//----------------------------------------------------------------------------
+ErrStatus Watchdog_init(void)
+{
+ // Check if the system has resumed from FWDGT reset
+ if (RESET != rcu_flag_get(RCU_FLAG_FWDGTRST))
+ {
+ // FWDGTRST flag set
+ rcu_all_reset_flag_clear();
+ }
+
+ // Clock source is IRC40K (40 kHz)
+ // Prescaler is 16
+ // Reload value is 4096 (0x0FFF)
+ // Watchdog fires after 1638.4 ms
+ if (fwdgt_config(0x0FFF, FWDGT_PSC_DIV16) != SUCCESS ||
+ fwdgt_window_value_config(0x0FFF) != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ // Enable free watchdog timer
+ fwdgt_enable();
+
+ return SUCCESS;
+}
+
+//----------------------------------------------------------------------------
+// Initializes the timeout timer
+//----------------------------------------------------------------------------
+void TimeoutTimer_init(void)
+{
+ // Enable timer clock
+ rcu_periph_clock_enable(RCU_TIMER13);
+
+ // Initial deinitialize of the timer
+ timer_deinit(TIMER13);
+
+ // Set up the basic parameter struct for the timer
+ // Update event will be fired every 1ms
+ timeoutTimer_paramter_struct.counterdirection = TIMER_COUNTER_UP;
+ timeoutTimer_paramter_struct.prescaler = 0;
+ timeoutTimer_paramter_struct.alignedmode = TIMER_COUNTER_CENTER_DOWN;
+ timeoutTimer_paramter_struct.period = 72000000 / 2 / TIMEOUT_FREQ;
+ timeoutTimer_paramter_struct.clockdivision = TIMER_CKDIV_DIV1;
+ timeoutTimer_paramter_struct.repetitioncounter = 0;
+ timer_auto_reload_shadow_disable(TIMER13);
+ timer_init(TIMER13, &timeoutTimer_paramter_struct);
+
+ // Enable TIMER_INT_UP interrupt and set priority
+ nvic_irq_enable(TIMER13_IRQn, 0, 0);
+ timer_interrupt_enable(TIMER13, TIMER_INT_UP);
+
+ // Enable timer
+ timer_enable(TIMER13);
+}
+
+//----------------------------------------------------------------------------
+// Initializes the GPIOs
+//----------------------------------------------------------------------------
+void GPIO_init(void)
+{
+ // Enable all GPIO clocks
+ rcu_periph_clock_enable(RCU_GPIOA);
+ rcu_periph_clock_enable(RCU_GPIOB);
+ rcu_periph_clock_enable(RCU_GPIOC);
+ rcu_periph_clock_enable(RCU_GPIOF);
+
+ // Init green LED
+ gpio_mode_set(LED_GREEN_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LED_GREEN);
+ gpio_output_options_set(LED_GREEN_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LED_GREEN);
+
+ // Init red LED
+ gpio_mode_set(LED_RED_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LED_RED);
+ gpio_output_options_set(LED_RED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LED_RED);
+
+ // Init orange LED
+ gpio_mode_set(LED_ORANGE_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LED_ORANGE);
+ gpio_output_options_set(LED_ORANGE_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LED_ORANGE);
+
+ // Init UPPER/LOWER LED
+ gpio_mode_set(UPPER_LED_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,UPPER_LED_PIN);
+ gpio_output_options_set(UPPER_LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, UPPER_LED_PIN);
+ gpio_mode_set(LOWER_LED_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,LOWER_LED_PIN);
+ gpio_output_options_set(LOWER_LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, LOWER_LED_PIN);
+
+ // Init mosfet output
+ gpio_mode_set(MOSFET_OUT_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MOSFET_OUT_PIN);
+ gpio_output_options_set(MOSFET_OUT_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, MOSFET_OUT_PIN);
+
+ // Init HAL input
+ gpio_mode_set(HALL_A_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_A_PIN);
+ gpio_mode_set(HALL_B_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_B_PIN);
+ gpio_mode_set(HALL_C_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, HALL_C_PIN);
+
+ // Init USART_HUGS
+ gpio_mode_set(USART_HUGS_TX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_HUGS_TX_PIN);
+ gpio_mode_set(USART_HUGS_RX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_HUGS_RX_PIN);
+ gpio_output_options_set(USART_HUGS_TX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_HUGS_TX_PIN);
+ gpio_output_options_set(USART_HUGS_RX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_HUGS_RX_PIN);
+ gpio_af_set(USART_HUGS_TX_PORT, GPIO_AF_1, USART_HUGS_TX_PIN);
+ gpio_af_set(USART_HUGS_RX_PORT, GPIO_AF_1, USART_HUGS_RX_PIN);
+
+ // Init ADC pins
+ gpio_mode_set(VBATT_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, VBATT_PIN);
+ gpio_mode_set(CURRENT_DC_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, CURRENT_DC_PIN);
+ gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_6);
+ gpio_mode_set(GPIOB, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0);
+
+ // Init debug pin
+ gpio_mode_set(DEBUG_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, DEBUG_PIN);
+ gpio_output_options_set(DEBUG_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, DEBUG_PIN);
+
+ // Init emergency shutdown pin
+ gpio_mode_set(TIMER_BLDC_EMERGENCY_SHUTDOWN_PORT , GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_EMERGENCY_SHUTDOWN_PIN);
+ gpio_af_set(TIMER_BLDC_EMERGENCY_SHUTDOWN_PORT, GPIO_AF_2, TIMER_BLDC_EMERGENCY_SHUTDOWN_PIN);
+
+ // Init PWM output Pins (Configure as alternate functions, push-pull, no pullup)
+ gpio_mode_set(TIMER_BLDC_GH_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_GH_PIN);
+ gpio_mode_set(TIMER_BLDC_BH_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_BH_PIN);
+ gpio_mode_set(TIMER_BLDC_YH_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_YH_PIN);
+ gpio_mode_set(TIMER_BLDC_GL_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_GL_PIN);
+ gpio_mode_set(TIMER_BLDC_BL_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_BL_PIN);
+ gpio_mode_set(TIMER_BLDC_YL_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, TIMER_BLDC_YL_PIN);
+
+ gpio_output_options_set(TIMER_BLDC_GH_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_GH_PIN);
+ gpio_output_options_set(TIMER_BLDC_BH_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_BH_PIN);
+ gpio_output_options_set(TIMER_BLDC_YH_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_YH_PIN);
+ gpio_output_options_set(TIMER_BLDC_GL_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_GL_PIN);
+ gpio_output_options_set(TIMER_BLDC_BL_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_BL_PIN);
+ gpio_output_options_set(TIMER_BLDC_YL_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, TIMER_BLDC_YL_PIN);
+
+ gpio_af_set(TIMER_BLDC_GH_PORT, GPIO_AF_2, TIMER_BLDC_GH_PIN);
+ gpio_af_set(TIMER_BLDC_BH_PORT, GPIO_AF_2, TIMER_BLDC_BH_PIN);
+ gpio_af_set(TIMER_BLDC_YH_PORT, GPIO_AF_2, TIMER_BLDC_YH_PIN);
+ gpio_af_set(TIMER_BLDC_GL_PORT, GPIO_AF_2, TIMER_BLDC_GL_PIN);
+ gpio_af_set(TIMER_BLDC_BL_PORT, GPIO_AF_2, TIMER_BLDC_BL_PIN);
+ gpio_af_set(TIMER_BLDC_YL_PORT, GPIO_AF_2, TIMER_BLDC_YL_PIN);
+
+ // Init self hold
+ gpio_mode_set(SELF_HOLD_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SELF_HOLD_PIN);
+ gpio_output_options_set(SELF_HOLD_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, SELF_HOLD_PIN);
+
+ // Init USART0
+ gpio_mode_set(USART_STEER_COM_TX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_STEER_COM_TX_PIN);
+ gpio_mode_set(USART_STEER_COM_RX_PORT , GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART_STEER_COM_RX_PIN);
+ gpio_output_options_set(USART_STEER_COM_TX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_STEER_COM_TX_PIN);
+ gpio_output_options_set(USART_STEER_COM_RX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART_STEER_COM_RX_PIN);
+ gpio_af_set(USART_STEER_COM_TX_PORT, GPIO_AF_0, USART_STEER_COM_TX_PIN);
+ gpio_af_set(USART_STEER_COM_RX_PORT, GPIO_AF_0, USART_STEER_COM_RX_PIN);
+
+ // Init buzzer
+ gpio_mode_set(BUZZER_PORT , GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, BUZZER_PIN);
+ gpio_output_options_set(BUZZER_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, BUZZER_PIN);
+
+ // Init button
+ gpio_mode_set(BUTTON_PORT , GPIO_MODE_INPUT, GPIO_PUPD_NONE, BUTTON_PIN);
+
+ // Init charge state
+ gpio_mode_set(CHARGE_STATE_PORT, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, CHARGE_STATE_PIN);
+}
+
+//----------------------------------------------------------------------------
+// Initializes the PWM
+//----------------------------------------------------------------------------
+void PWM_init(void)
+{
+ // Enable timer clock
+ rcu_periph_clock_enable(RCU_TIMER_BLDC);
+
+ // Initial deinitialize of the timer
+ timer_deinit(TIMER_BLDC);
+
+ // Set up the basic parameter struct for the timer
+ timerBldc_paramter_struct.counterdirection = TIMER_COUNTER_UP;
+ timerBldc_paramter_struct.prescaler = 0;
+ timerBldc_paramter_struct.alignedmode = TIMER_COUNTER_CENTER_DOWN;
+ timerBldc_paramter_struct.period = 72000000 / 2 / PWM_FREQ;
+ timerBldc_paramter_struct.clockdivision = TIMER_CKDIV_DIV1;
+ timerBldc_paramter_struct.repetitioncounter = 0;
+ timer_auto_reload_shadow_disable(TIMER_BLDC);
+
+ // Initialize timer with basic parameter struct
+ timer_init(TIMER_BLDC, &timerBldc_paramter_struct);
+
+ // Deactivate output channel fastmode
+ timer_channel_output_fast_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_OC_FAST_DISABLE);
+ timer_channel_output_fast_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_OC_FAST_DISABLE);
+ timer_channel_output_fast_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_OC_FAST_DISABLE);
+
+ // Deactivate output channel shadow function
+ timer_channel_output_shadow_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_OC_SHADOW_DISABLE);
+ timer_channel_output_shadow_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_OC_SHADOW_DISABLE);
+ timer_channel_output_shadow_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_OC_SHADOW_DISABLE);
+
+ // Set output channel PWM type to PWM1
+ timer_channel_output_mode_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_OC_MODE_PWM1);
+ timer_channel_output_mode_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_OC_MODE_PWM1);
+ timer_channel_output_mode_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_OC_MODE_PWM1);
+
+ // Initialize pulse length with value 0 (pulse duty factor = zero)
+ timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, 0);
+ timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, 0);
+ timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, 0);
+
+ // Set up the output channel parameter struct
+ timerBldc_oc_parameter_struct.ocpolarity = TIMER_OC_POLARITY_HIGH;
+ timerBldc_oc_parameter_struct.ocnpolarity = TIMER_OCN_POLARITY_LOW;
+ timerBldc_oc_parameter_struct.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
+ timerBldc_oc_parameter_struct.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH;
+
+ // Configure all three output channels with the output channel parameter struct
+ timer_channel_output_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, &timerBldc_oc_parameter_struct);
+ timer_channel_output_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, &timerBldc_oc_parameter_struct);
+ timer_channel_output_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, &timerBldc_oc_parameter_struct);
+
+ // Set up the break parameter struct
+ timerBldc_break_parameter_struct.runoffstate = TIMER_ROS_STATE_ENABLE;
+ timerBldc_break_parameter_struct.ideloffstate = TIMER_IOS_STATE_DISABLE;
+ timerBldc_break_parameter_struct.protectmode = TIMER_CCHP_PROT_OFF;
+ timerBldc_break_parameter_struct.deadtime = DEAD_TIME;
+ timerBldc_break_parameter_struct.breakstate = TIMER_BREAK_ENABLE;
+ timerBldc_break_parameter_struct.breakpolarity = TIMER_BREAK_POLARITY_LOW;
+ timerBldc_break_parameter_struct.outputautostate = TIMER_OUTAUTO_ENABLE;
+
+ // Configure the timer with the break parameter struct
+ timer_break_config(TIMER_BLDC, &timerBldc_break_parameter_struct);
+
+ // Disable until all channels are set for PWM output
+ timer_disable(TIMER_BLDC);
+
+ // Enable all three channels for PWM output
+ timer_channel_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_CCX_ENABLE);
+ timer_channel_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_CCX_ENABLE);
+ timer_channel_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_CCX_ENABLE);
+
+ // Enable all three complemenary channels for PWM output
+ timer_channel_complementary_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, TIMER_CCXN_ENABLE);
+ timer_channel_complementary_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, TIMER_CCXN_ENABLE);
+ timer_channel_complementary_output_state_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, TIMER_CCXN_ENABLE);
+
+ // Enable TIMER_INT_UP interrupt and set priority
+ nvic_irq_enable(TIMER0_BRK_UP_TRG_COM_IRQn, 0, 0);
+ timer_interrupt_enable(TIMER_BLDC, TIMER_INT_UP);
+
+ // Enable the timer and start PWM
+ timer_enable(TIMER_BLDC);
+}
+
+//----------------------------------------------------------------------------
+// Initializes the ADC
+//----------------------------------------------------------------------------
+void ADC_init(void)
+{
+ // Enable ADC and DMA clock
+ rcu_periph_clock_enable(RCU_ADC);
+ rcu_periph_clock_enable(RCU_DMA);
+
+ // Configure ADC clock (APB2 clock is DIV1 -> 72MHz, ADC clock is DIV6 -> 12MHz)
+ rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+
+ // Interrupt channel 0 enable
+ nvic_irq_enable(DMA_Channel0_IRQn, 1, 0);
+
+ // Initialize DMA channel 0 for ADC
+ dma_deinit(DMA_CH0);
+ dma_init_struct_adc.direction = DMA_PERIPHERAL_TO_MEMORY;
+ dma_init_struct_adc.memory_addr = (uint32_t)&adc_buffer;
+ dma_init_struct_adc.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
+ dma_init_struct_adc.memory_width = DMA_MEMORY_WIDTH_16BIT;
+ dma_init_struct_adc.number = 2;
+ dma_init_struct_adc.periph_addr = (uint32_t)&ADC_RDATA;
+ dma_init_struct_adc.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
+ dma_init_struct_adc.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
+ dma_init_struct_adc.priority = DMA_PRIORITY_ULTRA_HIGH;
+ dma_init(DMA_CH0, dma_init_struct_adc);
+
+ // Configure DMA mode
+ dma_circulation_enable(DMA_CH0);
+ dma_memory_to_memory_disable(DMA_CH0);
+
+ // Enable DMA transfer complete interrupt
+ dma_interrupt_enable(DMA_CH0, DMA_CHXCTL_FTFIE);
+
+ // At least clear number of remaining data to be transferred by the DMA
+ dma_transfer_number_config(DMA_CH0, 2);
+
+ // Enable DMA channel 0
+ dma_channel_enable(DMA_CH0);
+
+ adc_channel_length_config(ADC_REGULAR_CHANNEL, 2);
+ adc_regular_channel_config(0, VBATT_CHANNEL, ADC_SAMPLETIME_13POINT5);
+ adc_regular_channel_config(1, CURRENT_DC_CHANNEL, ADC_SAMPLETIME_13POINT5);
+ adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+
+ // Set trigger of ADC
+ adc_external_trigger_config(ADC_REGULAR_CHANNEL, ENABLE);
+ adc_external_trigger_source_config(ADC_REGULAR_CHANNEL, ADC_EXTTRIG_REGULAR_SWRCST);
+
+ // Disable the temperature sensor, Vrefint and vbat channel
+ adc_tempsensor_vrefint_disable();
+ adc_vbat_disable();
+
+ // ADC analog watchdog disable
+ adc_watchdog_disable();
+
+ // Enable ADC (must be before calibration)
+ adc_enable();
+
+ // Calibrate ADC values
+ adc_calibration_enable();
+
+ // Enable DMA request
+ adc_dma_mode_enable();
+
+ // Set ADC to scan mode
+ adc_special_function_config(ADC_SCAN_MODE, ENABLE);
+}
+
+//----------------------------------------------------------------------------
+// Initializes the usart master slave
+//----------------------------------------------------------------------------
+void USART_HUGS_init(void)
+{
+ // Enable ADC and DMA clock
+ rcu_periph_clock_enable(RCU_USART1);
+ rcu_periph_clock_enable(RCU_DMA);
+
+ // Init USART for 115200 baud, 8N1
+ usart_baudrate_set(USART_HUGS, 115200);
+ usart_parity_config(USART_HUGS, USART_PM_NONE);
+ usart_word_length_set(USART_HUGS, USART_WL_8BIT);
+ usart_stop_bit_set(USART_HUGS, USART_STB_1BIT);
+ usart_oversample_config(USART_HUGS, USART_OVSMOD_16);
+
+ // Enable both transmitter and receiver
+ usart_transmit_config(USART_HUGS, USART_TRANSMIT_ENABLE);
+ usart_receive_config(USART_HUGS, USART_RECEIVE_ENABLE);
+
+ // Enable USART
+ usart_enable(USART_HUGS);
+
+ // Interrupt channel 3/4 enable
+ nvic_irq_enable(DMA_Channel3_4_IRQn, 2, 0);
+
+ // Initialize DMA channel 4 for USART_SLAVE RX
+ dma_deinit(DMA_CH4);
+ dma_init_struct_usart.direction = DMA_PERIPHERAL_TO_MEMORY;
+ dma_init_struct_usart.memory_addr = (uint32_t)usartHUGS_rx_buf;
+ dma_init_struct_usart.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
+ dma_init_struct_usart.memory_width = DMA_MEMORY_WIDTH_8BIT;
+ dma_init_struct_usart.number = USART_HUGS_RX_BUFFERSIZE;
+ dma_init_struct_usart.periph_addr = USART_HUGS_DATA_RX_ADDRESS;
+ dma_init_struct_usart.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
+ dma_init_struct_usart.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
+ dma_init_struct_usart.priority = DMA_PRIORITY_ULTRA_HIGH;
+ dma_init(DMA_CH4, dma_init_struct_usart);
+
+ // Configure DMA mode
+ dma_circulation_enable(DMA_CH4);
+ dma_memory_to_memory_disable(DMA_CH4);
+
+ // USART DMA enable for transmission and receive
+ usart_dma_receive_config(USART_HUGS, USART_DENR_ENABLE);
+
+ // Enable DMA transfer complete interrupt
+ dma_interrupt_enable(DMA_CH4, DMA_CHXCTL_FTFIE);
+
+ // At least clear number of remaining data to be transferred by the DMA
+ dma_transfer_number_config(DMA_CH4, 1);
+
+ // Enable dma receive channel
+ dma_channel_enable(DMA_CH4);
+}
+
+//----------------------------------------------------------------------------
+// Initializes the usart steer/bluetooth
+//----------------------------------------------------------------------------
+void USART_Steer_COM_init(void)
+{
+ // Enable ADC and DMA clock
+ rcu_periph_clock_enable(RCU_USART0);
+ rcu_periph_clock_enable(RCU_DMA);
+
+ // Init USART for 38400 baud, 8N1 (Works best with PIC 8MHz)
+ usart_baudrate_set(USART_STEER_COM, 38400);
+ usart_parity_config(USART_STEER_COM, USART_PM_NONE);
+ usart_word_length_set(USART_STEER_COM, USART_WL_8BIT);
+ usart_stop_bit_set(USART_STEER_COM, USART_STB_1BIT);
+ usart_oversample_config(USART_STEER_COM, USART_OVSMOD_16);
+
+ // Enable both transmitter and receiver
+ usart_transmit_config(USART_STEER_COM, USART_TRANSMIT_ENABLE);
+ usart_receive_config(USART_STEER_COM, USART_RECEIVE_ENABLE);
+
+ // Enable USART
+ usart_enable(USART_STEER_COM);
+
+ // Interrupt channel 1/2 enable
+ nvic_irq_enable(DMA_Channel1_2_IRQn, 2, 0);
+
+ // Initialize DMA channel 2 for USART_STEER_COM RX
+ dma_deinit(DMA_CH2);
+ dma_init_struct_usart.direction = DMA_PERIPHERAL_TO_MEMORY;
+ dma_init_struct_usart.memory_addr = (uint32_t)usartSteer_COM_rx_buf;
+ dma_init_struct_usart.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
+ dma_init_struct_usart.memory_width = DMA_MEMORY_WIDTH_8BIT;
+ dma_init_struct_usart.number = USART_STEER_COM_RX_BUFFERSIZE;
+ dma_init_struct_usart.periph_addr = USART_STEER_COM_DATA_RX_ADDRESS;
+ dma_init_struct_usart.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
+ dma_init_struct_usart.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
+ dma_init_struct_usart.priority = DMA_PRIORITY_ULTRA_HIGH;
+ dma_init(DMA_CH2, dma_init_struct_usart);
+
+ // Configure DMA mode
+ dma_circulation_enable(DMA_CH2);
+ dma_memory_to_memory_disable(DMA_CH2);
+
+ // USART DMA enable for transmission and receive
+ usart_dma_receive_config(USART_STEER_COM, USART_DENR_ENABLE);
+
+ // Enable DMA transfer complete interrupt
+ dma_interrupt_enable(DMA_CH2, DMA_CHXCTL_FTFIE);
+
+ // At least clear number of remaining data to be transferred by the DMA
+ dma_transfer_number_config(DMA_CH2, 1);
+
+ // Enable dma receive channel
+ dma_channel_enable(DMA_CH2);
+}
diff --git a/Hardware_Overview_small.png b/Hardware_Overview_small.png
deleted file mode 100644
index c5ef17f3..00000000
Binary files a/Hardware_Overview_small.png and /dev/null differ
diff --git a/HoverBoardGigaDevice/Inc/bldc.h b/HoverBoardGigaDevice/Inc/bldc.h
deleted file mode 100644
index 0ca9bbe2..00000000
--- a/HoverBoardGigaDevice/Inc/bldc.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#ifndef BLDC_H
-#define BLDC_H
-
-#include "gd32f1x0.h"
-#include "../Inc/config.h"
-
-//----------------------------------------------------------------------------
-// Set motor enable
-//----------------------------------------------------------------------------
-void SetEnable(FlagStatus setEnable);
-
-//----------------------------------------------------------------------------
-// Set pwm -1000 to 1000
-//----------------------------------------------------------------------------
-void SetPWM(int16_t setPwm);
-
-//----------------------------------------------------------------------------
-// Calculation-Routine for BLDC => calculates with 16kHz
-//----------------------------------------------------------------------------
-void CalculateBLDC(void);
-
-#endif
diff --git a/HoverBoardGigaDevice/Inc/commsBluetooth.h b/HoverBoardGigaDevice/Inc/commsBluetooth.h
deleted file mode 100644
index 84e5586b..00000000
--- a/HoverBoardGigaDevice/Inc/commsBluetooth.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#ifndef COMMSBLUETOOTH_H
-#define COMMSBLUETOOTH_H
-
-#include "gd32f1x0.h"
-#include "../Inc/config.h"
-
-// Only slave communicates over bluetooth
-#ifdef SLAVE
-
-//----------------------------------------------------------------------------
-// Update USART bluetooth input
-//----------------------------------------------------------------------------
-void UpdateUSARTBluetoothInput(void);
-
-#endif
-
-#endif
diff --git a/HoverBoardGigaDevice/RTE/_Target_1/RTE_Components.h b/HoverBoardGigaDevice/RTE/_Target_1/RTE_Components.h
deleted file mode 100644
index 5d00c025..00000000
--- a/HoverBoardGigaDevice/RTE/_Target_1/RTE_Components.h
+++ /dev/null
@@ -1,34 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- * *** Do not modify ! ***
- *
- * Project: 'Hoverboard'
- * Target: 'Target 1'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File:
- */
-#define CMSIS_device_header "gd32f1x0.h"
-
-#define RTE_DEVICE_STDPERIPHERALS_ADC
-#define RTE_DEVICE_STDPERIPHERALS_DBG
-#define RTE_DEVICE_STDPERIPHERALS_DMA
-#define RTE_DEVICE_STDPERIPHERALS_FWDGT
-#define RTE_DEVICE_STDPERIPHERALS_GPIO
-#define RTE_DEVICE_STDPERIPHERALS_I2C
-#define RTE_DEVICE_STDPERIPHERALS_MISC
-#define RTE_DEVICE_STDPERIPHERALS_OPA
-#define RTE_DEVICE_STDPERIPHERALS_PMU
-#define RTE_DEVICE_STDPERIPHERALS_RCU
-#define RTE_DEVICE_STDPERIPHERALS_SYSCFG
-#define RTE_DEVICE_STDPERIPHERALS_TIMER
-#define RTE_DEVICE_STDPERIPHERALS_USART
-#define RTE_DEVICE_STDPERIPHERALS_WWDGT
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/HoverBoardGigaDevice/Src/bldc.c b/HoverBoardGigaDevice/Src/bldc.c
deleted file mode 100644
index 63464d82..00000000
--- a/HoverBoardGigaDevice/Src/bldc.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/setup.h"
-#include "../Inc/defines.h"
-#include "../Inc/config.h"
-
-// Internal constants
-const int16_t pwm_res = 72000000 / 2 / PWM_FREQ; // = 2000
-
-// Global variables for voltage and current
-float batteryVoltage = 40.0;
-float currentDC = 0.0;
-float realSpeed = 0.0;
-
-// Timeoutvariable set by timeout timer
-extern FlagStatus timedOut;
-
-// Variables to be set from the main routine
-int16_t bldc_inputFilterPwm = 0;
-FlagStatus bldc_enable = RESET;
-
-// ADC buffer to be filled by DMA
-adc_buf_t adc_buffer;
-
-// Internal calculation variables
-uint8_t hall_a;
-uint8_t hall_b;
-uint8_t hall_c;
-uint8_t hall;
-uint8_t pos;
-uint8_t lastPos;
-int16_t bldc_outputFilterPwm = 0;
-int32_t filter_reg;
-FlagStatus buzzerToggle = RESET;
-uint8_t buzzerFreq = 0;
-uint8_t buzzerPattern = 0;
-uint16_t buzzerTimer = 0;
-int16_t offsetcount = 0;
-int16_t offsetdc = 2000;
-uint32_t speedCounter = 0;
-
-//----------------------------------------------------------------------------
-// Commutation table
-//----------------------------------------------------------------------------
-const uint8_t hall_to_pos[8] =
-{
- // annotation: for example SA=0 means hall sensor pulls SA down to Ground
- 0, // hall position [-] - No function (access from 1-6)
- 3, // hall position [1] (SA=1, SB=0, SC=0) -> PWM-position 3
- 5, // hall position [2] (SA=0, SB=1, SC=0) -> PWM-position 5
- 4, // hall position [3] (SA=1, SB=1, SC=0) -> PWM-position 4
- 1, // hall position [4] (SA=0, SB=0, SC=1) -> PWM-position 1
- 2, // hall position [5] (SA=1, SB=0, SC=1) -> PWM-position 2
- 6, // hall position [6] (SA=0, SB=1, SC=1) -> PWM-position 6
- 0, // hall position [-] - No function (access from 1-6)
-};
-
-//----------------------------------------------------------------------------
-// Block PWM calculation based on position
-//----------------------------------------------------------------------------
-__INLINE void blockPWM(int pwm, int pwmPos, int *y, int *b, int *g)
-{
- switch(pwmPos)
- {
- case 1:
- *y = 0;
- *b = pwm;
- *g = -pwm;
- break;
- case 2:
- *y = -pwm;
- *b = pwm;
- *g = 0;
- break;
- case 3:
- *y = -pwm;
- *b = 0;
- *g = pwm;
- break;
- case 4:
- *y = 0;
- *b = -pwm;
- *g = pwm;
- break;
- case 5:
- *y = pwm;
- *b = -pwm;
- *g = 0;
- break;
- case 6:
- *y = pwm;
- *b = 0;
- *g = -pwm;
- break;
- default:
- *y = 0;
- *b = 0;
- *g = 0;
- }
-}
-
-//----------------------------------------------------------------------------
-// Set motor enable
-//----------------------------------------------------------------------------
-void SetEnable(FlagStatus setEnable)
-{
- bldc_enable = setEnable;
-}
-
-//----------------------------------------------------------------------------
-// Set pwm -1000 to 1000
-//----------------------------------------------------------------------------
-void SetPWM(int16_t setPwm)
-{
- bldc_inputFilterPwm = CLAMP(setPwm, -1000, 1000);
-}
-
-//----------------------------------------------------------------------------
-// Calculation-Routine for BLDC => calculates with 16kHz
-//----------------------------------------------------------------------------
-void CalculateBLDC(void)
-{
- int y = 0; // yellow = phase A
- int b = 0; // blue = phase B
- int g = 0; // green = phase C
-
- // Calibrate ADC offsets for the first 1000 cycles
- if (offsetcount < 1000)
- {
- offsetcount++;
- offsetdc = (adc_buffer.current_dc + offsetdc) / 2;
- return;
- }
-
- // Calculate battery voltage every 100 cycles
- if (buzzerTimer % 100 == 0)
- {
- batteryVoltage = batteryVoltage * 0.999 + ((float)adc_buffer.v_batt * ADC_BATTERY_VOLT) * 0.001;
- }
-
-#ifdef MASTER
- // Create square wave for buzzer
- buzzerTimer++;
- if (buzzerFreq != 0 && (buzzerTimer / 5000) % (buzzerPattern + 1) == 0)
- {
- if (buzzerTimer % buzzerFreq == 0)
- {
- buzzerToggle = buzzerToggle == RESET ? SET : RESET; // toggle variable
- gpio_bit_write(BUZZER_PORT, BUZZER_PIN, buzzerToggle);
- }
- }
- else
- {
- gpio_bit_write(BUZZER_PORT, BUZZER_PIN, RESET);
- }
-#endif
-
- // Calculate current DC
- currentDC = ABS((adc_buffer.current_dc - offsetdc) * MOTOR_AMP_CONV_DC_AMP);
-
- // Disable PWM when current limit is reached (current chopping), enable is not set or timeout is reached
- if (currentDC > DC_CUR_LIMIT || bldc_enable == RESET || timedOut == SET)
- {
- timer_automatic_output_disable(TIMER_BLDC);
- }
- else
- {
- timer_automatic_output_enable(TIMER_BLDC);
- }
-
- // Read hall sensors
- hall_a = gpio_input_bit_get(HALL_A_PORT, HALL_A_PIN);
- hall_b = gpio_input_bit_get(HALL_B_PORT, HALL_B_PIN);
- hall_c = gpio_input_bit_get(HALL_C_PORT, HALL_C_PIN);
-
- // Determine current position based on hall sensors
- hall = hall_a * 1 + hall_b * 2 + hall_c * 4;
- pos = hall_to_pos[hall];
-
- // Calculate low-pass filter for pwm value
- filter_reg = filter_reg - (filter_reg >> FILTER_SHIFT) + bldc_inputFilterPwm;
- bldc_outputFilterPwm = filter_reg >> FILTER_SHIFT;
-
- // Update PWM channels based on position y(ellow), b(lue), g(reen)
- blockPWM(bldc_outputFilterPwm, pos, &y, &b, &g);
-
- // Set PWM output (pwm_res/2 is the mean value, setvalue has to be between 10 and pwm_res-10)
- timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_G, CLAMP(g + pwm_res / 2, 10, pwm_res-10));
- timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_B, CLAMP(b + pwm_res / 2, 10, pwm_res-10));
- timer_channel_output_pulse_value_config(TIMER_BLDC, TIMER_BLDC_CHANNEL_Y, CLAMP(y + pwm_res / 2, 10, pwm_res-10));
-
- // Increments with 62.5us
- if(speedCounter < 4000) // No speed after 250ms
- {
- speedCounter++;
- }
-
- // Every time position reaches value 1, one round is performed (rising edge)
- if (lastPos != 1 && pos == 1)
- {
- realSpeed = 1991.81f / (float)speedCounter; //[km/h]
- speedCounter = 0;
- }
- else
- {
- if (speedCounter >= 4000)
- {
- realSpeed = 0;
- }
- }
-
- // Safe last position
- lastPos = pos;
-}
diff --git a/HoverBoardGigaDevice/Src/commsBluetooth.c b/HoverBoardGigaDevice/Src/commsBluetooth.c
deleted file mode 100644
index 1cf8b0b6..00000000
--- a/HoverBoardGigaDevice/Src/commsBluetooth.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/defines.h"
-#include "../Inc/setup.h"
-#include "../Inc/comms.h"
-#include "../Inc/commsMasterSlave.h"
-#include "../Inc/commsBluetooth.h"
-#include "../Inc/led.h"
-#include "stdio.h"
-#include "string.h"
-
-// Only slave communicates over bluetooth
-#ifdef SLAVE
-// Variables which will be send over bluetooth
-extern float currentDC;
-extern float realSpeed;
-
-extern uint32_t hornCounter_ms;
-
-#define USART_BLUETOOTH_TX_BYTES 11 // Transmit byte count including start '/' and stop character '\n'
-#define USART_BLUETOOTH_RX_BYTES 11 // Receive byte count including start '/' and stop character '\n'
-
-extern uint8_t usartSteer_COM_rx_buf[USART_STEER_COM_RX_BUFFERSIZE];
-static uint8_t sBluetoothRecord = 0;
-static uint8_t sUSARTBluetoothRecordBuffer[USART_BLUETOOTH_RX_BYTES];
-static uint8_t sUSARTBluetoothRecordBufferCounter = 0;
-
-void CheckUSARTBluetoothInput(uint8_t USARTBuffer[]);
-void SendBluetoothDevice(uint8_t identifier, int16_t value);
-
-//----------------------------------------------------------------------------
-// Update USART bluetooth input
-//----------------------------------------------------------------------------
-void UpdateUSARTBluetoothInput(void)
-{
- uint8_t character = usartSteer_COM_rx_buf[0];
-
- // Start character is captured, start record
- if (character == '/')
- {
- sUSARTBluetoothRecordBufferCounter = 0;
- sBluetoothRecord = 1;
- }
-
- if (sBluetoothRecord)
- {
- sUSARTBluetoothRecordBuffer[sUSARTBluetoothRecordBufferCounter] = character;
- sUSARTBluetoothRecordBufferCounter++;
-
- if (sUSARTBluetoothRecordBufferCounter >= USART_BLUETOOTH_RX_BYTES)
- {
- sUSARTBluetoothRecordBufferCounter = 0;
- sBluetoothRecord = 0;
-
- // Check input
- CheckUSARTBluetoothInput (sUSARTBluetoothRecordBuffer);
- }
- }
-}
-
-//----------------------------------------------------------------------------
-// Check USART bluetooth input
-//----------------------------------------------------------------------------
-void CheckUSARTBluetoothInput(uint8_t USARTBuffer[])
-{
- // Auxiliary variables
- uint8_t identifier = 0;
- uint8_t readWrite = 0;
- int16_t sign = 0;
- int16_t digit1 = 0;
- int16_t digit2 = 0;
- int16_t digit3 = 0;
- int16_t digit4 = 0;
- int16_t digit5 = 0;
- int16_t value = 0;
-
- // Check start and stop character
- if ( USARTBuffer[0] != '/' ||
- USARTBuffer[USART_BLUETOOTH_RX_BYTES - 1] != '\n')
- {
- return;
- }
-
- // Calculate identifier (number 0-99)
- digit1 = (USARTBuffer[1] - '0') * 10;
- digit2 = (USARTBuffer[2] - '0');
- identifier = digit1 + digit2;
-
- // Calculate read or write access (0 - read, 1 - write)
- readWrite = USARTBuffer[3] - '0';
-
- // If read mode, answer with correct value
- if (readWrite == 0)
- {
- switch(identifier)
- {
- case 0:
- // Answer with battery voltage from master
- value = GetBatteryMaster();
- break;
- case 1:
- // Answer with current from master
- value = GetCurrentDCMaster();
- break;
- case 2:
- // Answer with current from slave
- value = currentDC * 100;
- break;
- case 3:
- // Answer with real speed of master
- value = GetRealSpeedMaster();
- break;
- case 4:
- // Answer with real speed of slave
- value = realSpeed * 100;
- break;
- case 5:
- // Answer with beeps backwards from master
- value = GetBeepsBackwardsMaster() == RESET ? 0 : 1;
- break;
- case 6:
- // Answer with lower LED state of master (music box)
- value = GetLowerLEDMaster() == RESET ? 0 : 1;
- break;
- case 7:
- // Answer with upper LED state of master (horn)
- value = GetUpperLEDMaster() == RESET ? 0 : 1;
- break;
- case 8:
- // Answer with hue value
- value = GetHSBHue();
- break;
- case 9:
- // Answer with saturation value
- value = GetHSBSaturation();
- break;
- case 10:
- // Answer with brightness value
- value = GetHSBBrightness();
- break;
- case 11:
- // Answer with LEDMode
- value = GetRGBProgram();
- break;
- case 12:
- // Answer with fading speed
- value = GetSpeedFading();
- break;
- case 13:
- // Answer with blink speed
- value = GetSpeedBlink();
- break;
- case 14:
- // Answer with strobe speed
- value = GetSpeedStrobe();
- break;
- }
-
- // Send Answer
- SendBluetoothDevice(identifier, value);
- }
- // If write mode, get result value
- else if ( readWrite == 1)
- {
- // Calculate result value (-10000 to 10000)
- sign = USARTBuffer[4] == '-' ? -1 : 1;
- digit1 = (USARTBuffer[5] - '0') * 10000;
- digit2 = (USARTBuffer[6] - '0') * 1000;
- digit3 = (USARTBuffer[7] - '0') * 100;
- digit4 = (USARTBuffer[8] - '0') * 10;
- digit5 = (USARTBuffer[9] - '0');
- value = sign * (digit1 + digit2 + digit3 + digit4 + digit5);
-
- switch(identifier)
- {
- case 5:
- SetBeepsBackwardsMaster(value == 0 ? RESET : SET);
- break;
- case 6:
- // Set lower LED of master (music box)
- SetLowerLEDMaster(value == 0 ? RESET : SET);
- break;
- case 7:
- // Set upper LED of master (horn)
- hornCounter_ms = 0;
- SetUpperLEDMaster(value == 0 ? RESET : SET);
- break;
- case 8:
- // Set LED hue
- SetHSBHue(value);
- break;
- case 9:
- // Set LED saturation
- SetHSBSaturation(value);
- break;
- case 10:
- // Set LED brightness
- SetHSBBrightness(value);
- break;
- case 11:
- // Set LED mode
- SetRGBProgram((LED_PROGRAM)value);
- break;
- case 12:
- // Set fading speed
- SetSpeedFading(value);
- break;
- case 13:
- // Set blink speed
- SetSpeedBlink(value);
- break;
- case 14:
- // Set strobe speed
- SetSpeedStrobe(value);
- break;
- default:
- // Do nothing for the rest of the identifiers
- break;
- }
- }
-}
-
-//----------------------------------------------------------------------------
-// Send frame to bluetooth device
-//----------------------------------------------------------------------------
-void SendBluetoothDevice(uint8_t identifier, int16_t value)
-{
- int index = 0;
- char charVal[5];
- uint8_t buffer[USART_BLUETOOTH_TX_BYTES];
-
- // Send bluetooth frame
- buffer[index++] = '/';
- sprintf(charVal, "%02d", identifier);
- buffer[index++] = charVal[0];
- buffer[index++] = charVal[1];
- buffer[index++] = '0';
- sprintf(charVal, "%05d", value);
- buffer[index++] = value < 0 ? '-' : '+';
- buffer[index++] = charVal[0];
- buffer[index++] = charVal[1];
- buffer[index++] = charVal[2];
- buffer[index++] = charVal[3];
- buffer[index++] = charVal[4];
- buffer[index++] = '\n';
-
- SendBuffer(USART_STEER_COM, buffer, index);
-}
-
-#endif
diff --git a/HoverBoardGigaDevice/Src/commsMasterSlave.c b/HoverBoardGigaDevice/Src/commsMasterSlave.c
deleted file mode 100644
index 92697475..00000000
--- a/HoverBoardGigaDevice/Src/commsMasterSlave.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/it.h"
-#include "../Inc/comms.h"
-#include "../Inc/commsMasterSlave.h"
-#include "../Inc/setup.h"
-#include "../Inc/config.h"
-#include "../Inc/defines.h"
-#include "../Inc/bldc.h"
-#include "stdio.h"
-#include "string.h"
-
-#ifdef MASTER
-#define USART_MASTERSLAVE_TX_BYTES 10 // Transmit byte count including start '/' and stop character '\n'
-#define USART_MASTERSLAVE_RX_BYTES 5 // Receive byte count including start '/' and stop character '\n'
-
-// Variables which will be written by slave frame
-extern FlagStatus beepsBackwards;
-#endif
-#ifdef SLAVE
-#define USART_MASTERSLAVE_TX_BYTES 5 // Transmit byte count including start '/' and stop character '\n'
-#define USART_MASTERSLAVE_RX_BYTES 10 // Receive byte count including start '/' and stop character '\n'
-
-// Variables which will be send to master
-FlagStatus upperLEDMaster = RESET;
-FlagStatus lowerLEDMaster = RESET;
-FlagStatus mosfetOutMaster = RESET;
-FlagStatus beepsBackwardsMaster = RESET;
-
-// Variables which will be written by master frame
-int16_t currentDCMaster = 0;
-int16_t batteryMaster = 0;
-int16_t realSpeedMaster = 0;
-
-void CheckGeneralValue(uint8_t identifier, int16_t value);
-#endif
-
-extern uint8_t usartMasterSlave_rx_buf[USART_MASTERSLAVE_RX_BUFFERSIZE];
-static uint8_t sMasterSlaveRecord = 0;
-static uint8_t sUSARTMasterSlaveRecordBuffer[USART_MASTERSLAVE_RX_BYTES];
-static uint8_t sUSARTMasterSlaveRecordBufferCounter = 0;
-
-void CheckUSARTMasterSlaveInput(uint8_t u8USARTBuffer[]);
-void SendBuffer(uint32_t usart_periph, uint8_t buffer[], uint8_t length);
-uint16_t CalcCRC(uint8_t *ptr, int count);
-
-//----------------------------------------------------------------------------
-// Update USART master slave input
-//----------------------------------------------------------------------------
-void UpdateUSARTMasterSlaveInput(void)
-{
- uint8_t character = usartMasterSlave_rx_buf[0];
-
- // Start character is captured, start record
- if (character == '/')
- {
- sUSARTMasterSlaveRecordBufferCounter = 0;
- sMasterSlaveRecord = 1;
- }
-
- if (sMasterSlaveRecord)
- {
- sUSARTMasterSlaveRecordBuffer[sUSARTMasterSlaveRecordBufferCounter] = character;
- sUSARTMasterSlaveRecordBufferCounter++;
-
- if (sUSARTMasterSlaveRecordBufferCounter >= USART_MASTERSLAVE_RX_BYTES)
- {
- sUSARTMasterSlaveRecordBufferCounter = 0;
- sMasterSlaveRecord = 0;
-
- // Check input
- CheckUSARTMasterSlaveInput (sUSARTMasterSlaveRecordBuffer);
- }
- }
-}
-
-//----------------------------------------------------------------------------
-// Check USART master slave input
-//----------------------------------------------------------------------------
-void CheckUSARTMasterSlaveInput(uint8_t USARTBuffer[])
-{
-#ifdef MASTER
- // Result variables
- FlagStatus upperLED = RESET;
- FlagStatus lowerLED = RESET;
- FlagStatus mosfetOut = RESET;
-
- // Auxiliary variables
- uint8_t byte;
-#endif
-#ifdef SLAVE
- // Result variables
- int16_t pwmSlave = 0;
- FlagStatus enable = RESET;
- FlagStatus shutoff = RESET;
- FlagStatus chargeStateLowActive = SET;
-
- // Auxiliary variables
- uint8_t identifier = 0;
- int16_t value = 0;
- uint8_t byte;
-#endif
- // Auxiliary variables
- uint16_t crc;
-
- // Check start and stop character
- if ( USARTBuffer[0] != '/' ||
- USARTBuffer[USART_MASTERSLAVE_RX_BYTES - 1] != '\n')
- {
- return;
- }
-
- // Calculate CRC (first bytes except crc and stop byte)
- crc = CalcCRC(USARTBuffer, USART_MASTERSLAVE_RX_BYTES - 3);
-
- // Check CRC
- if ( USARTBuffer[USART_MASTERSLAVE_RX_BYTES - 3] != ((crc >> 8) & 0xFF) ||
- USARTBuffer[USART_MASTERSLAVE_RX_BYTES - 2] != (crc & 0xFF))
- {
- return;
- }
-
-#ifdef MASTER
- // Calculate setvalues for LED and mosfets
- byte = USARTBuffer[1];
-
- //none = (byte & BIT(7)) ? SET : RESET;
- //none = (byte & BIT(6)) ? SET : RESET;
- //none = (byte & BIT(5)) ? SET : RESET;
- //none = (byte & BIT(4)) ? SET : RESET;
- beepsBackwards = (byte & BIT(3)) ? SET : RESET;
- mosfetOut = (byte & BIT(2)) ? SET : RESET;
- lowerLED = (byte & BIT(1)) ? SET : RESET;
- upperLED = (byte & BIT(0)) ? SET : RESET;
-
- // Set functions according to the variables
- gpio_bit_write(MOSFET_OUT_PORT, MOSFET_OUT_PIN, mosfetOut);
- gpio_bit_write(UPPER_LED_PORT, UPPER_LED_PIN, upperLED);
- gpio_bit_write(LOWER_LED_PORT, LOWER_LED_PIN, lowerLED);
-#endif
-#ifdef SLAVE
- // Calculate result pwm value -1000 to 1000
- pwmSlave = (int16_t)((USARTBuffer[1] << 8) | USARTBuffer[2]);
-
- // Get identifier
- identifier = USARTBuffer[3];
-
- // Calculate result general value
- value = (int16_t)((USARTBuffer[4] << 8) | USARTBuffer[5]);
-
- // Calculate setvalues for enable and shutoff
- byte = USARTBuffer[6];
-
- shutoff = (byte & BIT(7)) ? SET : RESET;
- //none = (byte & BIT(6)) ? SET : RESET;
- //none = (byte & BIT(5)) ? SET : RESET;
- //none = (byte & BIT(4)) ? SET : RESET;
- //none = (byte & BIT(3)) ? SET : RESET;
- //none = (byte & BIT(2)) ? SET : RESET;
- chargeStateLowActive = (byte & BIT(1)) ? SET : RESET;
- enable = (byte & BIT(0)) ? SET : RESET;
-
- if (shutoff == SET)
- {
- // Disable usart
- usart_deinit(USART_MASTERSLAVE);
-
- // Set pwm and enable to off
- SetEnable(RESET);
- SetPWM(0);
-
- gpio_bit_write(SELF_HOLD_PORT, SELF_HOLD_PIN, RESET);
- while(1)
- {
- // Reload watchdog until device is off
- fwdgt_counter_reload();
- }
- }
-
- // Set functions according to the variables
- gpio_bit_write(LED_GREEN_PORT, LED_GREEN, chargeStateLowActive == SET ? SET : RESET);
- gpio_bit_write(LED_RED_PORT, LED_RED, chargeStateLowActive == RESET ? SET : RESET);
- SetEnable(enable);
- SetPWM(pwmSlave);
- CheckGeneralValue(identifier, value);
-
- // Send answer
- SendMaster(upperLEDMaster, lowerLEDMaster, mosfetOutMaster, beepsBackwardsMaster);
-
- // Reset the pwm timout to avoid stopping motors
- ResetTimeout();
-#endif
-}
-
-#ifdef MASTER
-//----------------------------------------------------------------------------
-// Send slave frame via USART
-//----------------------------------------------------------------------------
-void SendSlave(int16_t pwmSlave, FlagStatus enable, FlagStatus shutoff, FlagStatus chargeState, uint8_t identifier, int16_t value)
-{
- uint8_t index = 0;
- uint16_t crc = 0;
- uint8_t buffer[USART_MASTERSLAVE_TX_BYTES];
-
- // Format pwmValue and general value
- int16_t sendPwm = CLAMP(pwmSlave, -1000, 1000);
- uint16_t sendPwm_Uint = (uint16_t)(sendPwm);
- uint16_t value_Uint = (uint16_t)(value);
-
- uint8_t sendByte = 0;
- sendByte |= (shutoff << 7);
- sendByte |= (0 << 6);
- sendByte |= (0 << 5);
- sendByte |= (0 << 4);
- sendByte |= (0 << 3);
- sendByte |= (0 << 2);
- sendByte |= (chargeState << 1);
- sendByte |= (enable << 0);
-
- // Send answer
- buffer[index++] = '/';
- buffer[index++] = (sendPwm_Uint >> 8) & 0xFF;
- buffer[index++] = sendPwm_Uint & 0xFF;
- buffer[index++] = identifier;
- buffer[index++] = (value_Uint >> 8) & 0xFF;
- buffer[index++] = value_Uint & 0xFF;
- buffer[index++] = sendByte;
-
- // Calculate CRC
- crc = CalcCRC(buffer, index);
- buffer[index++] = (crc >> 8) & 0xFF;
- buffer[index++] = crc & 0xFF;
-
- // Stop byte
- buffer[index++] = '\n';
-
- SendBuffer(USART_MASTERSLAVE, buffer, index);
-}
-#endif
-#ifdef SLAVE
-//----------------------------------------------------------------------------
-// Send master frame via USART
-//----------------------------------------------------------------------------
-void SendMaster(FlagStatus upperLEDMaster, FlagStatus lowerLEDMaster, FlagStatus mosfetOutMaster, FlagStatus beepsBackwards)
-{
- uint8_t index = 0;
- uint16_t crc = 0;
- uint8_t buffer[USART_MASTERSLAVE_TX_BYTES];
-
- uint8_t sendByte = 0;
- sendByte |= (0 << 7);
- sendByte |= (0 << 6);
- sendByte |= (0 << 5);
- sendByte |= (0 << 4);
- sendByte |= (beepsBackwards << 3);
- sendByte |= (mosfetOutMaster << 2);
- sendByte |= (lowerLEDMaster << 1);
- sendByte |= (upperLEDMaster << 0);
-
- // Send answer
- buffer[index++] = '/';
- buffer[index++] = sendByte;
-
- // Calculate CRC
- crc = CalcCRC(buffer, index);
- buffer[index++] = (crc >> 8) & 0xFF;
- buffer[index++] = crc & 0xFF;
-
- // Stop byte
- buffer[index++] = '\n';
-
- SendBuffer(USART_MASTERSLAVE, buffer, index);
-}
-
-//----------------------------------------------------------------------------
-// Checks input value from master to set value depending on identifier
-//----------------------------------------------------------------------------
-void CheckGeneralValue(uint8_t identifier, int16_t value)
-{
- switch(identifier)
- {
- case 0:
- currentDCMaster = value;
- break;
- case 1:
- batteryMaster = value;
- break;
- case 2:
- realSpeedMaster = value;
- break;
- case 3:
- break;
- default:
- break;
- }
-}
-
-//----------------------------------------------------------------------------
-// Returns current value sent by master
-//----------------------------------------------------------------------------
-int16_t GetCurrentDCMaster(void)
-{
- return currentDCMaster;
-}
-
-//----------------------------------------------------------------------------
-// Returns battery value sent by master
-//----------------------------------------------------------------------------
-int16_t GetBatteryMaster(void)
-{
- return batteryMaster;
-}
-
-//----------------------------------------------------------------------------
-// Returns realspeed value sent by master
-//----------------------------------------------------------------------------
-int16_t GetRealSpeedMaster(void)
-{
- return realSpeedMaster;
-}
-
-//----------------------------------------------------------------------------
-// Sets upper LED value which will be send to master
-//----------------------------------------------------------------------------
-void SetUpperLEDMaster(FlagStatus value)
-{
- upperLEDMaster = value;
-}
-
-//----------------------------------------------------------------------------
-// Returns upper LED value sent by master
-//----------------------------------------------------------------------------
-FlagStatus GetUpperLEDMaster(void)
-{
- return upperLEDMaster;
-}
-
-//----------------------------------------------------------------------------
-// Sets lower LED value which will be send to master
-//----------------------------------------------------------------------------
-void SetLowerLEDMaster(FlagStatus value)
-{
- lowerLEDMaster = value;
-}
-
-//----------------------------------------------------------------------------
-// Returns lower LED value sent by master
-//----------------------------------------------------------------------------
-FlagStatus GetLowerLEDMaster(void)
-{
- return lowerLEDMaster;
-}
-
-//----------------------------------------------------------------------------
-// Sets mosfetOut value which will be send to master
-//----------------------------------------------------------------------------
-void SetMosfetOutMaster(FlagStatus value)
-{
- mosfetOutMaster = value;
-}
-
-//----------------------------------------------------------------------------
-// Returns MosfetOut value sent by master
-//----------------------------------------------------------------------------
-FlagStatus GetMosfetOutMaster(void)
-{
- return mosfetOutMaster;
-}
-
-//----------------------------------------------------------------------------
-// Sets beepsBackwards value which will be send to master
-//----------------------------------------------------------------------------
-void SetBeepsBackwardsMaster(FlagStatus value)
-{
- beepsBackwardsMaster = value;
-}
-
-//----------------------------------------------------------------------------
-// Returns beepsBackwardsMaster value sent by master
-//----------------------------------------------------------------------------
-FlagStatus GetBeepsBackwardsMaster(void)
-{
- return beepsBackwardsMaster;
-}
-#endif
diff --git a/HoverBoardGigaDevice/Src/commsSteering.c b/HoverBoardGigaDevice/Src/commsSteering.c
deleted file mode 100644
index 45ae8d8e..00000000
--- a/HoverBoardGigaDevice/Src/commsSteering.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "gd32f1x0.h"
-#include "../Inc/it.h"
-#include "../Inc/comms.h"
-#include "../Inc/commsSteering.h"
-#include "../Inc/setup.h"
-#include "../Inc/config.h"
-#include "../Inc/defines.h"
-#include "../Inc/bldc.h"
-#include "stdio.h"
-#include "string.h"
-
-// Only master communicates with steerin device
-#ifdef MASTER
-#define USART_STEER_TX_BYTES 2 // Transmit byte count including start '/' and stop character '\n'
-#define USART_STEER_RX_BYTES 8 // Receive byte count including start '/' and stop character '\n'
-
-extern uint8_t usartSteer_COM_rx_buf[USART_STEER_COM_RX_BUFFERSIZE];
-static uint8_t sSteerRecord = 0;
-static uint8_t sUSARTSteerRecordBuffer[USART_STEER_RX_BYTES];
-static uint8_t sUSARTSteerRecordBufferCounter = 0;
-
-void CheckUSARTSteerInput(uint8_t u8USARTBuffer[]);
-
-extern int32_t steer;
-extern int32_t speed;
-
-//----------------------------------------------------------------------------
-// Send frame to steer device
-//----------------------------------------------------------------------------
-void SendSteerDevice(void)
-{
- int index = 0;
- uint8_t buffer[USART_STEER_TX_BYTES];
-
- // Ask for steer input
- buffer[index++] = '/';
- buffer[index++] = '\n';
-
- SendBuffer(USART_STEER_COM, buffer, index);
-}
-
-//----------------------------------------------------------------------------
-// Update USART steer input
-//----------------------------------------------------------------------------
-void UpdateUSARTSteerInput(void)
-{
- uint8_t character = usartSteer_COM_rx_buf[0];
-
- // Start character is captured, start record
- if (character == '/')
- {
- sUSARTSteerRecordBufferCounter = 0;
- sSteerRecord = 1;
- }
-
- if (sSteerRecord)
- {
- sUSARTSteerRecordBuffer[sUSARTSteerRecordBufferCounter] = character;
- sUSARTSteerRecordBufferCounter++;
-
- if (sUSARTSteerRecordBufferCounter >= USART_STEER_RX_BYTES)
- {
- sUSARTSteerRecordBufferCounter = 0;
- sSteerRecord = 0;
-
- // Check input
- CheckUSARTSteerInput (sUSARTSteerRecordBuffer);
- }
- }
-}
-
-//----------------------------------------------------------------------------
-// Check USART steer input
-//----------------------------------------------------------------------------
-void CheckUSARTSteerInput(uint8_t USARTBuffer[])
-{
- // Auxiliary variables
- uint16_t crc;
-
- // Check start and stop character
- if ( USARTBuffer[0] != '/' ||
- USARTBuffer[USART_STEER_RX_BYTES - 1] != '\n')
- {
- return;
- }
-
- // Calculate CRC (first bytes except crc and stop byte)
- crc = CalcCRC(USARTBuffer, USART_STEER_RX_BYTES - 3);
-
- // Check CRC
- if ( USARTBuffer[USART_STEER_RX_BYTES - 3] != ((crc >> 8) & 0xFF) ||
- USARTBuffer[USART_STEER_RX_BYTES - 2] != (crc & 0xFF))
- {
- return;
- }
-
- // Calculate result speed value -1000 to 1000
- speed = (int16_t)((USARTBuffer[1] << 8) | USARTBuffer[2]);
-
- // Calculate result steering value -1000 to 1000
- steer = (int16_t)((USARTBuffer[3] << 8) | USARTBuffer[4]);
-
- // Reset the pwm timout to avoid stopping motors
- ResetTimeout();
-}
-#endif
diff --git a/HoverBoardGigaDevice/Src/main.c b/HoverBoardGigaDevice/Src/main.c
deleted file mode 100644
index a8389700..00000000
--- a/HoverBoardGigaDevice/Src/main.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#define ARM_MATH_CM3
-
-#include "gd32f1x0.h"
-
-#include "../Inc/setup.h"
-#include "../Inc/defines.h"
-#include "../Inc/config.h"
-#include "../Inc/it.h"
-#include "../Inc/bldc.h"
-#include "../Inc/commsMasterSlave.h"
-#include "../Inc/commsSteering.h"
-#include "../Inc/commsBluetooth.h"
-#include "stdio.h"
-#include "stdlib.h"
-#include "string.h"
-#include
-#include "arm_math.h"
-
-#ifdef MASTER
-int32_t steer = 0; // global variable for steering. -1000 to 1000
-int32_t speed = 0; // global variable for speed. -1000 to 1000
-FlagStatus activateWeakening = RESET; // global variable for weakening
-FlagStatus beepsBackwards = RESET; // global variable for beeps backwards
-
-extern uint8_t buzzerFreq; // global variable for the buzzer pitch. can be 1, 2, 3, 4, 5, 6, 7...
-extern uint8_t buzzerPattern; // global variable for the buzzer pattern. can be 1, 2, 3, 4, 5, 6, 7...
-
-extern float batteryVoltage; // global variable for battery voltage
-extern float currentDC; // global variable for current dc
-extern float realSpeed; // global variable for real Speed
-uint8_t slaveError = 0; // global variable for slave error
-
-extern FlagStatus timedOut; // Timeoutvariable set by timeout timer
-
-uint32_t inactivity_timeout_counter = 0; // Inactivity counter
-uint32_t steerCounter = 0; // Steer counter for setting update rate
-
-void ShowBatteryState(uint32_t pin);
-void BeepsBackwards(FlagStatus beepsBackwards);
-void ShutOff(void);
-#endif
-
-const float lookUpTableAngle[181] =
-{
- -1,
- -0.937202577,
- -0.878193767,
- -0.822607884,
- -0.770124422,
- -0.720461266,
- -0.673369096,
- -0.628626737,
- -0.58603728,
- -0.545424828,
- -0.506631749,
- -0.46951635,
- -0.433950895,
- -0.399819915,
- -0.367018754,
- -0.335452314,
- -0.30503398,
- -0.275684674,
- -0.24733204,
- -0.219909731,
- -0.193356783,
- -0.167617063,
- -0.142638788,
- -0.118374098,
- -0.094778672,
- -0.071811398,
- -0.049434068,
- -0.027611115,
- -0.006309372,
- 0.014502141,
- 0.03485241,
- 0.054768601,
- 0.074276213,
- 0.093399224,
- 0.112160212,
- 0.130580478,
- 0.148680146,
- 0.166478264,
- 0.183992885,
- 0.201241154,
- 0.218239378,
- 0.235003093,
- 0.251547129,
- 0.267885663,
- 0.284032276,
- 0.3,
- 0.315801365,
- 0.331448439,
- 0.34695287,
- 0.362325923,
- 0.377578512,
- 0.392721236,
- 0.407764409,
- 0.422718089,
- 0.437592106,
- 0.45239609,
- 0.467139493,
- 0.48183162,
- 0.496481645,
- 0.511098642,
- 0.5256916,
- 0.540269454,
- 0.554841097,
- 0.569415411,
- 0.584001283,
- 0.598607627,
- 0.613243408,
- 0.627917665,
- 0.642639528,
- 0.657418247,
- 0.672263213,
- 0.687183982,
- 0.702190301,
- 0.717292134,
- 0.732499689,
- 0.747823448,
- 0.763274197,
- 0.778863056,
- 0.794601516,
- 0.810501473,
- 0.826575268,
- 0.842835728,
- 0.859296209,
- 0.875970644,
- 0.892873598,
- 0.910020317,
- 0.927426794,
- 0.94510983,
- 0.963087109,
- 0.981377271,
- 1,
- 1.018976116,
- 1.038327677,
- 1.058078086,
- 1.07825222,
- 1.098876565,
- 1.119979359,
- 1.141590767,
- 1.163743061,
- 1.186470823,
- 1.209811179,
- 1.23380405,
- 1.258492439,
- 1.283922754,
- 1.310145166,
- 1.33721402,
- 1.365188293,
- 1.394132116,
- 1.42411537,
- 1.455214362,
- 1.487512601,
- 1.521101681,
- 1.556082309,
- 1.592565485,
- 1.630673867,
- 1.670543366,
- 1.712325006,
- 1.7561871,
- 1.802317825,
- 1.85092826,
- 1.902255998,
- 1.956569473,
- 2.014173151,
- 2.075413814,
- 2.140688197,
- 2.210452351,
- 2.28523318,
- 2.365642792,
- 2.452396478,
- 2.546335439,
- 2.648455802,
- 2.75994605,
- 2.882235846,
- 3.01706052,
- 3.166547428,
- 3.333333333,
- 3.520726642,
- 3.732935875,
- 3.97539819,
- 4.255263139,
- 4.582124498,
- 4.96916252,
- 5.434992778,
- 6.006790189,
- 6.72584757,
- 7.658112588,
- 8.915817681,
- 10.70672711,
- 13.46326037,
- 18.25863694,
- 28.69242032,
- 68.95533643,
- -158.4943784,
- -36.21729907,
- -20.22896451,
- -13.92536607,
- -10.55089693,
- -8.447794056,
- -7.010715755,
- -5.965979741,
- -5.171786508,
- -4.547320366,
- -4.043147824,
- -3.62733258,
- -3.278323283,
- -2.981049637,
- -2.72465641,
- -2.501126036,
- -2.304408198,
- -2.129851283,
- -1.973820239,
- -1.833433222,
- -1.706376086,
- -1.590769119,
- -1.485069639,
- -1.387999671,
- -1.29849148,
- -1.21564602,
- -1.138700863,
- -1.067005175,
- -1
-};
-
-
-//----------------------------------------------------------------------------
-// MAIN function
-//----------------------------------------------------------------------------
-int main (void)
-{
-#ifdef MASTER
- FlagStatus enable = RESET;
- FlagStatus enableSlave = RESET;
- FlagStatus chargeStateLowActive = SET;
- int16_t sendSlaveValue = 0;
- uint8_t sendSlaveIdentifier = 0;
- int8_t index = 8;
- int16_t pwmSlave = 0;
- int16_t pwmMaster = 0;
- int16_t scaledSpeed = 0;
- int16_t scaledSteer = 0;
- float expo = 0;
- float steerAngle = 0;
- float xScale = 0;
-#endif
-
- //SystemClock_Config();
- SystemCoreClockUpdate();
- SysTick_Config(SystemCoreClock / 100);
-
- // Init watchdog
- if (Watchdog_init() == ERROR)
- {
- // If an error accours with watchdog initialization do not start device
- while(1);
- }
-
- // Init Interrupts
- Interrupt_init();
-
- // Init timeout timer
- TimeoutTimer_init();
-
- // Init GPIOs
- GPIO_init();
-
- // Activate self hold direct after GPIO-init
- gpio_bit_write(SELF_HOLD_PORT, SELF_HOLD_PIN, SET);
-
- // Init usart master slave
- USART_MasterSlave_init();
-
- // Init ADC
- ADC_init();
-
- // Init PWM
- PWM_init();
-
- // Device has 1,6 seconds to do all the initialization
- // afterwards watchdog will be fired
- fwdgt_counter_reload();
-
- // Init usart steer/bluetooth
- USART_Steer_COM_init();
-
-#ifdef MASTER
- // Startup-Sound
- for (; index >= 0; index--)
- {
- buzzerFreq = index;
- Delay(10);
- }
- buzzerFreq = 0;
-
- // Wait until button is pressed
- while (gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN))
- {
- // Reload watchdog while button is pressed
- fwdgt_counter_reload();
- }
-#endif
-
- while(1)
- {
-#ifdef MASTER
- steerCounter++;
- if ((steerCounter % 2) == 0)
- {
- // Request steering data
- SendSteerDevice();
- }
-
- // Calculate expo rate for less steering with higher speeds
- expo = MAP((float)ABS(speed), 0, 1000, 1, 0.5);
-
- // Each speedvalue or steervalue between 50 and -50 means absolutely no pwm
- // -> to get the device calm 'around zero speed'
- scaledSpeed = speed < 50 && speed > -50 ? 0 : CLAMP(speed, -1000, 1000) * SPEED_COEFFICIENT;
- scaledSteer = steer < 50 && steer > -50 ? 0 : CLAMP(steer, -1000, 1000) * STEER_COEFFICIENT * expo;
-
- // Map to an angle of 180 degress to 0 degrees for array access (means angle -90 to 90 degrees)
- steerAngle = MAP((float)scaledSteer, -1000, 1000, 180, 0);
- xScale = lookUpTableAngle[(uint16_t)steerAngle];
-
- // Mix steering and speed value for right and left speed
- if(steerAngle >= 90)
- {
- pwmSlave = CLAMP(scaledSpeed, -1000, 1000);
- pwmMaster = CLAMP(pwmSlave / xScale, -1000, 1000);
- }
- else
- {
- pwmMaster = CLAMP(scaledSpeed, -1000, 1000);
- pwmSlave = CLAMP(xScale * pwmMaster, -1000, 1000);
- }
-
- // Read charge state
- chargeStateLowActive = gpio_input_bit_get(CHARGE_STATE_PORT, CHARGE_STATE_PIN);
-
- // Enable is depending on charger is connected or not
- enable = chargeStateLowActive;
-
- // Enable channel output
- SetEnable(enable);
-
- // Decide if slave will be enabled
- enableSlave = (enable == SET && timedOut == RESET) ? SET : RESET;
-
- // Decide which process value has to be sent
- switch(sendSlaveIdentifier)
- {
- case 0:
- sendSlaveValue = currentDC * 100;
- break;
- case 1:
- sendSlaveValue = batteryVoltage * 100;
- break;
- case 2:
- sendSlaveValue = realSpeed * 100;
- break;
- default:
- break;
- }
-
- // Set output
- SetPWM(pwmMaster);
- SendSlave(-pwmSlave, enableSlave, RESET, chargeStateLowActive, sendSlaveIdentifier, sendSlaveValue);
-
- // Increment identifier
- sendSlaveIdentifier++;
- if (sendSlaveIdentifier > 2)
- {
- sendSlaveIdentifier = 0;
- }
-
- // Show green battery symbol when battery level BAT_LOW_LVL1 is reached
- if (batteryVoltage > BAT_LOW_LVL1)
- {
- // Show green battery light
- ShowBatteryState(LED_GREEN);
-
- // Beeps backwards
- BeepsBackwards(beepsBackwards);
- }
- // Make silent sound and show orange battery symbol when battery level BAT_LOW_LVL2 is reached
- else if (batteryVoltage > BAT_LOW_LVL2 && batteryVoltage < BAT_LOW_LVL1)
- {
- // Show orange battery light
- ShowBatteryState(LED_ORANGE);
-
- buzzerFreq = 5;
- buzzerPattern = 8;
- }
- // Make even more sound and show red battery symbol when battery level BAT_LOW_DEAD is reached
- else if (batteryVoltage > BAT_LOW_DEAD && batteryVoltage < BAT_LOW_LVL2)
- {
- // Show red battery light
- ShowBatteryState(LED_RED);
-
- buzzerFreq = 5;
- buzzerPattern = 1;
- }
- // Shut device off, when battery is dead
- else if (batteryVoltage < BAT_LOW_DEAD)
- {
- ShutOff();
- }
- else
- {
- ShutOff();
- }
-
- // Shut device off when button is pressed
- if (gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN))
- {
- while (gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN)) {}
- ShutOff();
- }
-
- // Calculate inactivity timeout (Except, when charger is active -> keep device running)
- if (ABS(pwmMaster) > 50 || ABS(pwmSlave) > 50 || !chargeStateLowActive)
- {
- inactivity_timeout_counter = 0;
- }
- else
- {
- inactivity_timeout_counter++;
- }
-
- // Shut off device after INACTIVITY_TIMEOUT in minutes
- if (inactivity_timeout_counter > (INACTIVITY_TIMEOUT * 60 * 1000) / (DELAY_IN_MAIN_LOOP + 1))
- {
- ShutOff();
- }
-#endif
-
- Delay(DELAY_IN_MAIN_LOOP);
-
- // Reload watchdog (watchdog fires after 1,6 seconds)
- fwdgt_counter_reload();
- }
-}
-
-#ifdef MASTER
-//----------------------------------------------------------------------------
-// Turns the device off
-//----------------------------------------------------------------------------
-void ShutOff(void)
-{
- int index = 0;
-
- buzzerPattern = 0;
- for (; index < 8; index++)
- {
- buzzerFreq = index;
- Delay(10);
- }
- buzzerFreq = 0;
-
- // Send shut off command to slave
- SendSlave(0, RESET, SET, RESET, RESET, RESET);
-
- // Disable usart
- usart_deinit(USART_MASTERSLAVE);
-
- // Set pwm and enable to off
- SetEnable(RESET);
- SetPWM(0);
-
- gpio_bit_write(SELF_HOLD_PORT, SELF_HOLD_PIN, RESET);
- while(1)
- {
- // Reload watchdog until device is off
- fwdgt_counter_reload();
- }
-}
-
-//----------------------------------------------------------------------------
-// Shows the battery state on the LEDs
-//----------------------------------------------------------------------------
-void ShowBatteryState(uint32_t pin)
-{
- gpio_bit_write(LED_GREEN_PORT, LED_GREEN, pin == LED_GREEN ? SET : RESET);
- gpio_bit_write(LED_ORANGE_PORT, LED_ORANGE, pin == LED_ORANGE ? SET : RESET);
- gpio_bit_write(LED_RED_PORT, LED_RED, pin == LED_RED ? SET : RESET);
-}
-
-//----------------------------------------------------------------------------
-// Beeps while driving backwards
-//----------------------------------------------------------------------------
-void BeepsBackwards(FlagStatus beepsBackwards)
-{
- // If the speed is less than -50, beep while driving backwards
- if (beepsBackwards == SET && speed < -50)
- {
- buzzerFreq = 5;
- buzzerPattern = 4;
- }
- else
- {
- buzzerFreq = 0;
- buzzerPattern = 0;
- }
-}
-#endif
diff --git a/PPMDeviceArduino_V1.0/PPMDevice/PPMDevice.ino b/PPMDeviceArduino_V1.0/PPMDevice/PPMDevice.ino
deleted file mode 100644
index 05b28210..00000000
--- a/PPMDeviceArduino_V1.0/PPMDevice/PPMDevice.ino
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "RCReceiver.h"
-#include "SteeringSerial.h"
-#include "utils.h"
-
-void setup()
-{
- // Initialize steering serial
- InitSteeringSerial();
-
- // Enable Debug LED
- pinMode(LED_BUILTIN, OUTPUT);
- digitalWrite(LED_BUILTIN, 1);
-
- // Initialize RC receiver
- InitRCReceiver();
-
- // Start RC receiver
- RCReceiverStart();
-}
-
-void loop()
-{
- uint16_t channel1 = GetRCValue(0);
- uint16_t channel2 = GetRCValue(1);
- uint16_t channel3 = GetRCValue(2);
-
- // Activate/deactivate speed mode
- float factor = channel3 < 1500 ? 0.5 : 1;
-
- // Handle receiver values
- SetSpeed(channel1, factor);
- SetSteer(channel2);
-
-/* SendDebug(); */
-
- // Reply only when you receive data
- if (Serial.available() > 0)
- {
- char character = Serial.read();
- if (character == '\n')
- {
- SendAnswer();
- }
- }
-}
-
diff --git a/PPMDeviceArduino_V1.0/PPMDevice/RCReceiver.cpp b/PPMDeviceArduino_V1.0/PPMDevice/RCReceiver.cpp
deleted file mode 100644
index 812e5250..00000000
--- a/PPMDeviceArduino_V1.0/PPMDevice/RCReceiver.cpp
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "RCReceiver.h"
-
-uint16_t m_pulseStart[SERVOS]; // Last measured pulse start for each input.
-uint16_t m_pulseLength_us[SERVOS]; // Last measured pulse length for each input.
-static uint8_t lastB = 0;
-volatile static bool enable = false;
-volatile static bool pinChangeActive = false;
-
-uint16_t RCReceiverGetStartCount();
-uint16_t RCReceiverGetStopCount(uint8_t p_servo);
-uint16_t RCReceiverGetCnt();
-
-//----------------------------------------------------------------------------
-// Initializes the steering serial
-//----------------------------------------------------------------------------
-void InitRCReceiver(void)
-{
- // Deinitialize timer1
- TCCR1A = 0;
- TCCR1B = 0;
- TCCR1C = 0;
- TIMSK1 = 0;
- OCR1A = 0;
- OCR1B = 0;
- TCNT1 = 0;
-
- // We use pin 8-10 PB0, PB1, PB2 as Servo input pins
- pinMode(8, INPUT);
- pinMode(9, INPUT);
- pinMode(10, INPUT);
-
- // We use pin change interrupts to detect changes in the signal
- // Only allow pin change interrupts for PB0-3 (digital pins 8-10)
- PCMSK0 |= (1 << PCINT0) | (1 << PCINT1) | (1 << PCINT2);
-
- // Enable pin change interrupt 0
- PCICR |= (1 << PCIE0);
-}
-
-//----------------------------------------------------------------------------
-// Starts the receiver
-//----------------------------------------------------------------------------
-void RCReceiverStart()
-{
- // Clean buffers
- for (uint8_t i = 0; i < SERVOS; ++i)
- {
- m_pulseStart[i] = 0;
- m_pulseLength_us[i] = ZERO_US;
- }
-
- // Start Timer 1
- // Timer 1 counts up with 1MHz, so that 1 count = 1us
- // Overflow interrupt after 1000000MHz / 65536 = 0,065536s -> every 65,5ms
- TCCR1B = (TCCR1B & ~(_BV(CS12) | _BV(CS11) | _BV(CS10))) | _BV(CS11);
- TIMSK1 |= _BV(TOIE1);
-}
-
-//----------------------------------------------------------------------------
-// Returns the current result value of specified pin
-//----------------------------------------------------------------------------
-uint16_t GetRCValue(uint8_t pin)
-{
- if (pin < 0 || pin > SERVOS)
- {
- return ZERO_US;
- }
- return m_pulseLength_us[pin];
-}
-
-//----------------------------------------------------------------------------
-// Will be called when a reciever pin changes
-//----------------------------------------------------------------------------
-void RCReceiverPinChanged(uint8_t p_servo, bool p_high)
-{
- if (p_high)
- {
- // Start of pulse
- m_pulseStart[p_servo] = RCReceiverGetStartCount();
- }
- else
- {
- // End of pulse
- m_pulseLength_us[p_servo] = CLAMP(RCReceiverGetStopCount(p_servo), 1000, 2000);
- }
-}
-
-//----------------------------------------------------------------------------
-// Returns the start count of the timer
-//----------------------------------------------------------------------------
-uint16_t RCReceiverGetStartCount()
-{
- uint16_t cnt = RCReceiverGetCnt();
-
- // Start of pulse
- return cnt;
-}
-
-//----------------------------------------------------------------------------
-// Returns the stop count of the specified input pin
-//----------------------------------------------------------------------------
-uint16_t RCReceiverGetStopCount(uint8_t p_servo)
-{
- uint16_t cnt = RCReceiverGetCnt();
-
- // End of pulse
- return (cnt - m_pulseStart[p_servo]) >> 1;
-}
-
-//----------------------------------------------------------------------------
-// Returns the count value of the timer
-//----------------------------------------------------------------------------
-uint16_t RCReceiverGetCnt()
-{
- uint8_t oldSREG = SREG;
- cli();
- uint16_t cnt = TCNT1;
- SREG = oldSREG;
-
- return cnt;
-}
-
-//----------------------------------------------------------------------------
-// Interrupt service routine for timer1 overflow
-//----------------------------------------------------------------------------
-ISR(TIMER1_OVF_vect)
-{
- sei();
-
- // Between two overflow interrupts (every 65,5ms) should be
- // at least one pin change interrupt (receiver pwm period is 6ms)
- if (pinChangeActive)
- {
- enable = true;
- }
- else
- {
- m_pulseLength_us[0] = ZERO_US;
- m_pulseLength_us[1] = ZERO_US;
- m_pulseLength_us[2] = ZERO_US;
- enable = false;
- }
- pinChangeActive = false;
-}
-
-//
-//----------------------------------------------------------------------------
-// Interrupt service routine for pin change port 0 interrupt
-//----------------------------------------------------------------------------
-ISR(PCINT0_vect)
-{
- if (enable == false)
- {
- pinChangeActive = true;
- return;
- }
- pinChangeActive = true;
- uint8_t newB = PINB;
-
- // Bitwise XOR will set all bits that have changed
- uint8_t chgB = newB ^ lastB;
- lastB = newB;
-
- // Has any of the pins changed?
- if (chgB)
- {
- // Find out which pin has changed
- if (chgB & _BV(0))
- {
- RCReceiverPinChanged(0, newB & _BV(0));
- }
- if (chgB & _BV(1))
- {
- RCReceiverPinChanged(1, newB & _BV(1));
- }
- if (chgB & _BV(2))
- {
- RCReceiverPinChanged(2, newB & _BV(2));
- }
- }
-}
diff --git a/PPMDeviceArduino_V1.0/PPMDevice/SteeringSerial.cpp b/PPMDeviceArduino_V1.0/PPMDevice/SteeringSerial.cpp
deleted file mode 100644
index 75717712..00000000
--- a/PPMDeviceArduino_V1.0/PPMDevice/SteeringSerial.cpp
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#include "SteeringSerial.h"
-
-//----------------------------------------------------------------------------
-// Variables
-//----------------------------------------------------------------------------
-int32_t speedValue = 0;
-int32_t steerValue = 0;
-uint8_t upperLEDMaster = 0;
-uint8_t lowerLEDMaster = 0;
-uint8_t mosfetOutMaster = 0;
-uint8_t upperLEDSlave = 0;
-uint8_t lowerLEDSlave = 0;
-uint8_t mosfetOutSlave = 0;
-uint8_t beepsBackwards = 0;
-uint8_t activateWeakening = 0;
-
-void SendBuffer(uint8_t buffer[], uint8_t length);
-uint16_t CalcCRC(uint8_t *ptr, int count);
-
-//----------------------------------------------------------------------------
-// Initializes the steering serial
-//----------------------------------------------------------------------------
-void InitSteeringSerial(void)
-{
- // Set up serial communication
- Serial.begin(19200, SERIAL_8N1);
-}
-
-//----------------------------------------------------------------------------
-// Sets the speed value
-//----------------------------------------------------------------------------
-void SetSpeed(uint16_t data, float factor)
-{
- int16_t tempValue = ((float)data * 2 ) - 3000.0; // Value -1000 to 1000
- tempValue *= factor;
- tempValue = CLAMP(tempValue, -1000, 1000); // Avoid calculation failure
- speedValue = tempValue;
-}
-
-//----------------------------------------------------------------------------
-// Sets the steering value
-//----------------------------------------------------------------------------
-void SetSteer(uint16_t data)
-{
- int16_t tempValue = ((float)data * 2 ) - 3000.0; // Value -1000 to 1000
- tempValue = CLAMP(tempValue, -1000, 1000); // Avoid calculation failure
- if (speedValue < 0)
- {
- steerValue *= -1;
- }
- steerValue = tempValue;
-}
-
-//----------------------------------------------------------------------------
-// Sends answer to master device
-//----------------------------------------------------------------------------
-void SendAnswer(void)
-{
- int index = 0;
- uint8_t buffer[9];
- uint8_t byte1 = 0;
- uint8_t byte2 = 0;
- uint8_t byte3 = 0;
- uint8_t byte4 = 0;
-
- uint8_t sendByte = 0;
- sendByte |= (activateWeakening << 7);
- sendByte |= (beepsBackwards << 6);
- sendByte |= (mosfetOutSlave << 5);
- sendByte |= (lowerLEDSlave << 4);
- sendByte |= (upperLEDSlave << 3);
- sendByte |= (mosfetOutMaster << 2);
- sendByte |= (lowerLEDMaster << 1);
- sendByte |= (upperLEDMaster << 0);
-
- uint16_t speedValue_Format = (uint16_t)(speedValue);
- byte1 |= (speedValue_Format >> 8) & 0xFF;
- byte2 |= speedValue_Format & 0xFF;
-
- uint16_t steerValue_Format = (uint16_t)(steerValue);
- byte3 |= (steerValue_Format >> 8) & 0xFF;
- byte4 |= steerValue_Format & 0xFF;
-
- // Send answer
- buffer[index++] = '/';
- buffer[index++] = byte1;
- buffer[index++] = byte2;
- buffer[index++] = byte3;
- buffer[index++] = byte4;
- buffer[index++] = sendByte;
-
- // Calculate CRC
- uint16_t crc = CalcCRC(buffer, index);
- buffer[index++] = (crc >> 8) & 0xFF;
- buffer[index++] = crc & 0xFF;
-
- // Stop byte
- buffer[index++] = '\n';
-
- SendBuffer(buffer, index);
-}
-
-//----------------------------------------------------------------------------
-// Calculates CRC value
-//----------------------------------------------------------------------------
-uint16_t CalcCRC(uint8_t *ptr, int count)
-{
- uint16_t crc;
- uint8_t i;
- crc = 0;
- while (--count >= 0)
- {
- crc = crc ^ (uint16_t) *ptr++ << 8;
- i = 8;
- do
- {
- if (crc & 0x8000)
- {
- crc = crc << 1 ^ 0x1021;
- }
- else
- {
- crc = crc << 1;
- }
- } while(--i);
- }
- return (crc);
-}
-
-//----------------------------------------------------------------------------
-// Sends buffer
-//----------------------------------------------------------------------------
-void SendBuffer(uint8_t buffer[], uint8_t length)
-{
- uint8_t index = 0;
-
- for(; index < length; index++)
- {
- Serial.write(buffer[index]);
- }
-}
-
-//----------------------------------------------------------------------------
-// Sends debug infos
-//----------------------------------------------------------------------------
-void SendDebug()
-{
- Serial.print(speedValue);
- Serial.print(",");
- Serial.println(steerValue);
-}
diff --git a/PPMDeviceArduino_V1.0/PPMDevice/SteeringSerial.h b/PPMDeviceArduino_V1.0/PPMDevice/SteeringSerial.h
deleted file mode 100644
index 5dd333fe..00000000
--- a/PPMDeviceArduino_V1.0/PPMDevice/SteeringSerial.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#ifndef STEERINGSERIAL_H
-#define STEERINGSERIAL_H
-
-#include
-#include
-#include "utils.h"
-
-//----------------------------------------------------------------------------
-// Initializes the steering serial
-//----------------------------------------------------------------------------
-void InitSteeringSerial(void);
-
-//----------------------------------------------------------------------------
-// Sets the speed value
-//----------------------------------------------------------------------------
-void SetSpeed(uint16_t data, float factor);
-
-//----------------------------------------------------------------------------
-// Sets the steering value
-//----------------------------------------------------------------------------
-void SetSteer(uint16_t data);
-
-//----------------------------------------------------------------------------
-// Sends answer to master device
-//----------------------------------------------------------------------------
-void SendAnswer(void);
-
-
-//----------------------------------------------------------------------------
-// Sends debug infos
-//----------------------------------------------------------------------------
-void SendDebug();
-
-#endif
diff --git a/PPMDeviceArduino_V1.0/PPMDevice/utils.h b/PPMDeviceArduino_V1.0/PPMDevice/utils.h
deleted file mode 100644
index 914cad94..00000000
--- a/PPMDeviceArduino_V1.0/PPMDevice/utils.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
-* This file is part of the hoverboard-firmware-hack-V2 project. The
-* firmware is used to hack the generation 2 board of the hoverboard.
-* These new hoverboards have no mainboard anymore. They consist of
-* two Sensorboards which have their own BLDC-Bridge per Motor and an
-* ARM Cortex-M3 processor GD32F130C8.
-*
-* Copyright (C) 2018 Florian Staeblein
-* Copyright (C) 2018 Jakob Broemauer
-* Copyright (C) 2018 Kai Liebich
-* Copyright (C) 2018 Christoph Lehnert
-*
-* The program is based on the hoverboard project by Niklas Fauth. The
-* structure was tried to be as similar as possible, so that everyone
-* could find a better way through the code.
-*
-* This program is free software: you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation, either version 3 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program. If not, see .
-*/
-
-#ifndef UTILS_H
-#define UTILS_H
-
-#define ABS(a) (((a) < 0.0) ? -(a) : (a))
-#define CLAMP(x, low, high) (((x) > (high)) ? (high) : (((x) < (low)) ? (low) : (x)))
-#define MAP(x, xMin, xMax, yMin, yMax) ((x - xMin) * (yMax - yMin) / (xMax - xMin) + yMin)
-
-#endif
diff --git a/README.md b/README.md
index d06aebdf..e5ff78b3 100644
--- a/README.md
+++ b/README.md
@@ -1,36 +1,68 @@
-#### Updates:
-````
-- Firmware is ready.
-- Sadly I can not support any issues. I'm not a student, less free time :)
-````
-### Hoverboard-Firmware-Hack-Gen2
+### Hoverboard Utility Gateway System (HUGS).
-Hoverboard Hack Firmware Generation 2 for the Hoverboard with the two Mainboards instead of the Sensorboards (See Pictures).
+Based on: Hoverboard-Firmware-Hack-Gen2
-This repo contains open source firmware for generic Hoverboards with two mainboards. It allows you to control the hardware of the new version of hoverboards (like the Mainboard, Motors and Battery) with an arduino or some other steering device for projects like driving armchairs.
+Hackaday Project Page: https://hackaday.io/project/170932-hoverboards-for-assistive-devices
-The structure of the firmware is based on the firmware hack of Niklas Fauth (https://github.com/NiklasFauth/hoverboard-firmware-hack/). Because of a different model of processor (GD32F130C8 instead of STM32F103) it was not possible to use the same firmware and it has to be written from scratch (Different hardware, different, pins, different registers :( )
+More inclusive Repo: https://github.com/gearsincorg/Hoverboards-for-assistive-devices
-- This project requires knowledge of the initial project linked above.
-- At the current point I am not able to support any questions or issues - sorry!
+### Purpose:
+The HUGS project goal is to enable Hoverboards, or Hoverboard drive components to be re-purposed to provide low-cost mobility to other systems, such as assistive devices for the disabled, general purpose robots or other labor saving devices.
+To implement this goal, new code will be developed and installed in existing hoverboards, to provide a generic purpose control protocol. This protocol will be used by external devices to run one or more “hoverboard” type wheels.
+
+### This project requires Rev 3.1 of the Giga Device libraries.
+In Keil compliier, use Project/Manage/Pack Installer and then File/Import and point to the pack file in this repo: GigaDevice.GD32F1x0_DFP.3.1.0.pack
+Ensure this is the device associated with this project.
+
+### Latest release:
+A major modification to the base control strategy was adding several different motor control methods.
+
+The basic method is a simple PWM power control where the the user requests a PWM level from 0 to 1000 and the comutation happens as required by the current sensed position. The resulting speed is an open loop response.
+
+The next method was a closed loop response using the resultant phase transition speed as feedback. A Feed forward control loop with proportional and integral gain was created to regulate the resulting speed. Control input is an actual linear speed in the +/- 5MPS range, expressed in mmPS.
+
+The third method is a low speed closed loop mode that uses a sinusoidal stepper motor sequence to drive the commutation at a fixed rate, depending on the requested speed. The method optains higgly accurate speeds at rates less than about 200 mmPS.
+
+The fourth and final mode is a hybrid of the last two which switches automatically between the low speed stepper mode and the PID control mode.
+
+### Background:
+The popular “Hoverboard” toy uses a somewhat unique drive system. A powerful brushless DC motor has been integrated inside each of the small rubber wheels, and paired with a low cost motor controller. This mechanical/electrical combination provides a compact drive system that produce precise motions, under considerable load, for relatively low cost.
+
+Through reverse engineering the controller electronics and firmware, code is now available which can be modified to provide alternative operation of the drive system (no longer tied to a tilt-and-drive control system).
+
+The goal of HUGS is to reprogram the motor controller to accept external control commands, and return wheel status information. HUGS will permit individual wheels to be commanded to run at set speeds, and to move to specified positions. Current speed and position information will be returned.
+By providing an open control protocol, other groups can develop their own high level control logic to run the drive wheels for a myriad of applications.
+
+This repo contains open source firmware that has been deveoped and tested on HOVER-1 Ultra Hoverboard
---
#### Hardware
-
+My initial Hoverboard purchase was the Hover-1 Ultra. I wanted to do the work on a board that could be purchased by name.
+I chose this model because it looked like the company had several models and was likely to be a more reliable vendor than most "direct from China" vendors.
+
+Ultimately my choice backfired on me because instead of the more common single board controller, this unit had two boards (one master and one slave). So I had to work from a more limited development set of Gen2 hoverboard.
+
+My most upsetting discovery was that when I was all done, I purchased a different model (Maverick vs Ultra) from the same supllier, and discovered that the Ultra code does not translate.
-The hardware has two main boards, which are different equipped. They are connected via USART. Additionally there are some LED PCB connected at X1 and X2 which signalize the battery state and the error state. There is an programming connector for ST-Link/V2 and they break out GND, USART/I2C, 5V on a second pinhead.
+Since I'm realy not able to reverse engineer this new hardware, this my be a throw-away hoverboard.
-The reverse-engineered schematics of the mainboards can be found here:
-https://github.com/flo199213/Hoverboard-Firmware-Hack-Gen2/blob/master/Schematics/HoverBoard_CoolAndFun.pdf
+So "For the record" everything here has been developed on the Hover-1 Ultra unit, and pictures of the controller boards are in the Documentation folder of this repo.
+The HOVER-1 Ultra has two sepparate motor controller boards, usually configured as a master and a slave with a USART Serial port passing commands and data back and forth.
+
+There is a sets of pads that can be used to program the processor using a ST-Link/V2.
+
+There is also a set of pads that can be used for a remote monitor /control port.
---
#### Flashing
-The firmware is built with Keil (free up to 32KByte). To build the firmware, open the Keil project file which is includes in repository. Right to the STM32, there is a debugging header with GND, 3V3, SWDIO and SWCLK. Connect GND, SWDIO and SWCLK to your SWD programmer, like the ST-Link found on many STM devboards.
-- If you never flashed your mainboard before, the controller is locked. To unlock the flash, use STM32 ST-LINK Utility or openOCD.
-- To flash the STM32, use the STM32 ST-LINK Utility as well, ST-Flash utility or Keil by itself.
+The firmware is built with Keil (free up to 32KByte).
+To build the firmware, open the Keil project file (includes in repository).
+
+- If the controller boards contain the original firmware, they will need to be unlocked. To do this, use the STM32 ST-LINK Utility.
+- To flash the STM32, use the STM32 ST-LINK Utility, or use Keil and run the code in debug mode, which will download the code first.
- Hold the powerbutton while flashing the firmware, as the controller releases the power latch and switches itself off during flashing
diff --git a/Schematics/HoverBoard_CoolAndFun.sch b/Schematics/HoverBoard_CoolAndFun.sch
deleted file mode 100644
index 97157b79..00000000
--- a/Schematics/HoverBoard_CoolAndFun.sch
+++ /dev/null
@@ -1,7695 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>Frames for Sheet and Layout</b>
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->DRAWING_NAME
->LAST_DATE_TIME
->SHEET
-Sheet:
-
-
-
-
-
-<b>FRAME</b><p>
-DIN A4, landscape with location and doc. field
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>Resistors, Capacitors, Inductors</b><p>
-Based on the previous libraries:
-<ul>
-<li>r.lbr
-<li>cap.lbr
-<li>cap-fe.lbr
-<li>captant.lbr
-<li>polcap.lbr
-<li>ipc-smd.lbr
-</ul>
-All SMD packages are defined according to the IPC specifications and CECC<p>
-<author>Created by librarian@cadsoft.de</author><p>
-<p>
-for Electrolyt Capacitors see also :<p>
-www.bccomponents.com <p>
-www.panasonic.com<p>
-www.kemet.com<p>
-http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
-<p>
-for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
-
-<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
-<tr valign="top">
-
-<! <td width="10"> </td>
-<td width="90%">
-
-<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
-<P>
-<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
- </B>
- </TD>
- <TD ALIGN=CENTER>
- <B>
- <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
- </B>
- </TD><TD> </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
- 3005P<BR>
- 3006P<BR>
- 3006W<BR>
- 3006Y<BR>
- 3009P<BR>
- 3009W<BR>
- 3009Y<BR>
- 3057J<BR>
- 3057L<BR>
- 3057P<BR>
- 3057Y<BR>
- 3059J<BR>
- 3059L<BR>
- 3059P<BR>
- 3059Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 89P<BR>
- 89W<BR>
- 89X<BR>
- 89PH<BR>
- 76P<BR>
- 89XH<BR>
- 78SLT<BR>
- 78L ALT<BR>
- 56P ALT<BR>
- 78P ALT<BR>
- T8S<BR>
- 78L<BR>
- 56P<BR>
- 78P<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- T18/784<BR>
- 783<BR>
- 781<BR>
- -<BR>
- -<BR>
- -<BR>
- 2199<BR>
- 1697/1897<BR>
- 1680/1880<BR>
- 2187<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 8035EKP/CT20/RJ-20P<BR>
- -<BR>
- RJ-20X<BR>
- -<BR>
- -<BR>
- -<BR>
- 1211L<BR>
- 8012EKQ ALT<BR>
- 8012EKR ALT<BR>
- 1211P<BR>
- 8012EKJ<BR>
- 8012EKL<BR>
- 8012EKQ<BR>
- 8012EKR<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 2101P<BR>
- 2101W<BR>
- 2101Y<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 2102L<BR>
- 2102S<BR>
- 2102Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- EVMCOG<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 43P<BR>
- 43W<BR>
- 43Y<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 40L<BR>
- 40P<BR>
- 40Y<BR>
- 70Y-T602<BR>
- 70L<BR>
- 70P<BR>
- 70Y<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- RT/RTR12<BR>
- RT/RTR12<BR>
- RT/RTR12<BR>
- -<BR>
- RJ/RJR12<BR>
- RJ/RJR12<BR>
- RJ/RJR12<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3250L<BR>
- 3250P<BR>
- 3250W<BR>
- 3250X<BR>
- 3252P<BR>
- 3252W<BR>
- 3252X<BR>
- 3260P<BR>
- 3260W<BR>
- 3260X<BR>
- 3262P<BR>
- 3262W<BR>
- 3262X<BR>
- 3266P<BR>
- 3266W<BR>
- 3266X<BR>
- 3290H<BR>
- 3290P<BR>
- 3290W<BR>
- 3292P<BR>
- 3292W<BR>
- 3292X<BR>
- 3296P<BR>
- 3296W<BR>
- 3296X<BR>
- 3296Y<BR>
- 3296Z<BR>
- 3299P<BR>
- 3299W<BR>
- 3299X<BR>
- 3299Y<BR>
- 3299Z<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66X ALT<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66X ALT<BR>
- -<BR>
- 64W ALT<BR>
- -<BR>
- 64P ALT<BR>
- 64W ALT<BR>
- 64X ALT<BR>
- 64P<BR>
- 64W<BR>
- 64X<BR>
- 66X ALT<BR>
- 66P ALT<BR>
- 66W ALT<BR>
- 66P<BR>
- 66W<BR>
- 66X<BR>
- 67P<BR>
- 67W<BR>
- 67X<BR>
- 67Y<BR>
- 67Z<BR>
- 68P<BR>
- 68W<BR>
- 68X<BR>
- 67Y ALT<BR>
- 67Z ALT<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 5050<BR>
- 5091<BR>
- 5080<BR>
- 5087<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- T63YB<BR>
- T63XB<BR>
- -<BR>
- -<BR>
- -<BR>
- 5887<BR>
- 5891<BR>
- 5880<BR>
- -<BR>
- -<BR>
- -<BR>
- T93Z<BR>
- T93YA<BR>
- T93XA<BR>
- T93YB<BR>
- T93XB<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 8026EKP<BR>
- 8026EKW<BR>
- 8026EKM<BR>
- 8026EKP<BR>
- 8026EKB<BR>
- 8026EKM<BR>
- 1309X<BR>
- 1309P<BR>
- 1309W<BR>
- 8024EKP<BR>
- 8024EKW<BR>
- 8024EKN<BR>
- RJ-9P/CT9P<BR>
- RJ-9W<BR>
- RJ-9X<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3103P<BR>
- 3103Y<BR>
- 3103Z<BR>
- 3103P<BR>
- 3103Y<BR>
- 3103Z<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3105P/3106P<BR>
- 3105W/3106W<BR>
- 3105X/3106X<BR>
- 3105Y/3106Y<BR>
- 3105Z/3105Z<BR>
- 3102P<BR>
- 3102W<BR>
- 3102X<BR>
- 3102Y<BR>
- 3102Z<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMCBG<BR>
- EVMCCG<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 55-1-X<BR>
- 55-4-X<BR>
- 55-3-X<BR>
- 55-2-X<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 50-2-X<BR>
- 50-4-X<BR>
- 50-3-X<BR>
- -<BR>
- -<BR>
- -<BR>
- 64P<BR>
- 64W<BR>
- 64X<BR>
- 64Y<BR>
- 64Z<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RT/RTR22<BR>
- RJ/RJR22<BR>
- RJ/RJR22<BR>
- RJ/RJR22<BR>
- RT/RTR26<BR>
- RT/RTR26<BR>
- RT/RTR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RJ/RJR26<BR>
- RT/RTR24<BR>
- RT/RTR24<BR>
- RT/RTR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- RJ/RJR24<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=8>
- <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
- </TD>
- <TD ALIGN=CENTER>
- <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3323P<BR>
- 3323S<BR>
- 3323W<BR>
- 3329H<BR>
- 3329P<BR>
- 3329W<BR>
- 3339H<BR>
- 3339P<BR>
- 3339W<BR>
- 3352E<BR>
- 3352H<BR>
- 3352K<BR>
- 3352P<BR>
- 3352T<BR>
- 3352V<BR>
- 3352W<BR>
- 3362H<BR>
- 3362M<BR>
- 3362P<BR>
- 3362R<BR>
- 3362S<BR>
- 3362U<BR>
- 3362W<BR>
- 3362X<BR>
- 3386B<BR>
- 3386C<BR>
- 3386F<BR>
- 3386H<BR>
- 3386K<BR>
- 3386M<BR>
- 3386P<BR>
- 3386S<BR>
- 3386W<BR>
- 3386X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 25P<BR>
- 25S<BR>
- 25RX<BR>
- 82P<BR>
- 82M<BR>
- 82PA<BR>
- -<BR>
- -<BR>
- -<BR>
- 91E<BR>
- 91X<BR>
- 91T<BR>
- 91B<BR>
- 91A<BR>
- 91V<BR>
- 91W<BR>
- 25W<BR>
- 25V<BR>
- 25P<BR>
- -<BR>
- 25S<BR>
- 25U<BR>
- 25RX<BR>
- 25X<BR>
- 72XW<BR>
- 72XL<BR>
- 72PM<BR>
- 72RX<BR>
- -<BR>
- 72PX<BR>
- 72P<BR>
- 72RXW<BR>
- 72RXL<BR>
- 72X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- T7YB<BR>
- T7YA<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- TXD<BR>
- TYA<BR>
- TYP<BR>
- -<BR>
- TYD<BR>
- TX<BR>
- -<BR>
- 150SX<BR>
- 100SX<BR>
- 102T<BR>
- 101S<BR>
- 190T<BR>
- 150TX<BR>
- 101<BR>
- -<BR>
- -<BR>
- 101SX<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ET6P<BR>
- ET6S<BR>
- ET6X<BR>
- RJ-6W/8014EMW<BR>
- RJ-6P/8014EMP<BR>
- RJ-6X/8014EMX<BR>
- TM7W<BR>
- TM7P<BR>
- TM7X<BR>
- -<BR>
- 8017SMS<BR>
- -<BR>
- 8017SMB<BR>
- 8017SMA<BR>
- -<BR>
- -<BR>
- CT-6W<BR>
- CT-6H<BR>
- CT-6P<BR>
- CT-6R<BR>
- -<BR>
- CT-6V<BR>
- CT-6X<BR>
- -<BR>
- -<BR>
- 8038EKV<BR>
- -<BR>
- 8038EKX<BR>
- -<BR>
- -<BR>
- 8038EKP<BR>
- 8038EKZ<BR>
- 8038EKW<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- 3321H<BR>
- 3321P<BR>
- 3321N<BR>
- 1102H<BR>
- 1102P<BR>
- 1102T<BR>
- RVA0911V304A<BR>
- -<BR>
- RVA0911H413A<BR>
- RVG0707V100A<BR>
- RVA0607V(H)306A<BR>
- RVA1214H213A<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 3104B<BR>
- 3104C<BR>
- 3104F<BR>
- 3104H<BR>
- -<BR>
- 3104M<BR>
- 3104P<BR>
- 3104S<BR>
- 3104W<BR>
- 3104X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- EVMQ0G<BR>
- EVMQIG<BR>
- EVMQ3G<BR>
- EVMS0G<BR>
- EVMQ0G<BR>
- EVMG0G<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMK4GA00B<BR>
- EVM30GA00B<BR>
- EVMK0GA00B<BR>
- EVM38GA00B<BR>
- EVMB6<BR>
- EVLQ0<BR>
- -<BR>
- EVMMSG<BR>
- EVMMBG<BR>
- EVMMAG<BR>
- -<BR>
- -<BR>
- EVMMCS<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- EVMM1<BR>
- -<BR>
- -<BR>
- EVMM0<BR>
- -<BR>
- -<BR>
- EVMM3<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- 62-3-1<BR>
- 62-1-2<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 67R<BR>
- -<BR>
- 67P<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- 67X<BR>
- 63V<BR>
- 63S<BR>
- 63M<BR>
- -<BR>
- -<BR>
- 63H<BR>
- 63P<BR>
- -<BR>
- -<BR>
- 63X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- RJ/RJR50<BR>
- RJ/RJR50<BR>
- RJ/RJR50<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
-</TABLE>
-<P> <P>
-<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
- <TR>
- <TD COLSPAN=7>
- <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
- <P>
- <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3224G<BR>
- 3224J<BR>
- 3224W<BR>
- 3269P<BR>
- 3269W<BR>
- 3269X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 44G<BR>
- 44J<BR>
- 44W<BR>
- 84P<BR>
- 84W<BR>
- 84X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- ST63Z<BR>
- ST63Y<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- ST5P<BR>
- ST5W<BR>
- ST5X<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=7>
- </TD>
- </TR>
- <TR>
- <TD COLSPAN=7>
- <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
- </TD>
- <TD>
- <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
- </TD>
- </TR>
- <TR>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 3314G<BR>
- 3314J<BR>
- 3364A/B<BR>
- 3364C/D<BR>
- 3364W/X<BR>
- 3313G<BR>
- 3313J<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- 23B<BR>
- 23A<BR>
- 21X<BR>
- 21W<BR>
- -<BR>
- 22B<BR>
- 22A<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ST5YL/ST53YL<BR>
- ST5YJ/5T53YJ<BR>
- ST-23A<BR>
- ST-22B<BR>
- ST-22<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- ST-4B<BR>
- ST-4A<BR>
- -<BR>
- -<BR>
- -<BR>
- ST-3B<BR>
- ST-3A<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- EVM-6YS<BR>
- EVM-1E<BR>
- EVM-1G<BR>
- EVM-1D<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- G4B<BR>
- G4A<BR>
- TR04-3S1<BR>
- TRG04-2S1<BR>
- -<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
- -<BR>
- -<BR>
- DVR-43A<BR>
- CVR-42C<BR>
- CVR-42A/C<BR>
- -<BR>
- -<BR></FONT>
- </TD>
- </TR>
-</TABLE>
-<P>
-<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
-<P>
-
-
-<P>
-</td>
-</tr>
-</table>
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b> wave soldering<p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-wave soldering
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b> wave soldering<p>
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.10 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.12 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.10 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.12 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-MELF 0.25 W
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0204, grid 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0204, grid 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0204, grid 2.5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 10 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 12 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 15mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 2.5 mm
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 5 mm
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0207, grid 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0309, grid 10mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0309, grid 12.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0309, grid 2.5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0411, grid 12.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0411, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0411, grid 3.81 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0414, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0414, grid 5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0617, grid 17.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0617, grid 22.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0617, grid 5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0922, grid 22.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>RESISTOR</b><p>
-type 0613, grid 5 mm
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b><p>
-type 0613, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type 0817, grid 22.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-0817
-
-
-
-
-<b>RESISTOR</b><p>
-type 0817, grid 6.35 mm
-
-
-
-
-
-
->NAME
->VALUE
-0817
-
-
-
-<b>RESISTOR</b><p>
-type V234, grid 12.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type V235, grid 17.78 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>RESISTOR</b><p>
-type V526-0, grid 2.5 mm
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC2211</b> Reflow Soldering<p>
-source Beyschlag
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC2211</b> Wave Soldering<p>
-source Beyschlag
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC3715</b> Reflow Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC3715</b> Wave Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC6123</b> Reflow Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CECC Size RC6123</b> Wave Soldering<p>
-source Beyschlag
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>RESISTOR</b><p>
-type 0922, grid 7.5 mm
-
-
-
-
-
-
->NAME
->VALUE
-0922
-
-
-
-<b>RESISTOR</b><p>
-type RDH, grid 15 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-RDH
-
-
-
-
-<b>Mini MELF 0102 Axial</b>
-
-
-
-
->NAME
->VALUE
-
-
-
-<b>RESISTOR</b> chip<p>
-Source: http://www.vishay.com/docs/20008/dcrcw.pdf
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR52<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR53<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR54<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR55<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RBR56<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RNC55<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
-MIL SIZE RNC60<br>
-Source: VISHAY .. vta56.pdf
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Package 4527</b><p>
-Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Wirewound Resistors, Precision Power</b><p>
-Source: VISHAY wscwsn.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
-Source: http://www.vishay.com .. dcrcw.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
-Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)</b><p>
-Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b><p>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 2.4 x 4.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 2.5 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 3 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 4 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 5 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm, outline 6 x 5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 2.4 x 4.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 2.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 4.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 3 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 5.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 7.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 3.2 x 10.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 4.2 x 10.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 5.2 x 10.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm, outline 4.3 x 13.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm, outline 5.4 x 13.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm, outline 6.4 x 13.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 5.4 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 6.4 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 7.2 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 8.4 x 18.3 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 15 mm, outline 9.1 x 18.2 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 6.2 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 7.4 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 8.7 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 10.8 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 22.5 mm, outline 11.3 x 26.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 9.3 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 11.3 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 13.4 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 20.5 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 32.5 mm, outline 13.7 x 37.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 32.5 mm, outline 16.2 x 37.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 32.5 mm, outline 18.2 x 37.4 mm
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 37.5 mm, outline 19.2 x 41.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 37.5 mm, outline 20.3 x 41.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 5 mm, outline 3.5 x 7.5 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 37.5 mm, outline 15.5 x 41.8 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 7.5 mm, outline 6.3 x 10.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 15.4 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>CAPACITOR</b><p>
-grid 27.5 mm, outline 17.3 x 31.6 mm
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
-Metric Code Size 1005
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
-Metric Code Size 1608
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
-Metric Code Size 2012
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
-Metric Code Size 3216
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
-Metric Code Size 3225
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
-Metric Code Size 4532
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
-Metric Code Size 4564
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b> </b><p>
-Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
-
-
->NAME
->VALUE
-
-
-
-Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
-
-
->NAME
->VALUE
-
-
-
-
-
-
-<b>CAPACITOR</b><p>
-Source: AVX .. aphvc.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b><p>
-Source: AVX .. aphvc.pdf
-
-
-
-
->NAME
->VALUE
-
-
-
-
-<b>CAPACITOR</b>
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-RESISTOR
-
-
-RESISTOR
-
-
-RESISTOR
-
-
-RESISTOR wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-
-
-RESISTOR
-wave soldering
-
-
-RESISTOR
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-RESISTOR wave soldering
-Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
-
-
-RESISTOR
-MELF 0.10 W
-
-
-RESISTOR
-MELF 0.25 W
-
-
-RESISTOR
-MELF 0.12 W
-
-
-RESISTOR
-MELF 0.10 W
-
-
-RESISTOR
-MELF 0.25 W
-
-
-RESISTOR
-MELF 0.25 W
-
-
-RESISTOR
-MELF 0.12 W
-
-
-RESISTOR
-MELF 0.25 W
-
-
-RESISTOR
-type 0204, grid 5 mm
-
-
-RESISTOR
-type 0204, grid 7.5 mm
-
-
-RESISTOR
-type 0204, grid 2.5 mm
-
-
-RESISTOR
-type 0207, grid 10 mm
-
-
-RESISTOR
-type 0207, grid 12 mm
-
-
-RESISTOR
-type 0207, grid 15mm
-
-
-RESISTOR
-type 0207, grid 2.5 mm
-
-
-RESISTOR
-type 0207, grid 5 mm
-
-
-RESISTOR
-type 0207, grid 7.5 mm
-
-
-RESISTOR
-type 0309, grid 10mm
-
-
-RESISTOR
-type 0309, grid 12.5 mm
-
-
-RESISTOR
-type 0309, grid 2.5 mm
-
-
-RESISTOR
-type 0411, grid 12.5 mm
-
-
-RESISTOR
-type 0411, grid 15 mm
-
-
-RESISTOR
-type 0411, grid 3.81 mm
-
-
-RESISTOR
-type 0414, grid 15 mm
-
-
-RESISTOR
-type 0414, grid 5 mm
-
-
-RESISTOR
-type 0617, grid 17.5 mm
-
-
-RESISTOR
-type 0617, grid 22.5 mm
-
-
-RESISTOR
-type 0617, grid 5 mm
-
-
-RESISTOR
-type 0922, grid 22.5 mm
-
-
-RESISTOR
-type 0613, grid 5 mm
-
-
-RESISTOR
-type 0613, grid 15 mm
-
-
-RESISTOR
-type 0817, grid 22.5 mm
-
-
-RESISTOR
-type 0817, grid 6.35 mm
-
-
-RESISTOR
-type V234, grid 12.5 mm
-
-
-RESISTOR
-type V235, grid 17.78 mm
-
-
-RESISTOR
-type V526-0, grid 2.5 mm
-
-
-CECC Size RC2211 Reflow Soldering
-source Beyschlag
-
-
-CECC Size RC2211 Wave Soldering
-source Beyschlag
-
-
-CECC Size RC3715 Reflow Soldering
-source Beyschlag
-
-
-CECC Size RC3715 Wave Soldering
-source Beyschlag
-
-
-CECC Size RC6123 Reflow Soldering
-source Beyschlag
-
-
-CECC Size RC6123 Wave Soldering
-source Beyschlag
-
-
-RESISTOR
-type 0922, grid 7.5 mm
-
-
-RESISTOR
-type RDH, grid 15 mm
-
-
-Mini MELF 0102 Axial
-
-
-RESISTOR chip
-Source: http://www.vishay.com/docs/20008/dcrcw.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR52
-Source: VISHAY .. vta56.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR53
-Source: VISHAY .. vta56.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR54
-Source: VISHAY .. vta56.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR55
-Source: VISHAY .. vta56.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RBR56
-Source: VISHAY .. vta56.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RNC55
-Source: VISHAY .. vta56.pdf
-
-
-Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements
-MIL SIZE RNC60
-Source: VISHAY .. vta56.pdf
-
-
-Package 4527
-Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-Wirewound Resistors, Precision Power
-Source: VISHAY wscwsn.pdf
-
-
-CRCW1218 Thick Film, Rectangular Chip Resistors
-Source: http://www.vishay.com .. dcrcw.pdf
-
-
-Chip Monolithic Ceramic Capacitors Medium Voltage High Capacitance for General Use
-Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
-
-
-PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)
-Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf
-
-
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-
-
-CAPACITOR
-grid 2.5 mm, outline 2.4 x 4.4 mm
-
-
-CAPACITOR
-grid 2.5 mm, outline 2.5 x 5 mm
-
-
-CAPACITOR
-grid 2.5 mm, outline 3 x 5 mm
-
-
-CAPACITOR
-grid 2.5 mm, outline 4 x 5 mm
-
-
-CAPACITOR
-grid 2.5 mm, outline 5 x 5 mm
-
-
-CAPACITOR
-grid 2.5 mm, outline 6 x 5 mm
-
-
-CAPACITOR
-grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
-
-
-CAPACITOR
-grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
-
-
-CAPACITOR
-grid 5 mm, outline 2.4 x 4.4 mm
-
-
-CAPACITOR
-grid 5 mm, outline 2.5 x 7.5 mm
-
-
-CAPACITOR
-grid 5 mm, outline 4.5 x 7.5 mm
-
-
-CAPACITOR
-grid 5 mm, outline 3 x 7.5 mm
-
-
-CAPACITOR
-grid 5 mm, outline 5 x 7.5 mm
-
-
-CAPACITOR
-grid 5 mm, outline 5.5 x 7.5 mm
-
-
-CAPACITOR
-grid 5 mm, outline 7.5 x 7.5 mm
-
-
-CAPACITOR
-Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
-
-
-CAPACITOR
-grid 7.5 mm, outline 3.2 x 10.3 mm
-
-
-CAPACITOR
-grid 7.5 mm, outline 4.2 x 10.3 mm
-
-
-CAPACITOR
-grid 7.5 mm, outline 5.2 x 10.6 mm
-
-
-CAPACITOR
-grid 10.2 mm, outline 4.3 x 13.3 mm
-
-
-CAPACITOR
-grid 10.2 mm, outline 5.4 x 13.3 mm
-
-
-CAPACITOR
-grid 10.2 mm, outline 6.4 x 13.3 mm
-
-
-CAPACITOR
-grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
-
-
-CAPACITOR
-grid 15 mm, outline 5.4 x 18.3 mm
-
-
-CAPACITOR
-grid 15 mm, outline 6.4 x 18.3 mm
-
-
-CAPACITOR
-grid 15 mm, outline 7.2 x 18.3 mm
-
-
-CAPACITOR
-grid 15 mm, outline 8.4 x 18.3 mm
-
-
-CAPACITOR
-grid 15 mm, outline 9.1 x 18.2 mm
-
-
-CAPACITOR
-grid 22.5 mm, outline 6.2 x 26.8 mm
-
-
-CAPACITOR
-grid 22.5 mm, outline 7.4 x 26.8 mm
-
-
-CAPACITOR
-grid 22.5 mm, outline 8.7 x 26.8 mm
-
-
-CAPACITOR
-grid 22.5 mm, outline 10.8 x 26.8 mm
-
-
-CAPACITOR
-grid 22.5 mm, outline 11.3 x 26.8 mm
-
-
-CAPACITOR
-grid 27.5 mm, outline 9.3 x 31.6 mm
-
-
-CAPACITOR
-grid 27.5 mm, outline 11.3 x 31.6 mm
-
-
-CAPACITOR
-grid 27.5 mm, outline 13.4 x 31.6 mm
-
-
-CAPACITOR
-grid 27.5 mm, outline 20.5 x 31.6 mm
-
-
-CAPACITOR
-grid 32.5 mm, outline 13.7 x 37.4 mm
-
-
-CAPACITOR
-grid 32.5 mm, outline 16.2 x 37.4 mm
-
-
-CAPACITOR
-grid 32.5 mm, outline 18.2 x 37.4 mm
-
-
-CAPACITOR
-grid 37.5 mm, outline 19.2 x 41.8 mm
-
-
-CAPACITOR
-grid 37.5 mm, outline 20.3 x 41.8 mm
-
-
-CAPACITOR
-grid 5 mm, outline 3.5 x 7.5 mm
-
-
-CAPACITOR
-grid 37.5 mm, outline 15.5 x 41.8 mm
-
-
-CAPACITOR
-grid 7.5 mm, outline 6.3 x 10.6 mm
-
-
-CAPACITOR
-grid 27.5 mm, outline 15.4 x 31.6 mm
-
-
-CAPACITOR
-grid 27.5 mm, outline 17.3 x 31.6 mm
-
-
-Ceramic Chip Capacitor KEMET 0204 reflow solder
-Metric Code Size 1005
-
-
-Ceramic Chip Capacitor KEMET 0603 reflow solder
-Metric Code Size 1608
-
-
-Ceramic Chip Capacitor KEMET 0805 reflow solder
-Metric Code Size 2012
-
-
-Ceramic Chip Capacitor KEMET 1206 reflow solder
-Metric Code Size 3216
-
-
-Ceramic Chip Capacitor KEMET 1210 reflow solder
-Metric Code Size 3225
-
-
-Ceramic Chip Capacitor KEMET 1812 reflow solder
-Metric Code Size 4532
-
-
-Ceramic Chip Capacitor KEMET 1825 reflow solder
-Metric Code Size 4564
-
-
-Ceramic Chip Capacitor KEMET 2220 reflow solderMetric Code Size 5650
-
-
-Ceramic Chip Capacitor KEMET 2225 reflow solderMetric Code Size 5664
-
-
-
-Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
-
-
-Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
-
-
-CAPACITOR
-Source: AVX .. aphvc.pdf
-
-
-CAPACITOR
-Source: AVX .. aphvc.pdf
-
-
-CAPACITOR
-
-
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
->NAME
->VALUE
-
-
-
-
-
-
-
-
-<B>RESISTOR</B>, European symbol
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<B>CAPACITOR</B>, European symbol
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>Supply Symbols</b><p>
- GND, VCC, 0V, +5V, -5V, etc.<p>
- Please keep in mind, that these devices are necessary for the
- automatic wiring of the supply signals.<p>
- The pin name defined in the symbol is identical to the net which is to be wired automatically.<p>
- In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p>
- <author>Created by librarian@cadsoft.de</author>
-
-
-
-
-
->VALUE
-
-
-
-
-
->VALUE
-
-
-
-
-
->VALUE
-
-
-
-
-
-<b>SUPPLY SYMBOL</b>
-
-
-
-
-
-
-
-
-
-
-
-
-<b>SUPPLY SYMBOL</b>
-
-
-
-
-
-
-
-
-
-
-
-
-<b>SUPPLY SYMBOL</b>
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-<b>Power Transistors</b><p>
-<author>Created by librarian@cadsoft.de</author>
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
->NAME
->VALUE
-D
-S
-G
-
-
-
-
-
-
-
-N-CHANNEL MOS FET <b>SYMBOL</b>
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-© Copyright Florian Stäblein 2018
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-12V
-12V
-1
-1
-1
-2
-2
-3
-4
-5
-VBAT
-VBAT
-3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-X1
-X2
-X3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-SC
-GND
-SB
-SA
-
-
-T
-5V
-
-
-
-
-
-HALL
-
-
-
-
-
-
-
-
-
-
-
-
-
-RX
-GND
-TX
-
-
-5V
-
-
-
-
-
-USART
-
-
-
-
-K1
-K2
-
-
-
-
-
-SWITCH
-
-
-
-
-
-
-
-
-
-VBAT
-
-
-VBAT
-GND
-
-
-
-
-
-
-
-CHARGE
-
-
-GND
-
-
-
-
-
-CHARGER
-
-
-
-
-
-VBAT
-
-
-
-
-GND
-
-
-
-
-Y
-
-
-
-
-B
-
-
-
-
-G
-
-
-
-
-L2
-
-
-
-
-L1
-
-
-
-
-
-
-
-
-T
-5V
-R
-
-
-GND
-
-
-
-
-
-REMOTE
-
-
-
-
-
-
-
-
-
-D
-3,3V
-C
-
-
-GND
-
-
-
-
-
-ST-LINK
-
-
-
-PHASE GREEN
-PHASE BLUE
-PHASE YELLOW
-
-
-LIGHT BARRIER
-LIGHT BARRIER
-
-
-BATTERY-
-BATTERY+
-
-B
-BUZZER
-X1.1: PA15 (out)
-X1.2: PA12 (out)
-X1.3: PB13 (out)
-X1.4: N/A (PB4)
-X1.5: N/A (PB5)
-
-X2.1: PA1 (out)
-X2.2: PA0 (out)
-X2.3: N/A (connected with X3.1)
-
-X3.1: PC13 (out)
-X4.SC: PC14 (in)
-X4.SB: PF1 (in)
-X4.SA: PB11 (in)
-
-X5.RX: PA3 (in, USART1)
-X5.TX: PA2 (out, USART1)
-
-BUZZER.B: PB10 (out)
-SWITCH.K1: PC15 (in)
-LATCH: PB2 (out)
-G_High: PA10 (out) TIM0_CH3
-G_Low : PB15 (out) TIM0_CH3N
-B_High: PA9 (out) TIM0_CH2
-B_Low : PB14 (out) TIM0_CH2N
-Y_High: PA8 (out) TIM0_CH1
-Y_Low : PB13 (out) TIM0_CH1N
-Controller: GD32F130C8
-Cool&Fun TT-SD2.2
-V_BATT: PA4 (analog)
-CURRENT_DC: PA6 (analog)
-EMERGENCY_OFF: PB12 (in) TIM0_Break_Input
-CHARGE_STATE: PF0 (in, pullup)
-
-unused: PB4, PB5, PA6
-L1: PA7 (in)
-L2: PA11 (in)
-
-REMOTE.R: PB7 (I2C1_SDA / USART0_RX)
-REMOTE.T: PB6 (I2C1_SCL / USART0_TX)
-MPU6050.SDA: PB9 (I2C2)
-MPU6050.SCL: PB8 (I2C2)
-
-
-
-
-
-
-
-
-
-
-
-© Copyright Florian Stäblein 2018
-HALL
-HALL (SA / SB / SC)
-uC
-
-
-
-
-
-
-
-
-Low-Pass
-Pullup
-
-USART
-RX
-uC, PA3
-
-
-
-
-
-Protective resistance
-TX
-uC, PA2
-
-
-Battery measurement
-uC, PA4
-Battery voltage
-Ubatt_measure = ( ADC / 4096 - 1 ) * 3,3V * 30
-
-0,004 Ohm
-uC, PA6
-uC, PB12
-Uthgs = 600mV (=150A Shunt) --> short circuit detection
-3,3V * 1/3 - 0,004Ohm * IL(ampere) = (ADC-Data/4095) *3,3V
-Current measurement
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-Since Version 6.2.2 text objects can contain more than one line,
-which will not be processed correctly with this version.
-
-
-Since Version 8.2, EAGLE supports online libraries. The ids
-of those online libraries will not be understood (or retained)
-with this version.
-
-
-Since Version 8.3, EAGLE supports URNs for individual library
-assets (packages, symbols, and devices). The URNs of those assets
-will not be understood (or retained) with this version.
-
-
-Since Version 8.3, EAGLE supports the association of 3D packages
-with devices in libraries, schematics, and board files. Those 3D
-packages will not be understood (or retained) with this version.
-
-
-