[Enhancement] Coverpoint Transition Bin support

[BanuAdrian]

Summary

SystemVerilog covergroups support transition bins to track sequences of value transitions (e.g., state0->state1) in coverage. PyVSC currently does not offer this feature and its documentation lists transition bins as unsupported.

Request

• Can you clarify if there are any plans, ongoing work, or roadblocks regarding transition (sequence) coverage bin support in PyVSC?
• Is this enhancement open for community contribution?

Motivation

Transition coverage is essential for protocol and FSM verification and would help PyVSC reach feature parity with SystemVerilog.

Thank you!

[mballance]

Hi @BanuAdrian, I don't currently have ongoing work to support transition bins and would welcome contributions. The mechanics of collecting/monitoring transition coverage are pretty straightforward. I'd start with how the user expresses these features. SystemVerilog uses SVA-like syntax that I suspect won't nicely map to Python.