feat(igla): Wave Loop 766 — module-scope [351][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1737) (#1474)

gHashTag · web-flow · commit 12b7efa8a39d · 2026-07-24T00:35:56.000+07:00
Closes #1737. 🤖 Generated with [Claude Code](https://claude.com/claude-code)
diff --git a/.claude/plans/wave-loop-767.md b/.claude/plans/wave-loop-767.md
@@ -0,0 +1,48 @@
+# Wave Loop 767 Plan — Issue #1738
+
+## Phase 1: Issue
+- Confirm W767 issue #1738 and branch `wave-loop-767`.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w767.py` derived from `scripts/gen_w766.py`.
+- Constants: `OUTER = 353`, `TOTAL = 22592`, `LAST_IDX = 352`, `MID_IDX = 176`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+
+## Phase 4: Impl
+- Add integration test `accepts_w767_bench_module_353x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs`.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./bootstrap/target/release/t27c seal --save specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./bootstrap/target/release/t27c parse ...`
+- `./bootstrap/target/release/t27c icarus-lowerable ...`
+- `./bootstrap/target/release/t27c icarus-simulate ...` (17 cycles)
+- `./bootstrap/target/release/t27c icarus-cocotb ...`
+- `cargo test -p t27c --bin t27c`
+- `cargo test -p tri`
+- `cargo test -p t27c --test icarus_lowerable`
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 767 — module-scope [353][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1738)`.
+- Push `wave-loop-767`, open PR, merge to `master`, create `wave-loop-768`.
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `skills-wave-loop-recipe.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[355][2]^6 Pt` (~0.694 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the same width.
+- **C:** add conditional (`if`) indexed writes at the current width.
diff --git a/.trinity/current-issue.md b/.trinity/current-issue.md
@@ -25,15 +25,15 @@ field writes and `assert_eq` read-back in a `bench` block.
 ## Technical notes
 
 - Shape: `[351][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `351 × 64 = 22,464`.
-- Packed vector width: `22,464 × 32 = 718,848` bits (~0.686 MiBit).
+- Total elements: `351 x 64 = 22,464`.
+- Packed vector width: `22,464 x 32 = 718,848` bits (~0.686 MiBit).
 - `MID_IDX = 175`; frame-condition element `[175][1][0][0][0][0][0]` is element
   `175*64 + 32 = 11,232`.
 - Generator script: `scripts/gen_w766.py` (copy from `scripts/gen_w765.py`, set
   `OUTER = 351` and `MID_IDX = 175`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
-- Include `make_grid(32768)` period-identity check because `32768 ≡ 0 (mod 32768)`.
+- Include `make_grid(32768)` period-identity check because `32768 == 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
diff --git a/.trinity/current_task/activity.md b/.trinity/current_task/activity.md
@@ -3672,3 +3672,7 @@
 - **Commit:** feat(igla): Wave Loop 764 — module-scope [347][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes
 - **Files:** .claude/plans/wave-loop-766.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w765_bench_module_349x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md,scripts/gen_w765.py,specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27
 
+## 2026-07-23T17:32:04Z — wave-loop-766
+- **Commit:** feat(igla): Wave Loop 765 — module-scope [349][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1736)
+- **Files:** .claude/plans/wave-loop-767.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w766_bench_module_351x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md,scripts/gen_w766.py,specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27
+
diff --git a/.trinity/experience.md b/.trinity/experience.md
@@ -75,6 +75,85 @@
   - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
     7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
 
+---
+
+## 2026-07-23 — Wave Loop 766 (module-scope `[351][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
+
+### What worked
+- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 351.
+  The `[351][2]^6 Pt` witness is 718,848 bits (~0.686 MiBit), still well under the 4-MiBit
+  cliff, and required no compiler changes.
+- A module-level `pub var dst : [351][2]^6 Pt` can be initialized from a function
+  call and exercised with indexed signed field writes, with zero compiler changes.
+- The cocotb/Python reference model correctly mirrored the row-major flattening
+  with outer stride 351, confirming the layout is preserved end-to-end.
+- Reused the corrected W632 element-index formula for mid-row expected values:
+  `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
+- For `OUTER = 351`, `MID_IDX = 175`; the frame-condition element is
+  `[175][1][0][0][0][0][0]`, element number `175*64 + 32 = 11,232`.
+- Updated weak-point audit: 40 of 49 30-day commits include `Closes #N` (≈82%).
+  Clean non-worktree scan: 53 of 893 `.t27` specs lack `test`/`invariant`/`bench`
+  (≈5.9%). 19 `scripts/*.sh` remain under `scripts/`.
+- Fresh 2025-2026 literature scan surfaced TeLLMe/TeLLMe v2, TerEffic, the
+  ISPASS 2026 LUT-based ternary accelerator generator, 5500FP/GargantuRAM,
+  Trinity v2.0.x, and recent CNTFET ternary full-adder work in IEEE TCAD/AEU.
+
+### What changed behavior
+- No changes to `bootstrap/src/compiler.rs`.
+- No changes to `bootstrap/stage0/FROZEN_HASH`.
+- No changes to `scripts/cocotb_ref_model.py`.
+- Added `specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27` (~1,536 KB /
+  ~66,751 lines) with seal and Icarus baseline.
+- Added integration test `accepts_w766_bench_module_351x2p6_aos_var_call_write`.
+- Added generator script `scripts/gen_w766.py`.
+
+### Validation
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
+- `cargo test -p tri`: 78 passed; 0 failed.
+- `cargo test -p t27c --test icarus_lowerable`: 226 passed; 0 failed.
+- Direct `t27c parse` W766: PASS.
+- Direct `t27c icarus-lowerable` W766: PASS (`lowerable`).
+- Direct `t27c icarus-simulate` W766: PASS (17 cycles, PASSED).
+- Direct `t27c icarus-cocotb` W766: PASS (`reference-model OK`).
+
+### Scientific / engineering background
+- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
+  packed dimensions, with no power-of-two restriction. Variant A emits a single
+  718,848-bit packed vector, which is legal SystemVerilog.
+- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
+  flattening nested arrays to wide packed vectors is a well-founded compiler
+  discipline, even when outer dimensions are non-power-of-two.
+- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
+  structs; t27 scalar flattening avoids that construct entirely.
+- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
+  unsupported in the native frontend; t27 packed-vector lowering avoids the
+  gap.
+- 2025-2026 ternary/MVL literature scan found:
+  - TeLLMe v2 / TeLLMe — end-to-end ternary LLM accelerators on AMD KV260 using
+    table-lookup matmul (25/143 tok/s decode/prefill under 5 W; arXiv 2025).
+  - TerEffic — Alveo U280 ternary LLM accelerator, 16,300 tok/s at 455 tok/s/W
+    for 370M model (arXiv 2025).
+  - Hardware Generation and Exploration of LUT-Based Accelerators for 1.58-bit
+    LLM Inference — open-source generator + cost model, TSMC 16 nm, accepted at
+    IEEE ISPASS 2026 (arXiv 2026).
+  - 5500FP / GargantuRAM — 24-trit balanced ternary RISC processor on Efinix
+    Trion FPGA at 20 MHz, 120-instruction ISA, real ±3.3 V ternary I/O,
+    CERN-OHL-P v2 board, commercially available (Zenodo/GitHub 2026).
+  - Trinity B002 / Trinity v2.0.x — zero-DSP ternary-weight autoregressive LLM
+    inference on Xilinx Artix-7 via OpenXC7, ~63 tok/s @ ~1 W, QMTech XC7A100T
+    (Zenodo 2026).
+  - Unbalanced ternary full adder in CNTFET — 42-transistor multi-threshold
+    design with 35.8–75.2% power reduction (IEEE TCAD 2026).
+  - CNTFET-based ternary full adder — 76/55 CNTFET complete/partial adders with
+    ~24% delay improvement (IEEE TCAD 2025).
+  - Energy-optimized ternary full adder using capacitive threshold logic and
+    CNTFETs for DSP (AEU 2026).
+  - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
+    7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
+
+---
+
 ## 2026-07-23 — Wave Loop 764 (module-scope `[347][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
 
 ### What worked
diff --git a/.trinity/seals/scratch_w766_bench_module_351x2p6_aos_var_call_write.json b/.trinity/seals/scratch_w766_bench_module_351x2p6_aos_var_call_write.json
@@ -0,0 +1,11 @@
+{
+  "gen_hash_c": "sha256:bfe7bc95931823b883a3c8edbe65fb23ca5ebc200731b697628d51b04765b140",
+  "gen_hash_rust": "sha256:9f3d730eda5fb82ff5499b6f43cd965bc2661c015b7d94d8ce324f61d2321444",
+  "gen_hash_verilog": "sha256:a392cffc872b8c42e9b5207e6edb2e8cc6461c154b0b22070b91ccc885d8e463",
+  "gen_hash_zig": "sha256:9a525b5462011d62abd9c6fb0c4e15b459e0a0a910d9fc2e04b80fb0d43f0003",
+  "module": "w766_bench_module_351x2p6_aos_var_call_write",
+  "ring": 12,
+  "sealed_at": "2026-07-23T17:25:48Z",
+  "spec_hash": "sha256:25fb588ab39e321ee5e315dd7e0e4882ab4cd2d25cfc74617b7ea7d7fd598570",
+  "spec_path": "specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27"
+}
diff --git a/bootstrap/tests/icarus_lowerable.rs b/bootstrap/tests/icarus_lowerable.rs
@@ -4081,6 +4081,24 @@ fn accepts_w765_bench_module_349x2p6_aos_var_call_write() {
     }
 }
 
+#[test]
+fn accepts_w766_bench_module_351x2p6_aos_var_call_write() {
+    let dir = scratch_dir();
+    for name in &[
+        "w766_bench_module_351x2p6_aos_var_call_write.t27",
+    ] {
+        let p = dir.join(name);
+        assert!(p.exists(), "missing W766 witness {}", p.display());
+        let (lowerable, json) = run_icarus_lowerable(&p);
+        assert!(
+            lowerable,
+            "expected {} to be lowerable, got: {}",
+            p.display(),
+            json
+        );
+    }
+}
+
 #[test]
 fn accepts_known_lowerable_witnesses() {
     let dir = scratch_dir();
diff --git a/docs/NOW.md b/docs/NOW.md
@@ -1,28 +1,28 @@
-# NOW — Wave Loop 765 close-out / Wave Loop 766 setup (2026-07-23)
+# NOW — Wave Loop 766 close-out / Wave Loop 767 setup (2026-07-23)
 
 Last updated: 2026-07-23
 
-## Wave Loop 765 — module-scope `[349][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1736)
+## Wave Loop 766 — module-scope `[351][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1737)
 
-- Branch: `wave-loop-765`
-- Issue: #1736
+- Branch: `wave-loop-766`
+- Issue: #1737
 - PR: to open
-- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md`
-- Plan: `.claude/plans/wave-loop-765.md`
-- Cooperation W766: `.claude/plans/wave-loop-766.md`
+- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md`
+- Plan: `.claude/plans/wave-loop-766.md`
+- Cooperation W767: `.claude/plans/wave-loop-767.md`
 
 ### What landed
-- `specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27`
-  - 22,336 elements, 714,752-bit packed vector (~0.682 MiBit).
-  - Module-scope `pub var dst : [349][2]^6 Pt` initialized from a function call and
+- `specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27`
+  - 22,464 elements, 718,848-bit packed vector (~0.686 MiBit).
+  - Module-scope `pub var dst : [351][2]^6 Pt` initialized from a function call and
     exercised with indexed signed field writes.
   - `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
-- `scripts/gen_w765.py`
-  - Generator for the W765 witness; `OUTER = 349`, `MID_IDX = 174`.
+- `scripts/gen_w766.py`
+  - Generator for the W766 witness; `OUTER = 351`, `MID_IDX = 175`.
 - `bootstrap/tests/icarus_lowerable.rs`
-  - Added `accepts_w765_bench_module_349x2p6_aos_var_call_write`.
-- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-766.md`
-  - W765 learnings saved and W766 issue/plan created.
+  - Added `accepts_w766_bench_module_351x2p6_aos_var_call_write`.
+- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-767.md`
+  - W766 learnings saved and W767 issue/plan created.
 
 ### Not changed
 - `bootstrap/src/compiler.rs` — zero compiler changes.
@@ -33,8 +33,21 @@ Last updated: 2026-07-23
 - `cargo build --release -p t27c`: OK.
 - `cargo test -p t27c --bin t27c`: 1494/0/2.
 - `cargo test -p tri`: 78/0.
-- `cargo test -p t27c --test icarus_lowerable`: 225/0.
-- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W765: PASS.
+- `cargo test -p t27c --test icarus_lowerable`: 226/0.
+- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W766: PASS.
+
+---
+
+## Wave Loop 767 — next odd outer-dimension `[353][2]^6 Pt` (Issue #1738)
+
+- Branch: `wave-loop-767` (to create after W766 merge)
+- Issue: #1738
+- Plan: `.claude/plans/wave-loop-767.md`
+
+### Candidate variants
+- Variant A (recommended): continue the odd outer-dimension ladder with `[353][2]^6 Pt`.
+- Variant B: keep width at ~0.686 MiBit but move the packed var to bench/function scope.
+- Variant C: add `if`-guarded indexed signed field writes at the current width.
 
 ---
 
diff --git a/docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md b/docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md
diff --git a/scripts/gen_w766.py b/scripts/gen_w766.py
diff --git a/specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27 b/specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27
