feat(igla): Wave Loop 765 — module-scope [349][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1736) (#1473)

gHashTag · web-flow · commit 3ba30eff4997 · 2026-07-24T00:18:26.000+07:00
Closes #1736. 🤖 Generated with [Claude Code](https://claude.com/claude-code)
diff --git a/.claude/plans/wave-loop-766.md b/.claude/plans/wave-loop-766.md
@@ -0,0 +1,48 @@
+# Wave Loop 766 Plan — Issue #1737
+
+## Phase 1: Issue
+- Confirm W766 issue #1737 and branch `wave-loop-766`.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w766.py` derived from `scripts/gen_w765.py`.
+- Constants: `OUTER = 351`, `TOTAL = 22464`, `LAST_IDX = 350`, `MID_IDX = 175`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+
+## Phase 4: Impl
+- Add integration test `accepts_w766_bench_module_351x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs`.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./bootstrap/target/release/t27c seal --save specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./bootstrap/target/release/t27c parse ...`
+- `./bootstrap/target/release/t27c icarus-lowerable ...`
+- `./bootstrap/target/release/t27c icarus-simulate ...` (17 cycles)
+- `./bootstrap/target/release/t27c icarus-cocotb ...`
+- `cargo test -p t27c --bin t27c`
+- `cargo test -p tri`
+- `cargo test -p t27c --test icarus_lowerable`
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 766 — module-scope [351][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1737)`.
+- Push `wave-loop-766`, open PR, merge to `master`, create `wave-loop-767`.
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `skills-wave-loop-recipe.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[353][2]^6 Pt` (~0.690 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the same width.
+- **C:** add conditional (`if`) indexed writes at the current width.
diff --git a/.trinity/current-issue.md b/.trinity/current-issue.md
@@ -1,45 +1,45 @@
-# Wave Loop 765 — Issue #1736
+# Wave Loop 766 — Issue #1737
 
-**Branch:** `wave-loop-765`  
+**Branch:** `wave-loop-766`  
 **Date:** 2026-07-23  
 **Cooperation variant:** A (recommended)
 
 ## Goal
 
-Close Wave Loop 765 by validating a module-scope `[349][2]^6 Pt` packed
+Close Wave Loop 766 by validating a module-scope `[351][2]^6 Pt` packed
 array-of-struct variable initialized from a function call, with indexed signed
 field writes and `assert_eq` read-back in a `bench` block.
 
 ## Acceptance criteria
 
-1. `specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27` is generated and parses.
+1. `specs/scratch/w766_bench_module_351x2p6_aos_var_call_write.t27` is generated and parses.
 2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
 3. The cocotb reference model matches the t27 semantics.
 4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
 5. All cargo suites remain green.
-6. Integration test `accepts_w765_bench_module_349x2p6_aos_var_call_write` is added.
-7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md` is written.
+6. Integration test `accepts_w766_bench_module_351x2p6_aos_var_call_write` is added.
+7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W766_2026-07-23.md` is written.
 8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
-9. Branch merges to `master` with `Closes #1736`.
+9. Branch merges to `master` with `Closes #1737`.
 
 ## Technical notes
 
-- Shape: `[349][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `349 × 64 = 22,336`.
-- Packed vector width: `22,336 × 32 = 714,752` bits (~0.682 MiBit).
-- `MID_IDX = 174`; frame-condition element `[174][1][0][0][0][0][0]` is element
-  `174*64 + 32 = 11,168`.
-- Generator script: `scripts/gen_w765.py` (copy from `scripts/gen_w764.py`, set
-  `OUTER = 349` and `MID_IDX = 174`, manually fix the f-string header).
+- Shape: `[351][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
+- Total elements: `351 × 64 = 22,464`.
+- Packed vector width: `22,464 × 32 = 718,848` bits (~0.686 MiBit).
+- `MID_IDX = 175`; frame-condition element `[175][1][0][0][0][0][0]` is element
+  `175*64 + 32 = 11,232`.
+- Generator script: `scripts/gen_w766.py` (copy from `scripts/gen_w765.py`, set
+  `OUTER = 351` and `MID_IDX = 175`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
 - Include `make_grid(32768)` period-identity check because `32768 ≡ 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
 
-- **Variant A (recommended):** continue the odd outer-dimension ladder with `[351][2]^6 Pt`.
-- **Variant B:** keep width at ~0.682 MiBit but move the packed var to bench/function scope.
+- **Variant A (recommended):** continue the odd outer-dimension ladder with `[353][2]^6 Pt`.
+- **Variant B:** keep width at ~0.686 MiBit but move the packed var to bench/function scope.
 - **Variant C:** add `if`-guarded indexed signed field writes at the current width.
 
 ---
diff --git a/.trinity/current_task/activity.md b/.trinity/current_task/activity.md
@@ -3668,3 +3668,7 @@
 - **Commit:** chore(trinity): record final W763 session log and commit count
 - **Files:** .claude/plans/wave-loop-763.md,.claude/plans/wave-loop-764.md,.trinity/current-issue.md,.trinity/current_task/.commit_count,.trinity/current_task/activity.md,.trinity/current_task/session_log.jsonl,.trinity/experience.md,.trinity/icarus-baselines/specs/scratch/w763_bench_module_345x2p6_aos_var_call_write.t27.baseline,.trinity/seals/scratch_w763_bench_module_345x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/reports/FPGA_LOOP_CLOSEOUT_W763_2026-07-23.md,scripts/gen_w763.py,specs/scratch/w763_bench_module_345x2p6_aos_var_call_write.t27
 
+## 2026-07-23T17:15:15Z — wave-loop-765
+- **Commit:** feat(igla): Wave Loop 764 — module-scope [347][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes
+- **Files:** .claude/plans/wave-loop-766.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w765_bench_module_349x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md,scripts/gen_w765.py,specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27
+
diff --git a/.trinity/experience.md b/.trinity/experience.md
@@ -1,3 +1,80 @@
+## 2026-07-23 — Wave Loop 765 (module-scope `[349][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
+
+### What worked
+- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 349.
+  The `[349][2]^6 Pt` witness is 714,752 bits (~0.682 MiBit), still well under the 4-MiBit
+  cliff, and required no compiler changes.
+- A module-level `pub var dst : [349][2]^6 Pt` can be initialized from a function
+  call and exercised with indexed signed field writes, with zero compiler changes.
+- The cocotb/Python reference model correctly mirrored the row-major flattening
+  with outer stride 349, confirming the layout is preserved end-to-end.
+- Reused the corrected W632 element-index formula for mid-row expected values:
+  `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
+- For `OUTER = 349`, `MID_IDX = 174`; the frame-condition element is
+  `[174][1][0][0][0][0][0]`, element number `174*64 + 32 = 11,168`.
+- Updated weak-point audit: 48 commits in 30 days (39 with `Closes #N`), 51
+  `.t27` specs without `test`/`invariant`/`bench`, 23 `scripts/*.sh` under `scripts/`.
+
+### What changed behavior
+- No changes to `bootstrap/src/compiler.rs`.
+- No changes to `bootstrap/stage0/FROZEN_HASH`.
+- No changes to `scripts/cocotb_ref_model.py`.
+- Added `specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27` (~1,528 KB /
+  ~66,371 lines) with seal and Icarus baseline.
+- Added integration test `accepts_w765_bench_module_349x2p6_aos_var_call_write`.
+- Added generator script `scripts/gen_w765.py`.
+
+### Validation
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
+- `cargo test -p tri`: 78 passed; 0 failed.
+- `cargo test -p t27c --test icarus_lowerable`: 225 passed; 0 failed.
+- Direct `t27c parse` W765: PASS.
+- Direct `t27c icarus-lowerable` W765: PASS (`lowerable`).
+- Direct `t27c icarus-simulate` W765: PASS (17 cycles, PASSED).
+- Direct `t27c icarus-cocotb` W765: PASS (`reference-model OK`).
+
+### Scientific / engineering background
+- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
+  packed dimensions, with no power-of-two restriction. Variant A emits a single
+  714,752-bit packed vector, which is legal SystemVerilog.
+- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
+  flattening nested arrays to wide packed vectors is a well-founded compiler
+  discipline, even when outer dimensions are non-power-of-two.
+- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
+  structs; t27 scalar flattening avoids that construct entirely.
+- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
+  unsupported in the native frontend; t27 packed-vector lowering avoids the
+  gap.
+- 2025-2026 ternary/MVL literature scan found:
+  - 5500FP / GargantuRAM — 24-trit balanced ternary RISC processor on Efinix
+    Trion FPGA at 20 MHz, 120-instruction ISA, real ±3.3 V ternary I/O,
+    CERN-OHL-P v2 board, commercially available (Zenodo/GitHub/Hackaday 2026).
+  - Trinity B002 / Trinity v2.0.x — zero-DSP ternary-weight autoregressive LLM
+    inference on Xilinx Artix-7 via OpenXC7, ~63 tok/s @ ~1 W, QMTech XC7A100T
+    (Zenodo 2025/2026).
+  - TernaryCore — open-source native {-1,0,+1} Verilog BitNet b1.58 accelerator,
+    zero DSP, 31/31 simulations passing, Artix-7 roadmap (GitHub 2026).
+  - ternfpga — end-to-end ternary LLM decode engine on Xilinx Arty A7-35T, 0 DSP,
+    ~1.62 J/token vs. 3.67 J/token on RTX 3060 (GitHub 2026).
+  - VitaLLM — versatile ternary/mixed-precision LLM accelerator in TSMC 16 nm,
+    ~70–72 tok/s decode, <1 s prefill, 0.214–0.223 mm², ~60–66 mW
+    (arXiv 2026).
+  - KU Leuven MICAS ternary-lut-dse — LUT-based ternary MatMul DSE for 1.58-bit
+    LLM inference, accepted at IEEE ISPASS 2026 (GitHub 2026).
+  - BitNet b1.58 2B4T Technical Report — Microsoft native 1.58-bit LLM
+    (arXiv 2025).
+  - Bitnet.cpp — Microsoft CPU inference for ternary LLMs, up to 6.25× speedup
+    over FP16 (ACL 2025).
+  - Unbalanced ternary full adder in CNTFET — 42-transistor design with 35.8–75.2%
+    power reduction (IEEE TCAD 2026).
+  - CNTFET-based ternary full adder — 76/55 CNTFET complete/partial adders with
+    ~24% delay improvement (IEEE TCAD 2025).
+  - Energy-optimized ternary full adder using capacitive threshold logic and
+    CNTFETs for DSP (AEU 2026).
+  - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
+    7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
+
 ## 2026-07-23 — Wave Loop 764 (module-scope `[347][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
 
 ### What worked
diff --git a/.trinity/seals/scratch_w765_bench_module_349x2p6_aos_var_call_write.json b/.trinity/seals/scratch_w765_bench_module_349x2p6_aos_var_call_write.json
@@ -0,0 +1,11 @@
+{
+  "gen_hash_c": "sha256:ad8a471cec2ae535aefe85183e570384f86aecb7592355bcc2449ec4a2bac96b",
+  "gen_hash_rust": "sha256:03f82c911fc18fa0278f043262a0617f7a01fbe3956a94e2568b89d3e94a59e7",
+  "gen_hash_verilog": "sha256:fd9116550ecb5baf92f58ffcd56f415473abaf0f3a9918d972ac4132b57b6033",
+  "gen_hash_zig": "sha256:535b4975dc33e5816f2cd1dd045c6e2fa9ac989ecee833b350ce46047198f356",
+  "module": "w765_bench_module_349x2p6_aos_var_call_write",
+  "ring": 12,
+  "sealed_at": "2026-07-23T17:10:17Z",
+  "spec_hash": "sha256:bc4f3b35c56f8f98aa6d745ebdb1845c33a0b40a41c9c6a30032b366d1b4df89",
+  "spec_path": "specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27"
+}
diff --git a/bootstrap/tests/icarus_lowerable.rs b/bootstrap/tests/icarus_lowerable.rs
@@ -4063,6 +4063,24 @@ fn accepts_w764_bench_module_347x2p6_aos_var_call_write() {
     }
 }
 
+#[test]
+fn accepts_w765_bench_module_349x2p6_aos_var_call_write() {
+    let dir = scratch_dir();
+    for name in &[
+        "w765_bench_module_349x2p6_aos_var_call_write.t27",
+    ] {
+        let p = dir.join(name);
+        assert!(p.exists(), "missing W765 witness {}", p.display());
+        let (lowerable, json) = run_icarus_lowerable(&p);
+        assert!(
+            lowerable,
+            "expected {} to be lowerable, got: {}",
+            p.display(),
+            json
+        );
+    }
+}
+
 #[test]
 fn accepts_known_lowerable_witnesses() {
     let dir = scratch_dir();
diff --git a/docs/NOW.md b/docs/NOW.md
@@ -1,28 +1,28 @@
-# NOW — Wave Loop 764 close-out / Wave Loop 765 setup (2026-07-23)
+# NOW — Wave Loop 765 close-out / Wave Loop 766 setup (2026-07-23)
 
 Last updated: 2026-07-23
 
-## Wave Loop 764 — module-scope `[347][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1735)
+## Wave Loop 765 — module-scope `[349][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1736)
 
-- Branch: `wave-loop-764`
-- Issue: #1735
+- Branch: `wave-loop-765`
+- Issue: #1736
 - PR: to open
-- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W764_2026-07-23.md`
-- Plan: `.claude/plans/wave-loop-764.md`
-- Cooperation W765: `.claude/plans/wave-loop-765.md`
+- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md`
+- Plan: `.claude/plans/wave-loop-765.md`
+- Cooperation W766: `.claude/plans/wave-loop-766.md`
 
 ### What landed
-- `specs/scratch/w764_bench_module_347x2p6_aos_var_call_write.t27`
-  - 22,208 elements, 710,656-bit packed vector (~0.678 MiBit).
-  - Module-scope `pub var dst : [347][2]^6 Pt` initialized from a function call and
+- `specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27`
+  - 22,336 elements, 714,752-bit packed vector (~0.682 MiBit).
+  - Module-scope `pub var dst : [349][2]^6 Pt` initialized from a function call and
     exercised with indexed signed field writes.
   - `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
-- `scripts/gen_w764.py`
-  - Generator for the W764 witness; `OUTER = 347`, `MID_IDX = 173`.
+- `scripts/gen_w765.py`
+  - Generator for the W765 witness; `OUTER = 349`, `MID_IDX = 174`.
 - `bootstrap/tests/icarus_lowerable.rs`
-  - Added `accepts_w764_bench_module_347x2p6_aos_var_call_write`.
-- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-765.md`
-  - W764 learnings saved and W765 issue/plan created.
+  - Added `accepts_w765_bench_module_349x2p6_aos_var_call_write`.
+- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-766.md`
+  - W765 learnings saved and W766 issue/plan created.
 
 ### Not changed
 - `bootstrap/src/compiler.rs` — zero compiler changes.
@@ -33,8 +33,21 @@ Last updated: 2026-07-23
 - `cargo build --release -p t27c`: OK.
 - `cargo test -p t27c --bin t27c`: 1494/0/2.
 - `cargo test -p tri`: 78/0.
-- `cargo test -p t27c --test icarus_lowerable`: 224/0.
-- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W764: PASS.
+- `cargo test -p t27c --test icarus_lowerable`: 225/0.
+- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W765: PASS.
+
+---
+
+## Wave Loop 766 — next odd outer-dimension `[351][2]^6 Pt` (Issue #1737)
+
+- Branch: `wave-loop-766` (to create after W765 merge)
+- Issue: #1737
+- Plan: `.claude/plans/wave-loop-766.md`
+
+### Candidate variants
+- Variant A (recommended): continue the odd outer-dimension ladder with `[351][2]^6 Pt`.
+- Variant B: keep width at ~0.682 MiBit but move the packed var to bench/function scope.
+- Variant C: add `if`-guarded indexed signed field writes at the current width.
 
 ---
 
diff --git a/docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md b/docs/reports/FPGA_LOOP_CLOSEOUT_W765_2026-07-23.md
diff --git a/scripts/gen_w765.py b/scripts/gen_w765.py
diff --git a/specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27 b/specs/scratch/w765_bench_module_349x2p6_aos_var_call_write.t27
