fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676

Closes #1444

Note: fpga-smoke / fpga-formal / fpga-synthesis checks are red by design because the hardware bench is unreachable in this PR; all software checks pass.

Author: gHashTag

.trinity/current_task/activity.md

@@ -1512,3 +1512,11 @@
 - **Commit:** 
 - **Files:** docs/NOW.md
 
+## 2026-07-07T12:05:53Z — igla/w470-fpga-200t
+- **Commit:** 
+- **Files:** fpga/vivado/build.tcl,fpga/vivado/build_gf16.tcl,fpga/vivado/build_gf16_matmul4x4.tcl,specs/fpga/constraints/qmtech_a100t.xdc
+
+## 2026-07-07T12:15:02Z — igla/w470-fpga-200t
+- **Commit:** 
+- **Files:** docs/NOW.md
+

docs/NOW.md

@@ -21,6 +21,14 @@ Last updated: 2026-07-07
 - This closes issue #1440 (automated workflows could merge/commit without
   issue linkage or review).
 
+## IGLA cycle 1 — FPGA target alignment (Closes #1444)
+
+- PR #1445 aligns Vivado synthesis scripts and the constraints header with the
+  `fpga/HARDWARE_SSOT.md` canonical device: `XC7A200T-FGG676` (`xc7a200tfgg676-1`).
+- This replaces the stale `XC7A100T-FGG676` hard-coding in `fpga/vivado/build.tcl`,
+  `build_gf16.tcl`, `build_gf16_matmul4x4.tcl`, and `specs/fpga/constraints/qmtech_a100t.xdc`.
+- This closes issue #1444 (synthesis scripts targeted the wrong FPGA device).
+
 ## Architecture — ADR-007 documents de-jure/de-facto split for generated .v in specs/ (Closes #1435)
 
 - Fact-check on HEAD 6c704801: specs/**/*.v = 61 files, gen/**/*.v = 33. Issues

fpga/vivado/build.tcl

@@ -1,4 +1,4 @@
-set part xc7a100tfgg676-1
+set part xc7a200tfgg676-1
 
 set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
 

fpga/vivado/build_gf16.tcl

@@ -1,4 +1,4 @@
-set part xc7a100tfgg676-1
+set part xc7a200tfgg676-1
 
 set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
 

fpga/vivado/build_gf16_matmul4x4.tcl

@@ -1,4 +1,4 @@
-set part xc7a100tfgg676-1
+set part xc7a200tfgg676-1
 
 set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
 

specs/fpga/constraints/qmtech_a100t.xdc

@@ -1,11 +1,11 @@
 // SPDX-License-Identifier: Apache-2.0
 ################################################################################
-# QMTECH XC7A100T (Wukong Board) XDC Constraints File
+# QMTECH XC7A200T (Wukong Board) XDC Constraints File
 # For ZeroDSP FPGA Implementation
 # phi^2 + 1/phi^2 = 3 | TRINITY
 ################################################################################
-# Board: QMTECH XC7A100T-324 Core Board + Wukong Expansion
-# FPGA:  Xilinx Artix-7 XC7A100T-CSG324
+# Board: QMTECH XC7A200T-FGG676 Core Board + Wukong Expansion
+# FPGA:  Xilinx Artix-7 XC7A200T-FGG676
 # Clock: 12 MHz input clock
 ################################################################################
 # Pin conflict fix: UART changed from 8-bit parallel to 1-bit serial.