|
70 | 70 |
|
71 | 71 | - name: Upload generated Verilog |
72 | 72 | if: always() |
73 | | - uses: actions/upload-artifact@v4 |
| 73 | + uses: actions/upload-artifact@v7 |
74 | 74 | with: |
75 | 75 | name: fpga-verilog |
76 | 76 | path: build/fpga/generated/ |
@@ -237,7 +237,7 @@ jobs: |
237 | 237 |
|
238 | 238 | - name: Upload synthesis output |
239 | 239 | if: always() |
240 | | - uses: actions/upload-artifact@v4 |
| 240 | + uses: actions/upload-artifact@v7 |
241 | 241 | with: |
242 | 242 | name: fpga-synthesis |
243 | 243 | path: | |
@@ -364,7 +364,7 @@ jobs: |
364 | 364 | ls -la build/fpga/ |
365 | 365 | |
366 | 366 | - name: Upload bitstream artifact |
367 | | - uses: actions/upload-artifact@v4 |
| 367 | + uses: actions/upload-artifact@v7 |
368 | 368 | with: |
369 | 369 | name: fpga-bitstream-${{ github.sha }} |
370 | 370 | path: build/fpga/bitstream.bit |
@@ -398,7 +398,7 @@ jobs: |
398 | 398 | sed -i 's/^ //' build/fpga/FLASHING.md |
399 | 399 |
|
400 | 400 | - name: Upload bitstream + flashing guide |
401 | | - uses: actions/upload-artifact@v4 |
| 401 | + uses: actions/upload-artifact@v7 |
402 | 402 | with: |
403 | 403 | name: fpga-bitstream-${{ github.sha }} |
404 | 404 | path: | |
@@ -470,7 +470,7 @@ jobs: |
470 | 470 |
|
471 | 471 | - name: Upload formal results |
472 | 472 | if: always() |
473 | | - uses: actions/upload-artifact@v4 |
| 473 | + uses: actions/upload-artifact@v7 |
474 | 474 | with: |
475 | 475 | name: fpga-formal |
476 | 476 | path: build/fpga/formal/ |
@@ -595,7 +595,7 @@ jobs: |
595 | 595 |
|
596 | 596 | - name: Upload conformance results |
597 | 597 | if: always() |
598 | | - uses: actions/upload-artifact@v4 |
| 598 | + uses: actions/upload-artifact@v7 |
599 | 599 | with: |
600 | 600 | name: fpga-conformance |
601 | 601 | path: build/fpga/conformance/ |
|
0 commit comments