fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676

- Flip fpga/vivado/build*.tcl from xc7a100tfgg676-1 to xc7a200tfgg676-1.
- Correct target board/FPGA comments in specs/fpga/constraints/qmtech_a100t.xdc.

Closes #1444

Author: Dmitrii Vasilev

.trinity/current_task/activity.md

@@ -1512,3 +1512,7 @@
 - **Commit:** 
 - **Files:** docs/NOW.md
 
+## 2026-07-07T12:05:53Z — igla/w470-fpga-200t
+- **Commit:** 
+- **Files:** fpga/vivado/build.tcl,fpga/vivado/build_gf16.tcl,fpga/vivado/build_gf16_matmul4x4.tcl,specs/fpga/constraints/qmtech_a100t.xdc
+

fpga/vivado/build.tcl

@@ -1,4 +1,4 @@
-set part xc7a100tfgg676-1
+set part xc7a200tfgg676-1
 
 set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
 

fpga/vivado/build_gf16.tcl

@@ -1,4 +1,4 @@
-set part xc7a100tfgg676-1
+set part xc7a200tfgg676-1
 
 set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
 

fpga/vivado/build_gf16_matmul4x4.tcl

@@ -1,4 +1,4 @@
-set part xc7a100tfgg676-1
+set part xc7a200tfgg676-1
 
 set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
 

specs/fpga/constraints/qmtech_a100t.xdc

@@ -1,11 +1,11 @@
 // SPDX-License-Identifier: Apache-2.0
 ################################################################################
-# QMTECH XC7A100T (Wukong Board) XDC Constraints File
+# QMTECH XC7A200T (Wukong Board) XDC Constraints File
 # For ZeroDSP FPGA Implementation
 # phi^2 + 1/phi^2 = 3 | TRINITY
 ################################################################################
-# Board: QMTECH XC7A100T-324 Core Board + Wukong Expansion
-# FPGA:  Xilinx Artix-7 XC7A100T-CSG324
+# Board: QMTECH XC7A200T-FGG676 Core Board + Wukong Expansion
+# FPGA:  Xilinx Artix-7 XC7A200T-FGG676
 # Clock: 12 MHz input clock
 ################################################################################
 # Pin conflict fix: UART changed from 8-bit parallel to 1-bit serial.