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| 1 | +## 2026-07-23 — Wave Loop 763 (module-scope `[345][2]^6 Pt` non-power-of-two outer-dimension AoS variable) |
| 2 | + |
| 3 | +### What worked |
| 4 | +- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 345. |
| 5 | + The `[345][2]^6 Pt` witness is 706,560 bits (~0.674 MiBit), still well under the 4-MiBit |
| 6 | + cliff, and required no compiler changes. |
| 7 | +- A module-level `pub var dst : [345][2]^6 Pt` can be initialized from a function |
| 8 | + call and exercised with indexed signed field writes, with zero compiler changes. |
| 9 | +- The cocotb/Python reference model correctly mirrored the row-major flattening |
| 10 | + with outer stride 345, confirming the layout is preserved end-to-end. |
| 11 | +- Reused the corrected W632 element-index formula for mid-row expected values: |
| 12 | + `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`. |
| 13 | +- For `OUTER = 345`, `MID_IDX = 172`; the frame-condition element is |
| 14 | + `[172][1][0][0][0][0][0]`, element number `172*64 + 32 = 11,040`. |
| 15 | +- Updated weak-point audit: 575 commits in 30 days (28 with `Closes #N`), 57 |
| 16 | + `.t27` specs without `test`/`invariant`/`bench`, 23 `scripts/*.sh` under `scripts/`. |
| 17 | + |
| 18 | +### What changed behavior |
| 19 | +- No changes to `bootstrap/src/compiler.rs`. |
| 20 | +- No changes to `bootstrap/stage0/FROZEN_HASH`. |
| 21 | +- No changes to `scripts/cocotb_ref_model.py`. |
| 22 | +- Added `specs/scratch/w763_bench_module_345x2p6_aos_var_call_write.t27` (~1,510 KB / |
| 23 | + ~65,611 lines) with seal and Icarus baseline. |
| 24 | +- Added integration test `accepts_w763_bench_module_345x2p6_aos_var_call_write`. |
| 25 | +- Added generator script `scripts/gen_w763.py`. |
| 26 | + |
| 27 | +### Validation |
| 28 | +- `cargo build --release -p t27c`: OK. |
| 29 | +- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored. |
| 30 | +- `cargo test -p tri`: 78 passed; 0 failed. |
| 31 | +- `cargo test -p t27c --test icarus_lowerable`: 223 passed; 0 failed. |
| 32 | +- Direct `t27c parse` W763: PASS. |
| 33 | +- Direct `t27c icarus-lowerable` W763: PASS (`lowerable`). |
| 34 | +- Direct `t27c icarus-simulate` W763: PASS (17 cycles, PASSED). |
| 35 | +- Direct `t27c icarus-cocotb` W763: PASS (`reference-model OK`). |
| 36 | + |
| 37 | +### Scientific / engineering background |
| 38 | +- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of |
| 39 | + packed dimensions, with no power-of-two restriction. Variant A emits a single |
| 40 | + 706,560-bit packed vector, which is legal SystemVerilog. |
| 41 | +- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that |
| 42 | + flattening nested arrays to wide packed vectors is a well-founded compiler |
| 43 | + discipline, even when outer dimensions are non-power-of-two. |
| 44 | +- Icarus issue #1134 documents assertion failures for unpacked arrays of packed |
| 45 | + structs; t27 scalar flattening avoids that construct entirely. |
| 46 | +- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain |
| 47 | + unsupported in the native frontend; t27 packed-vector lowering avoids the |
| 48 | + gap. |
| 49 | +- 2025-2026 ternary/MVL literature scan found: |
| 50 | + - Trinity B002 / Trinity v2.0.x — zero-DSP ternary-weight autoregressive LLM |
| 51 | + inference on Xilinx Artix-7 via OpenXC7, ~63 tok/s @ ~1 W, QMTech XC7A100T |
| 52 | + (Zenodo 2025/2026). |
| 53 | + - TerEffic — highly efficient ternary LLM inference on AMD Alveo U280, 16,300 |
| 54 | + tok/s on 370 M model, 455 tok/s/W (arXiv 2025). |
| 55 | + - TeLLMe v2 — end-to-end ternary LLM prefill/decode accelerator on AMD Kria |
| 56 | + KV260, up to 25 tok/s decode / 143 tok/s prefill under 5 W (arXiv 2025). |
| 57 | + - 5500FP / GargantuRAM — 24-trit balanced ternary RISC processor on Efinix |
| 58 | + Trion FPGA at 20 MHz, real ±3.3 V ternary I/O, CERN-OHL-P v2 board, |
| 59 | + commercially available (Zenodo/GitHub/Hackaday 2026). |
| 60 | + - TernaryCore — open-source native {-1,0,+1} Verilog BitNet b1.58 accelerator, |
| 61 | + zero DSP, 31/31 simulations passing, Artix-7 roadmap (GitHub 2026). |
| 62 | + - Unbalanced ternary full adder in CNTFET — 42-transistor design with 35.8–75.2% |
| 63 | + power reduction (IEEE TCAD 2026). |
| 64 | + - CNTFET-based ternary full adder — 76/55 CNTFET complete/partial adders with |
| 65 | + ~24% delay improvement (IEEE TCAD 2025). |
| 66 | + - Energy-optimized ternary full adder using capacitive threshold logic and |
| 67 | + CNTFETs for DSP (AEU 2026). |
| 68 | + - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx |
| 69 | + 7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado. |
| 70 | + |
1 | 71 | ## 2026-07-23 — Wave Loop 762 (module-scope `[343][2]^6 Pt` non-power-of-two outer-dimension AoS variable) |
2 | 72 |
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3 | 73 | ### What worked |
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