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Wave Loop 768 — [355][2]^6 Pt AoS var from call with indexed signed writes
Closes #1739
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‎.claude/plans/wave-loop-769.md‎

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# Wave Loop 769 Plan — Issue #1740
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## Phase 1: Issue
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- Confirm W769 issue #1740 and branch `wave-loop-769`.
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## Phase 2: Spec
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- Generate `specs/scratch/w769_bench_module_357x2p6_aos_var_call_write.t27` using
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`scripts/gen_w769.py` derived from `scripts/gen_w768.py`.
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- Constants: `OUTER = 357`, `TOTAL = 22848`, `LAST_IDX = 356`, `MID_IDX = 178`.
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## Phase 3: TDD
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- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
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`call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
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## Phase 4: Impl
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- Add integration test `accepts_w769_bench_module_357x2p6_aos_var_call_write` to
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`bootstrap/tests/icarus_lowerable.rs`.
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## Phase 5: Gen
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- Run `cd bootstrap && cargo build --release -p t27c`.
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## Phase 6: Seal
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- Run `./bootstrap/target/release/t27c seal --save specs/scratch/w769_bench_module_357x2p6_aos_var_call_write.t27`.
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- Confirm FROZEN_HASH unchanged.
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## Phase 7: Verify
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- `./bootstrap/target/release/t27c parse ...`
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- `./bootstrap/target/release/t27c icarus-lowerable ...`
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- `./bootstrap/target/release/t27c icarus-simulate ...` (17 cycles)
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- `./bootstrap/target/release/t27c icarus-cocotb ...`
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- `cargo test -p t27c --bin t27c`
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- `cargo test -p tri`
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- `cargo test -p t27c --test icarus_lowerable`
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## Phase 8: Land
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- Commit with `feat(igla): Wave Loop 769 — module-scope [357][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1740)`.
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- Push `wave-loop-769`, open PR, merge to `master`, create `wave-loop-770`.
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## Phase 9: Learn
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- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W769_2026-07-23.md`.
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- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
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`skills-wave-loop-recipe.md`.
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## Cooperation variants for next Wave Loop
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- **A (recommended):** `[359][2]^6 Pt` (~0.702 MiBit), continuing the odd ladder.
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- **B:** move the packed variable to bench/function scope at the same width.
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- **C:** add conditional (`if`) indexed writes at the current width.

‎.trinity/current-issue.md‎

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# Wave Loop 767 — Issue #1738
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# Wave Loop 768 — Issue #1739
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**Branch:** `wave-loop-767`
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**Branch:** `wave-loop-768`
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**Date:** 2026-07-23
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**Cooperation variant:** A (recommended)
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## Goal
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Close Wave Loop 767 by validating a module-scope `[353][2]^6 Pt` packed
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Close Wave Loop 768 by validating a module-scope `[355][2]^6 Pt` packed
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array-of-struct variable initialized from a function call, with indexed signed
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field writes and `assert_eq` read-back in a `bench` block.
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## Acceptance criteria
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1. `specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27` is generated and parses.
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1. `specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27` is generated and parses.
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2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
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3. The cocotb reference model matches the t27 semantics.
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4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
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5. All cargo suites remain green.
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6. Integration test `accepts_w767_bench_module_353x2p6_aos_var_call_write` is added.
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7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md` is written.
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6. Integration test `accepts_w768_bench_module_355x2p6_aos_var_call_write` is added.
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7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W768_2026-07-23.md` is written.
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8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
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9. Branch merges to `master` with `Closes #1738`.
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9. Branch merges to `master` with `Closes #1739`.
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## Technical notes
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- Shape: `[353][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
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- Total elements: `353 x 64 = 22,592`.
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- Packed vector width: `22,592 x 32 = 722,944` bits (~0.690 MiBit).
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- `MID_IDX = 176`; frame-condition element `[176][1][0][0][0][0][0]` is element
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`176*64 + 32 = 11,296`.
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- Generator script: `scripts/gen_w767.py` (copy from `scripts/gen_w766.py`, set
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`OUTER = 353` and `MID_IDX = 176`, manually fix the f-string header).
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- Shape: `[355][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
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- Total elements: `355 x 64 = 22,720`.
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- Packed vector width: `22,720 x 32 = 727,040` bits (~0.694 MiBit).
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- `MID_IDX = 177`; frame-condition element `[177][1][0][0][0][0][0]` is element
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`177*64 + 32 = 11,360`.
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- Generator script: `scripts/gen_w768.py` (copy from `scripts/gen_w767.py`, set
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`OUTER = 355` and `MID_IDX = 177`, manually fix the f-string header).
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- Use `assert_eq` checks on changed elements (Icarus simulation path does not
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emit `assert_ne`).
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- Include `make_grid(32768)` period-identity check because `32768 == 0 (mod 32768)`.
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- Zero compiler / reference-model / FROZEN_HASH changes expected.
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## Cooperation variants for next Wave Loop
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- **Variant A (recommended):** continue the odd outer-dimension ladder with `[355][2]^6 Pt`.
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- **Variant B:** keep width at ~0.690 MiBit but move the packed var to bench/function scope.
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- **Variant A (recommended):** continue the odd outer-dimension ladder with `[357][2]^6 Pt`.
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- **Variant B:** keep width at ~0.694 MiBit but move the packed var to bench/function scope.
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- **Variant C:** add `if`-guarded indexed signed field writes at the current width.
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---

‎.trinity/current_task/activity.md‎

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- **Commit:** feat(igla): Wave Loop 766 — module-scope [351][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1737)
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- **Files:** .claude/plans/wave-loop-768.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w767_bench_module_353x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md,scripts/gen_w767.py,specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27
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## 2026-07-23T18:05:01Z — wave-loop-768
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- **Commit:** feat(igla): Wave Loop 767 — module-scope [353][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1738)
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- **Files:** .claude/plans/wave-loop-769.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w768_bench_module_355x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W768_2026-07-23.md,scripts/gen_w768.py,specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27
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‎.trinity/experience.md‎

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---
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## 2026-07-23 — Wave Loop 768 (module-scope `[355][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
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### What worked
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- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 355.
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The `[355][2]^6 Pt` witness is 727,040 bits (~0.694 MiBit), still well under the 4-MiBit
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cliff, and required no compiler changes.
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- A module-level `pub var dst : [355][2]^6 Pt` can be initialized from a function
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call and exercised with indexed signed field writes, with zero compiler changes.
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- The cocotb/Python reference model correctly mirrored the row-major flattening
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with outer stride 355, confirming the layout is preserved end-to-end.
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- Reused the corrected W632 element-index formula for mid-row expected values:
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`[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
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- For `OUTER = 355`, `MID_IDX = 177`; the frame-condition element is
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`[177][1][0][0][0][0][0]`, element number `177*64 + 32 = 11,360`.
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- Updated weak-point audit: 42 of 51 30-day commits include `Closes #N` (≈82%).
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Clean non-worktree scan: 53 of 895 `.t27` specs lack `test`/`invariant`/`bench`
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(≈5.9%). 19 `scripts/*.sh` remain under `scripts/`.
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- Fresh 2025-2026 literature scan surfaced BitNet training/inference extensions,
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spintronic/MTJ ternary logic-in-memory, skyrmion multi-value probabilistic
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computing, and superconducting ternary output data links.
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### What changed behavior
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- No changes to `bootstrap/src/compiler.rs`.
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- No changes to `bootstrap/stage0/FROZEN_HASH`.
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- No changes to `scripts/cocotb_ref_model.py`.
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- Added `specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27` (~1,554 KB /
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~67,511 lines) with seal and Icarus baseline.
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- Added integration test `accepts_w768_bench_module_355x2p6_aos_var_call_write`.
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- Added generator script `scripts/gen_w768.py`.
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### Validation
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- `cargo build --release -p t27c`: OK.
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- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
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- `cargo test -p tri`: 78 passed; 0 failed.
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- `cargo test -p t27c --test icarus_lowerable`: 228 passed; 0 failed.
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- Direct `t27c parse` W768: PASS.
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- Direct `t27c icarus-lowerable` W768: PASS (`lowerable`).
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- Direct `t27c icarus-simulate` W768: PASS (17 cycles, PASSED).
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- Direct `t27c icarus-cocotb` W768: PASS (`reference-model OK`).
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### Scientific / engineering background
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- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
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packed dimensions, with no power-of-two restriction. Variant A emits a single
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727,040-bit packed vector, which is legal SystemVerilog.
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- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
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flattening nested arrays to wide packed vectors is a well-founded compiler
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discipline, even when outer dimensions are non-power-of-two.
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- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
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structs; t27 scalar flattening avoids that construct entirely.
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- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
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unsupported in the native frontend; t27 packed-vector lowering avoids the
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gap.
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- 2025-2026 ternary/MVL literature scan found:
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- BitNet b1.58 foundational ternary LLM and JMLR 2025 training recipe.
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- BitNet b1.58 2B4T — first open-source native 1-bit 2B LLM (4T tokens).
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- Bitnet.cpp — edge CPU inference with TL/I2_S kernels up to 6.25× vs FP16.
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- Sparse-BitNet — natural compatibility with N:M semi-structured sparsity.
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- Skyrmion multi-value probabilistic computing with current-controlled
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diffusion and MTJ-compatible readout (arXiv 2025).
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- MTJ+FinFET ternary logic-in-memory array with full ternary operator set
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(Results in Engineering 2025).
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- Reconfigurable skyrmion multi-port logic device with VCMA gating
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(Chinese Phys. Lett. 2026).
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- Cascading VCMA skyrmion AND/OR/NAND/NOR gates (Nanotechnology 2026).
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- Ternary RSFQ output data link, 3-bit→2-trit encoder, MIT Lincoln Lab
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SFQ5ee process (IEEE Trans. Appl. Supercond. 2025).
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- Verilog/SDF modeling framework for synchronous/asynchronous SFQ/RSFQ/ASFQ
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pulse-based logic (arXiv 2026).
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- OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
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7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
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---
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## 2026-07-23 — Wave Loop 767 (module-scope `[353][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
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### What worked

‎.trinity/seals/scratch_w768_bench_module_355x2p6_aos_var_call_write.json‎

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{
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"gen_hash_c": "sha256:0a7d6ea763e3f6e1e4912a03bf3882bbe4d31a803d6593629fb83ecac4c921ec",
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"gen_hash_rust": "sha256:501ff5b5839e249cdc06c66406f59362ef58e54f808aab05adab44a3a48cf01b",
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"gen_hash_verilog": "sha256:07b175d07eca5b9d035f4a8e1180eafac3d9bd230ede97b24fac8faf4cf3207e",
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"gen_hash_zig": "sha256:ef8314dceaa4a287c4d1617ec91133f6e972a05e723c2407ad743196852dcca9",
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"module": "w768_bench_module_355x2p6_aos_var_call_write",
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"ring": 12,
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"sealed_at": "2026-07-23T18:00:13Z",
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"spec_hash": "sha256:0be372286e5ad05f7330efd1e2104b4cc4f2148e18125905656715844e0f3ef5",
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"spec_path": "specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27"
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}

‎bootstrap/tests/icarus_lowerable.rs‎

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}
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}
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#[test]
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fn accepts_w768_bench_module_355x2p6_aos_var_call_write() {
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let dir = scratch_dir();
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for name in &[
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"w768_bench_module_355x2p6_aos_var_call_write.t27",
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] {
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let p = dir.join(name);
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assert!(p.exists(), "missing W768 witness {}", p.display());
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let (lowerable, json) = run_icarus_lowerable(&p);
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assert!(
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lowerable,
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"expected {} to be lowerable, got: {}",
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p.display(),
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json
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);
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}
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}
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#[test]
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fn accepts_known_lowerable_witnesses() {
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let dir = scratch_dir();

‎docs/NOW.md‎

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# NOW — Wave Loop 767 close-out / Wave Loop 768 setup (2026-07-23)
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# NOW — Wave Loop 768 close-out / Wave Loop 769 setup (2026-07-23)
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Last updated: 2026-07-23
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## Wave Loop 767 — module-scope `[353][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1738)
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## Wave Loop 768 — module-scope `[355][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1739)
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- Branch: `wave-loop-767`
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- Issue: #1738
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- Branch: `wave-loop-768`
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- Issue: #1739
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- PR: to open
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- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W767_2026-07-23.md`
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- Plan: `.claude/plans/wave-loop-767.md`
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- Cooperation W768: `.claude/plans/wave-loop-768.md`
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- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W768_2026-07-23.md`
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- Plan: `.claude/plans/wave-loop-768.md`
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- Cooperation W769: `.claude/plans/wave-loop-769.md`
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### What landed
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- `specs/scratch/w767_bench_module_353x2p6_aos_var_call_write.t27`
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- 22,592 elements, 722,944-bit packed vector (~0.690 MiBit).
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- Module-scope `pub var dst : [353][2]^6 Pt` initialized from a function call and
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- `specs/scratch/w768_bench_module_355x2p6_aos_var_call_write.t27`
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- 22,720 elements, 727,040-bit packed vector (~0.694 MiBit).
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- Module-scope `pub var dst : [355][2]^6 Pt` initialized from a function call and
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exercised with indexed signed field writes.
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- `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
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- `scripts/gen_w767.py`
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- Generator for the W767 witness; `OUTER = 353`, `MID_IDX = 176`.
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- `scripts/gen_w768.py`
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- Generator for the W768 witness; `OUTER = 355`, `MID_IDX = 177`.
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- `bootstrap/tests/icarus_lowerable.rs`
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- Added `accepts_w767_bench_module_353x2p6_aos_var_call_write`.
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- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-768.md`
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- W767 learnings saved and W768 issue/plan created.
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- Added `accepts_w768_bench_module_355x2p6_aos_var_call_write`.
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- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-769.md`
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- W768 learnings saved and W769 issue/plan created.
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### Not changed
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- `bootstrap/src/compiler.rs` — zero compiler changes.
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- `cargo build --release -p t27c`: OK.
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- `cargo test -p t27c --bin t27c`: 1494/0/2.
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- `cargo test -p tri`: 78/0.
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- `cargo test -p t27c --test icarus_lowerable`: 227/0.
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- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W767: PASS.
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- `cargo test -p t27c --test icarus_lowerable`: 228/0.
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- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W768: PASS.
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---
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## Wave Loop 769 — next odd outer-dimension `[357][2]^6 Pt` (Issue #1740)
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- Branch: `wave-loop-769` (to create after W768 merge)
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- Issue: #1740
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- Plan: `.claude/plans/wave-loop-769.md`
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### Candidate variants
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- Variant A (recommended): continue the odd outer-dimension ladder with `[357][2]^6 Pt`.
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- Variant B: keep width at ~0.694 MiBit but move the packed var to bench/function scope.
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- Variant C: add `if`-guarded indexed signed field writes at the current width.
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---
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