feat(igla): Wave Loop 770 — module-scope [359][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1741)

Author: Dmitrii Vasilev

.claude/plans/wave-loop-771.md

@@ -0,0 +1,48 @@
+# Wave Loop 771 Plan — Issue #1742
+
+## Phase 1: Issue
+- Confirm W771 issue #1742 and branch `wave-loop-771`.
+
+## Phase 2: Spec
+- Generate `specs/scratch/w771_bench_module_361x2p6_aos_var_call_write.t27` using
+  `scripts/gen_w771.py` derived from `scripts/gen_w770.py`.
+- Constants: `OUTER = 361`, `TOTAL = 23104`, `LAST_IDX = 360`, `MID_IDX = 180`.
+
+## Phase 3: TDD
+- Inspect generated assertions: `make_grid(32768)`, `make_grid(1)`,
+  `call_write_grid`, field writes, `assert_eq` read-backs, mid and last checks.
+
+## Phase 4: Impl
+- Add integration test `accepts_w771_bench_module_361x2p6_aos_var_call_write` to
+  `bootstrap/tests/icarus_lowerable.rs`.
+
+## Phase 5: Gen
+- Run `cd bootstrap && cargo build --release -p t27c`.
+
+## Phase 6: Seal
+- Run `./bootstrap/target/release/t27c seal --save specs/scratch/w771_bench_module_361x2p6_aos_var_call_write.t27`.
+- Confirm FROZEN_HASH unchanged.
+
+## Phase 7: Verify
+- `./bootstrap/target/release/t27c parse ...`
+- `./bootstrap/target/release/t27c icarus-lowerable ...`
+- `./bootstrap/target/release/t27c icarus-simulate ...` (17 cycles)
+- `./bootstrap/target/release/t27c icarus-cocotb ...`
+- `cargo test -p t27c --bin t27c`
+- `cargo test -p tri`
+- `cargo test -p t27c --test icarus_lowerable`
+
+## Phase 8: Land
+- Commit with `feat(igla): Wave Loop 771 — module-scope [361][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1742)`.
+- Push `wave-loop-771`, open PR, merge to `master`, create `wave-loop-772`.
+
+## Phase 9: Learn
+- Write `docs/reports/FPGA_LOOP_CLOSEOUT_W771_2026-07-24.md`.
+- Save `.trinity/experience.md`, memory file, `MEMORY.md` pointer, and update
+  `skills-wave-loop-recipe.md`.
+
+## Cooperation variants for next Wave Loop
+
+- **A (recommended):** `[363][2]^6 Pt` (~0.709 MiBit), continuing the odd ladder.
+- **B:** move the packed variable to bench/function scope at the same width.
+- **C:** add conditional (`if`) indexed writes at the current width.

.trinity/current-issue.md

@@ -1,45 +1,45 @@
-# Wave Loop 769 — Issue #1740
+# Wave Loop 770 — Issue #1741
 
-**Branch:** `wave-loop-769`  
+**Branch:** `wave-loop-770`  
 **Date:** 2026-07-24  
 **Cooperation variant:** A (recommended)
 
 ## Goal
 
-Close Wave Loop 769 by validating a module-scope `[357][2]^6 Pt` packed
+Close Wave Loop 770 by validating a module-scope `[359][2]^6 Pt` packed
 array-of-struct variable initialized from a function call, with indexed signed
 field writes and `assert_eq` read-back in a `bench` block.
 
 ## Acceptance criteria
 
-1. `specs/scratch/w769_bench_module_357x2p6_aos_var_call_write.t27` is generated and parses.
+1. `specs/scratch/w770_bench_module_359x2p6_aos_var_call_write.t27` is generated and parses.
 2. The witness is Icarus-lowerable and simulates correctly (17 cycles, PASSED).
 3. The cocotb reference model matches the t27 semantics.
 4. `t27c seal --save` succeeds and FROZEN_HASH remains unchanged.
 5. All cargo suites remain green.
-6. Integration test `accepts_w769_bench_module_357x2p6_aos_var_call_write` is added.
-7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W769_2026-07-24.md` is written.
+6. Integration test `accepts_w770_bench_module_359x2p6_aos_var_call_write` is added.
+7. Closeout report `docs/reports/FPGA_LOOP_CLOSEOUT_W770_2026-07-24.md` is written.
 8. Learning is saved to `.trinity/experience.md`, memory, and `skills-wave-loop-recipe.md`.
-9. Branch merges to `master` with `Closes #1740`.
+9. Branch merges to `master` with `Closes #1741`.
 
 ## Technical notes
 
-- Shape: `[357][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
-- Total elements: `357 x 64 = 22,848`.
-- Packed vector width: `22,848 x 32 = 731,136` bits (~0.697 MiBit).
-- `MID_IDX = 178`; frame-condition element `[178][1][0][0][0][0][0]` is element
-  `178*64 + 32 = 11,424`.
-- Generator script: `scripts/gen_w769.py` (copy from `scripts/gen_w768.py`, set
-  `OUTER = 357` and `MID_IDX = 178`, manually fix the f-string header).
+- Shape: `[359][2]^6 Pt` where `Pt = pub struct Pt { x : i16, y : i16 }`.
+- Total elements: `359 x 64 = 22,976`.
+- Packed vector width: `22,976 x 32 = 735,232` bits (~0.701 MiBit).
+- `MID_IDX = 179`; frame-condition element `[179][1][0][0][0][0][0]` is element
+  `179*64 + 32 = 11,488`.
+- Generator script: `scripts/gen_w770.py` (copy from `scripts/gen_w769.py`, set
+  `OUTER = 359` and `MID_IDX = 179`, manually fix the f-string header).
 - Use `assert_eq` checks on changed elements (Icarus simulation path does not
   emit `assert_ne`).
 - Include `make_grid(32768)` period-identity check because `32768 == 0 (mod 32768)`.
 - Zero compiler / reference-model / FROZEN_HASH changes expected.
 
 ## Cooperation variants for next Wave Loop
 
-- **Variant A (recommended):** continue the odd outer-dimension ladder with `[359][2]^6 Pt`.
-- **Variant B:** keep width at ~0.697 MiBit but move the packed var to bench/function scope.
+- **Variant A (recommended):** continue the odd outer-dimension ladder with `[361][2]^6 Pt`.
+- **Variant B:** keep width at ~0.701 MiBit but move the packed var to bench/function scope.
 - **Variant C:** add `if`-guarded indexed signed field writes at the current width.
 
 ---

.trinity/current_task/activity.md

@@ -3688,3 +3688,11 @@
 - **Commit:** feat(igla): Wave Loop 768 — module-scope [355][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1739)
 - **Files:** .claude/plans/wave-loop-770.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w769_bench_module_357x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/NOW.md,docs/reports/FPGA_LOOP_CLOSEOUT_W769_2026-07-24.md,scripts/gen_w769.py,specs/scratch/w769_bench_module_357x2p6_aos_var_call_write.t27
 
+## 2026-07-23T18:30:25Z — wave-loop-770
+- **Commit:** feat(igla): Wave Loop 769 — module-scope [357][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1740)
+- **Files:** .claude/plans/wave-loop-771.md,.trinity/current-issue.md,.trinity/experience.md,.trinity/seals/scratch_w770_bench_module_359x2p6_aos_var_call_write.json,bootstrap/tests/icarus_lowerable.rs,docs/reports/FPGA_LOOP_CLOSEOUT_W770_2026-07-24.md,scripts/gen_w770.py,specs/scratch/w770_bench_module_359x2p6_aos_var_call_write.t27
+
+## 2026-07-23T18:31:56Z — wave-loop-770
+- **Commit:** feat(igla): Wave Loop 770 — module-scope [359][2]^6 Pt non-power-of-two outer-dimension array-of-struct variable from call with indexed signed writes (Closes #1741)
+- **Files:** docs/NOW.md
+

.trinity/experience.md

@@ -1,3 +1,80 @@
+## 2026-07-24 — Wave Loop 770 (module-scope `[359][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
+
+### What worked
+- Variant A extended the module-scope packed AoS odd outer-dimension ladder to 359.
+  The `[359][2]^6 Pt` witness is 735,232 bits (~0.701 MiBit), still well under the 4-MiBit
+  cliff, and required no compiler changes.
+- A module-level `pub var dst : [359][2]^6 Pt` can be initialized from a function
+  call and exercised with indexed signed field writes, with zero compiler changes.
+- The cocotb/Python reference model correctly mirrored the row-major flattening
+  with outer stride 359, confirming the layout is preserved end-to-end.
+- Reused the corrected W632 element-index formula for mid-row expected values:
+  `[r][a5][a4][a3][a2][a1][a0]` is element `r*64 + a5*32 + a4*16 + a3*8 + a2*4 + a1*2 + a0`.
+- For `OUTER = 359`, `MID_IDX = 179`; the frame-condition element is
+  `[179][1][0][0][0][0][0]`, element number `179*64 + 32 = 11,488`.
+- Updated weak-point audit: 44 of 53 30-day commits include `Closes #N` (≈83%).
+  Clean non-worktree scan: 57 of 873 `.t27` specs lack `test`/`invariant`/`bench`
+  (≈6.5%). 19 `scripts/*.sh` remain under `scripts/`.
+- Fresh 2025-2026 literature scan surfaced ternary FPGA LLM accelerators (TeLLMe,
+  TerEffic), ternary HDL/ISA work (Ternary VHDL, Setnex, REBEL-6, xTern, T-SAR),
+  and memristor/FeFET ternary logic-in-memory arrays.
+
+### What changed behavior
+- No changes to `bootstrap/src/compiler.rs`.
+- No changes to `bootstrap/stage0/FROZEN_HASH`.
+- No changes to `scripts/cocotb_ref_model.py`.
+- Added `specs/scratch/w770_bench_module_359x2p6_aos_var_call_write.t27` (~1,572 KB /
+  ~68,271 lines) with seal and Icarus baseline.
+- Added integration test `accepts_w770_bench_module_359x2p6_aos_var_call_write`.
+- Added generator script `scripts/gen_w770.py`.
+
+### Validation
+- `cargo build --release -p t27c`: OK.
+- `cargo test -p t27c --bin t27c`: 1494 passed; 0 failed; 2 ignored.
+- `cargo test -p tri`: 78 passed; 0 failed.
+- `cargo test -p t27c --test icarus_lowerable`: 230 passed; 0 failed.
+- Direct `t27c parse` W770: PASS.
+- Direct `t27c icarus-lowerable` W770: PASS (`lowerable`).
+- Direct `t27c icarus-simulate` W770: PASS (17 cycles, PASSED).
+- Direct `t27c icarus-cocotb` W770: PASS (`reference-model OK`).
+
+### Scientific / engineering background
+- IEEE 1800-2017 7.4.1/7.4.3 define packed-array total width as the product of
+  packed dimensions, with no power-of-two restriction. Variant A emits a single
+  735,232-bit packed vector, which is legal SystemVerilog.
+- Lutsig verified array lowering and CIRCT `HWLegalizeModules` show that
+  flattening nested arrays to wide packed vectors is a well-founded compiler
+  discipline, even when outer dimensions are non-power-of-two.
+- Icarus issue #1134 documents assertion failures for unpacked arrays of packed
+  structs; t27 scalar flattening avoids that construct entirely.
+- Yosys issue #2677 / #4653 confirm that arrays of packed structs remain
+  unsupported in the native frontend; t27 packed-vector lowering avoids the
+  gap.
+- 2025-2026 ternary/MVL literature scan found:
+  - TeLLMe — energy-efficient ternary LLM accelerator on edge FPGAs with
+    table-lookup MatMul and fused attention (arXiv 2025).
+  - TerEffic — highly efficient ternary LLM inference on FPGA with 1.6-bit
+    compression and LUT-based TMat Core (arXiv 2025).
+  - Ternary VHDL — IEEE 1076-2008 extension for balanced ternary mixed-radix
+    VLSI design and GHDL simulation (IEEE ISMVL 2026).
+  - Setnex ISA v0.8 — clean-slate balanced-ternary ISA with 27-trit words and
+    configurable three-valued logics (2026).
+  - REBEL-6 — 32-trit balanced ternary ISA binary-compatible with RV32I
+    (IEEE ISMVL 2025).
+  - xTern — RISC-V ISA extension with packed-SIMD ternary MAC for edge NN
+    inference (arXiv 2024).
+  - T-SAR — CPU-only ternary LLM inference via in-place SIMD ALU
+    reorganization, extensible to RISC-V Vector (arXiv 2025).
+  - Memristor-based balanced ternary logic gates, decoders, full adders, and
+    Łukasiewicz logic using tri-valued resistance states (EPJP 2026, Phil.
+    Trans. R. Soc. A 2025, IJCTA 2026).
+  - FeFET-based non-volatile comparator with built-in less-than operation
+    (IEICE ELEX 2025).
+  - OpenXC7 / nextpnr-xilinx / Project X-Ray — fully open-source Xilinx
+    7-series toolchain, used for QMTech XC7A100T ternary projects without Vivado.
+
+---
+
 ## 2026-07-23 — Wave Loop 769 (module-scope `[357][2]^6 Pt` non-power-of-two outer-dimension AoS variable)
 
 ### What worked

.trinity/seals/scratch_w770_bench_module_359x2p6_aos_var_call_write.json

@@ -0,0 +1,11 @@
+{
+  "gen_hash_c": "sha256:44aff9f243b87b121d30cae112425b85691e10eca416a0a9289a72ab527eae15",
+  "gen_hash_rust": "sha256:0d86b72e63446bb3be468c2acc8dfe1212f60ad25839fcc9df6e8917dd42ff2f",
+  "gen_hash_verilog": "sha256:6aea36e0741286b4cde890fd14201b459bc387fce9570c8f6d1b7eb1051807c0",
+  "gen_hash_zig": "sha256:02d9e927c6b83323a74dbe3fd09a6fc91d9888da7618466217ddce6af7b9656a",
+  "module": "w770_bench_module_359x2p6_aos_var_call_write",
+  "ring": 12,
+  "sealed_at": "2026-07-23T18:27:12Z",
+  "spec_hash": "sha256:1dc5281e1481d494baf2a837df74a6d35bbdc09595bb9df56e3df46dfa1fb087",
+  "spec_path": "specs/scratch/w770_bench_module_359x2p6_aos_var_call_write.t27"
+}

bootstrap/tests/icarus_lowerable.rs

@@ -4153,6 +4153,24 @@ fn accepts_w769_bench_module_357x2p6_aos_var_call_write() {
     }
 }
 
+#[test]
+fn accepts_w770_bench_module_359x2p6_aos_var_call_write() {
+    let dir = scratch_dir();
+    for name in &[
+        "w770_bench_module_359x2p6_aos_var_call_write.t27",
+    ] {
+        let p = dir.join(name);
+        assert!(p.exists(), "missing W770 witness {}", p.display());
+        let (lowerable, json) = run_icarus_lowerable(&p);
+        assert!(
+            lowerable,
+            "expected {} to be lowerable, got: {}",
+            p.display(),
+            json
+        );
+    }
+}
+
 #[test]
 fn accepts_known_lowerable_witnesses() {
     let dir = scratch_dir();

docs/NOW.md

@@ -1,28 +1,28 @@
-# NOW — Wave Loop 769 close-out / Wave Loop 770 setup (2026-07-24)
+# NOW — Wave Loop 770 close-out / Wave Loop 771 setup (2026-07-24)
 
 Last updated: 2026-07-24
 
-## Wave Loop 769 — module-scope `[357][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1740)
+## Wave Loop 770 — module-scope `[359][2]^6 Pt` packed array-of-struct from call with indexed signed writes (Closes #1741)
 
-- Branch: `wave-loop-769`
-- Issue: #1740
+- Branch: `wave-loop-770`
+- Issue: #1741
 - PR: to open
-- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W769_2026-07-24.md`
-- Plan: `.claude/plans/wave-loop-769.md`
-- Cooperation W770: `.claude/plans/wave-loop-770.md`
+- Report: `docs/reports/FPGA_LOOP_CLOSEOUT_W770_2026-07-24.md`
+- Plan: `.claude/plans/wave-loop-770.md`
+- Cooperation W771: `.claude/plans/wave-loop-771.md`
 
 ### What landed
-- `specs/scratch/w769_bench_module_357x2p6_aos_var_call_write.t27`
-  - 22,848 elements, 731,136-bit packed vector (~0.697 MiBit).
-  - Module-scope `pub var dst : [357][2]^6 Pt` initialized from a function call and
+- `specs/scratch/w770_bench_module_359x2p6_aos_var_call_write.t27`
+  - 22,976 elements, 735,232-bit packed vector (~0.701 MiBit).
+  - Module-scope `pub var dst : [359][2]^6 Pt` initialized from a function call and
     exercised with indexed signed field writes.
   - `assert_eq` read-back in a `bench` block (Icarus path does not emit `assert_ne`).
-- `scripts/gen_w769.py`
-  - Generator for the W769 witness; `OUTER = 357`, `MID_IDX = 178`.
+- `scripts/gen_w770.py`
+  - Generator for the W770 witness; `OUTER = 359`, `MID_IDX = 179`.
 - `bootstrap/tests/icarus_lowerable.rs`
-  - Added `accepts_w769_bench_module_357x2p6_aos_var_call_write`.
-- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-770.md`
-  - W769 learnings saved and W770 issue/plan created.
+  - Added `accepts_w770_bench_module_359x2p6_aos_var_call_write`.
+- `.trinity/experience.md`, `.trinity/current-issue.md`, `.claude/plans/wave-loop-771.md`
+  - W770 learnings saved and W771 issue/plan created.
 
 ### Not changed
 - `bootstrap/src/compiler.rs` — zero compiler changes.
@@ -33,20 +33,20 @@ Last updated: 2026-07-24
 - `cargo build --release -p t27c`: OK.
 - `cargo test -p t27c --bin t27c`: 1494/0/2.
 - `cargo test -p tri`: 78/0.
-- `cargo test -p t27c --test icarus_lowerable`: 229/0.
-- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W769: PASS.
+- `cargo test -p t27c --test icarus_lowerable`: 230/0.
+- `t27c parse|icarus-lowerable|icarus-simulate|icarus-cocotb|seal --save` W770: PASS.
 
 ---
 
-## Wave Loop 770 — next odd outer-dimension `[359][2]^6 Pt` (Issue #1741)
+## Wave Loop 771 — next odd outer-dimension `[361][2]^6 Pt` (Issue #1742)
 
-- Branch: `wave-loop-770` (to create after W769 merge)
-- Issue: #1741
-- Plan: `.claude/plans/wave-loop-770.md`
+- Branch: `wave-loop-771` (to create after W770 merge)
+- Issue: #1742
+- Plan: `.claude/plans/wave-loop-771.md`
 
 ### Candidate variants
-- Variant A (recommended): continue the odd outer-dimension ladder with `[359][2]^6 Pt`.
-- Variant B: keep width at ~0.697 MiBit but move the packed var to bench/function scope.
+- Variant A (recommended): continue the odd outer-dimension ladder with `[361][2]^6 Pt`.
+- Variant B: keep width at ~0.701 MiBit but move the packed var to bench/function scope.
 - Variant C: add `if`-guarded indexed signed field writes at the current width.
 
 ---