feat(igla): W403 bitstream config linked to cold-POR decision tree in Lean 4#1308
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…ion tree in Lean 4 (Closes #1307) - Add BitstreamConfig + canonical predicate to TernaryFPGABoot.lean (IDCODE=0x03636093, SPI_BUSWIDTH=x1, STARTUPCLK=CCLK, OSCFSEL=0). - Add ColdPOR preconditions and linkage lemmas: cold_por_done_eos_high_implies_boot_success, cold_por_done_low_implies_h2, decision_tree_exhaustive. - Update fpga/HARDWARE_SSOT.md §3.2 with bitstream-config formal traceability. - Update docs/NOW.md and .trinity/experience.md with W403 learnings. - Add close-out reports: WAVE_LOOP_403_REPORT.md, FPGA_LOOP_EVIDENCE_2026-07-06.md, FPGA_LOOP_COOPERATION_2026-07-06.md. - Conformance suite 576/576 PASS; lake build Trinity.TernaryFPGABoot green. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-07-04 09:13:57 UTC
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Closes #1307
Extends the W402 Lean 4 STAT-register model with bitstream-level predicates and cold-POR linkage.
Verification:
Physical CCLK measurement (Variant A) and --require-cable SRAM smoke (Variant C) remain deferred to W404.
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