Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation

.claude/plans/wave-loop-420.md

@@ -0,0 +1,69 @@
+# Wave Loop 420 — Decomposed Plan
+
+**Issue:** #1361  
+**Branch:** `wave-loop-420`  
+**Default variant:** C (physical bench still blocked: DLC10 cable not found, P12 unwired, no relay)
+
+---
+
+## 1. Weak points identified
+
+1. **Missing VCD `$comment` exact-token terminator.** The W419 report claimed this
+   hardening landed, but the merged commit (`101fd0748`) did not touch the VCD
+   parser. The current code still uses `ends_with("$end")` / `contains(" $end")`
+   heuristics, so a `$comment` block containing the literal substring `$end`
+   terminates early and corrupts the signal dictionary.
+2. **Real-valued VCD nets require an explicit `--vcd-threshold-v`.** There is no
+   auto-threshold fallback for analog VCD exports; users must know the voltage
+   swing up-front.
+3. **PVT half-period bound lacks a process-corner monotonicity lemma.** We have
+   temperature monotonicity and VCCINT antitonicity from W419, but no formal
+   statement that `ff ≤ tt ≤ ss` is preserved by the half-period bound itself.
+
+---
+
+## 2. Competitor landscape (high-level)
+
+The closest formal-HDL competition is **Sparkle / Verilean** (Lean 4 native,
+binary RTL). Other credible players: **Clash** (Haskell, external formal),
+**Chisel/FIRRTL/CIRCT** (mainstream, SVA/model-checking oriented),
+**Bluespec** (rule-based, Coq bridge via Kami), **Coq Kami / Silver Oak**
+(dependent-type hardware), **ACL2** (specification/proof layer only).
+
+None combine Lean 4 native proof, a ternary compute stack, spec-first sealed
+`*.t27 → gen/` code generation, and physical boot-evidence instrumentation.
+That intersection is the gap t27 fills.
+
+---
+
+## 3. Implementation steps
+
+| Step | Files | Deliverable | Acceptance |
+|------|-------|-------------|------------|
+| 3.1 | `cli/tri/src/fpga.rs` | Replace VCD `$date`/`$version`/`$comment` terminator heuristics with exact-token check; clear state immediately on same-line termination. | `test_parse_vcd_comment_with_embedded_end_token` PASS |
+| 3.2 | `cli/tri/src/fpga.rs` | Add VCD auto-threshold for real-valued nets: compute `50% (vmin + vmax)` when `--vcd-threshold-v` is omitted; warn user. | `test_parse_vcd_real_auto_threshold` PASS |
+| 3.3 | `proofs/lean4/Trinity/TernaryFPGABoot.lean` | Add `pvt_half_ns_monotone_in_process_corner` lemma: `c1.worse_than c2 → bound c1 ≤ bound c2`. | `lake build` PASS |
+| 3.4 | `cli/tri/src/fpga.rs` | Add Rust test `test_pvt_half_ns_monotone_in_process_corner`. | `cargo test` PASS |
+| 3.5 | `fpga/HARDWARE_SSOT.md` | Document VCD `$comment` exact-terminator behavior and real-net auto-threshold. | docs render clean |
+| 3.6 | `.trinity/experience.md` | Capture W420 learnings. | committed |
+| 3.7 | `docs/reports/*` | W420 report, evidence, W421 cooperation variants. | committed |
+
+---
+
+## 4. Verification plan
+
+- `cargo test -p tri vcd` — expect 12 tests (was 11).
+- `cargo test -p tri pvt` — expect 10 tests (was 9).
+- `cargo test -p tri fpga::tests` — expect 47 tests (was 45).
+- `lake build Trinity.TernaryFPGABoot` — must PASS.
+- `./scripts/tri test` — must PASS except 16 pre-existing gen-verilog yosys failures.
+
+---
+
+## 5. Land
+
+- Commit with `Closes #1361`.
+- Open PR #? from `wave-loop-420` → `master`.
+- After merge, create issue #? and branch `wave-loop-421`.
+
+*φ² + φ⁻² = 3 | TRINITY*

.claude/plans/wave-loop-421.md

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+# Wave Loop 421 Decomposed Plan
+
+**Issue:** #1363  
+**Branch:** `wave-loop-421`  
+**Date:** 2026-07-06  
+**Selected variant:** C (fallback — hardware still unreachable)
+
+---
+
+## 1. Weak-point analysis
+
+### 1.1 W420 dependency / branch state
+- `wave-loop-421` was created from `master` (101fd0748) **before** PR #1362
+  (Wave Loop 420) merges. This means the W421 branch initially lacked the W420
+  VCD exact-terminator and auto-threshold work.
+- **Mitigation:** reset `wave-loop-421` onto `wave-loop-420` so W421 builds on
+  top of W420. Once PR #1362 lands, W421 can be rebased onto `master` cleanly.
+
+### 1.2 VCD parser remaining gaps
+- `$date` / `$version` / `$comment` sections now use exact-token terminators
+  (W420), but `$timescale` still uses the old substring heuristics
+  `contains(" $end")` / `ends_with(" $end")`. A `$timescale` comment that
+  mentions `$end` could therefore mis-parse.
+- Real-valued net auto-threshold works, but has no regression test for a
+  non-default `$timescale` unit (e.g., `1 us` or `1 ps`).
+
+### 1.3 PVT envelope
+- W419/W420 proved each axis independently (temp monotone, VCCINT antitone,
+  corner monotone). The combined ordering (temp ↑, VCCINT ↓, corner worse) is
+  not yet a single lemma/test, which is what a worst-case operating-point
+  search actually needs.
+
+### 1.4 Competition
+- Sparkle/Verilean (Lean 4 native HDL) is the closest competitor and is
+  accelerating in 2026: RV32IMA SoC, networking stack, crypto, formal proofs.
+- Clash Formal and CIRCT/Chisel LTL/Verif dialects are also closing the formal
+  gap from the mainstream side.
+- t27 must keep differentiating through: (a) ternary/balanced-trit compute + Lean
+  proof lattice, (b) spec-first `*.t27 → gen/` sealed pipeline, (c) physical
+  boot-evidence instrumentation.
+
+### 1.5 Hardware
+- The Digilent FTDI cable is present (`0x0403:0x6014`), but `openFPGALoader
+  --detect` reports **0 devices**. The board is either not powered, not wired,
+  or the JTAG header is disconnected. Variant A is therefore still blocked.
+
+---
+
+## 2. Work items
+
+| # | File | Change | Test |
+|---|------|--------|------|
+| 1 | `cli/tri/src/fpga.rs` | Apply `vcd_line_ends_with_token` to `$timescale` terminator | `test_parse_vcd_timescale_with_embedded_end_token` |
+| 2 | `cli/tri/src/fpga.rs` | Add non-default `$timescale` real-net parse test | `test_parse_vcd_real_auto_threshold_us_timescale` |
+| 3 | `proofs/lean4/Trinity/TernaryFPGABoot.lean` | Add combined PVT monotonicity lemma | `lake build Trinity.TernaryFPGABoot` |
+| 4 | `cli/tri/src/fpga.rs` | Add combined PVT monotonicity Rust test | `test_pvt_half_ns_monotone_combined` |
+| 5 | `docs/reports/T27_VS_FORMAL_HDL_2026.md` | Competitor comparison note | visual review |
+| 6 | `fpga/HARDWARE_SSOT.md` | §3.6.18 documenting W421 parser + PVT improvements | visual review |
+| 7 | `docs/NOW.md` | W421 close-out / W422 setup | visual review |
+| 8 | `.trinity/experience.md` | W421 learnings | visual review |
+| 9 | `docs/reports/*` | W421 report, evidence, W422 cooperation | visual review |
+| 10 | git/PR/issue | Commit, open PR #? for W421, create W422 issue + branch | CI passes |
+
+---
+
+## 3. Verification checklist
+
+- [ ] `cargo test -p tri vcd`: all PASS (was 13).
+- [ ] `cargo test -p tri pvt`: all PASS (was 10).
+- [ ] `cargo test -p tri fpga::tests`: all PASS (was 48).
+- [ ] `lake build Trinity.TernaryFPGABoot`: PASS.
+- [ ] `./scripts/tri test`: no new failures beyond the 16 pre-existing yosys
+      smoke failures from weak point #1245.
+
+---
+
+*φ² + φ⁻² = 3 | TRINITY*

.trinity/current-issue.md

@@ -1,97 +1,123 @@
-# Wave Loop 419 — physical CCLK capture, real relay gate, or instrument-import parity
+# Wave Loop 429 — FPGA boot-evidence next variant (physical CCLK / XADC readout / formal fallback)
 
-**Issue:** #1357  
-**Branch:** `wave-loop-419`  
-**Milestone:** Continue the FPGA boot-evidence line from W418.
+**Issue:** #1385  
+**Branch:** `wave-loop-429`  
+**Milestone:** Continue the FPGA boot-evidence line from Wave Loop 428.
 
 ---
 
 ## Goal
 
-Wave 418 closed the Variant C fallback (formal tooling and instrument import).
-Wave 419 re-evaluates the bench state and executes the first available variant.
+Wave Loop 428 hardened the FPGA CLI and formal model while the bench was blocked
+(P12 unwired, no relay gate, no DLC10 cable, no OSCFSEL 6/7 bitstreams, no
+external captures). Wave Loop 429 executes the first available variant from
+`docs/reports/FPGA_LOOP_COOPERATION_W429_2026-07-05.md`.
 
 1. **Variant A (preferred when bench becomes available):**
-   - Wire P12 to a logic-analyzer channel and capture real CCLK for
-     `OSCFSEL=6` and `OSCFSEL=7`.
-   - Program each variant to SPI flash and perform a true cold-POR boot.
-   - Import the captures with `tri fpga measured-to-lean --csv/--vcd --raw-ns
-     --standalone --validate --pvt-context <ctx.json>` and commit the generated
-     Lean theorems.
-   - Document the measured frequencies/duty cycles and PVT context in
-     `fpga/HARDWARE_SSOT.md`.
-
-2. **Variant B (if relay hardware is available, no CCLK probe):**
-   - Implement a real `--relay-port` backend for `tri fpga cold-por`
-     (e.g. serial or TCP relay controlling board power).
-   - Perform an automated cold-POR power-cycle and capture STAT without
-     operator intervention.
-   - Document relay wiring and port syntax in `fpga/HARDWARE_SSOT.md`.
+   - Confirm P12 is wired to a logic-analyzer channel.
+   - Program SPI flash with OSCFSEL=6 and OSCFSEL=7 variants.
+   - Capture real CCLK during cold-POR boot for both variants.
+   - Import with `tri fpga measured-to-lean --csv/--vcd --raw-ns --standalone
+     --validate --pvt-context <ctx.json>` and commit generated Lean theorems.
+   - Document frequencies/duty cycles and PVT context in
+     `fpga/HARDWARE_SSOT.md` §3.6.
+
+2. **Variant B (if board is reachable or external capture available):**
+   - Add real XADC readout to `tri fpga boot-log` / `cclk-sweep` / `cold-por`
+     over the existing JTAG path, so JSON `xadc` has `source: "xadc"` and live
+     temp/vccint/vccaux values.
+   - Alternatively, import at least one external CSV/VCD capture end-to-end.
+   - Run dry-run or real cold-POR sweep for OSCFSEL 6/7 variants with
+     `--pvt-context`.
+   - Document the recipe in `fpga/HARDWARE_SSOT.md` §3.6.
 
 3. **Variant C (fallback if bench still blocked):**
-   - Extend instrument-import parity: additional VCD/CSV formats and hardened
-     `$comment` sections.
-   - Add PVT envelope monotonicity/antitonicity tests in Rust and Lean.
-   - Document the standalone `lake`-package workflow end-to-end in
-     `fpga/HARDWARE_SSOT.md`.
+   - Extend the unified OSCFSEL PVT theorem library from W428 (e.g. a theorem
+     linking a measured raw-ns capture to the unified
+     `cclk_variant_implies_transaction_ok` family when the period matches a
+     nominal variant within tolerance).
+   - Land one safe gen-verilog #1245 sub-fix if narrow and regression-free;
+     otherwise explicitly defer and update
+     `docs/reports/GEN_VERILOG_DEFECTS_REPRO.md`.
+   - Further harden `tri fpga` CLI or JSON output (e.g. add `--json` to
+     `measured-to-lean` summary or enrich `pvt-envelope --json`).
+   - Refresh `docs/reports/T27_VS_FORMAL_HDL_2026.md` if new 2026 competitor
+     developments surface.
 
 ---
 
 ## Decomposed plan
 
-See `docs/reports/FPGA_LOOP_COOPERATION_W419_2026-07-04.md` and
-`.claude/plans/wave-loop-419.md`.
-
 | Step | File(s) | Deliverable |
 |------|---------|-------------|
-| 1 | `cli/tri/src/fpga.rs` | Variant A import, B relay backend, or C parity/monotonicity tests |
-| 2 | `proofs/lean4/Trinity/TernaryFPGABoot.lean` | PVT monotonicity lemmas or new measured theorems |
-| 3 | `fpga/HARDWARE_SSOT.md` | Updated capture / relay / integration protocol |
-| 4 | `docs/reports/*` | W419 report, evidence, W420 cooperation |
-| 5 | `.trinity/experience.md` | W419 learnings |
-| 6 | git/PR | squash-merge to `master`, close #1357, open #? for W420 |
+| 1 | `proofs/lean4/Trinity/TernaryFPGABoot.lean` | Extend unified OSCFSEL theorem family with measured-to-unified link or whole-table worst-case theorem |
+| 2 | `cli/tri/src/fpga.rs` or `bootstrap/src/compiler.rs` | Land one safe gen-verilog #1245 sub-fix, or update deferral note |
+| 3 | `cli/tri/src/fpga.rs` | Extend machine-readable `tri fpga` output (e.g. `--json` for `measured-to-lean` summary) |
+| 4 | `docs/reports/T27_VS_FORMAL_HDL_2026.md` | Refresh competitor snapshot if new signals appear |
+| 5 | `docs/reports/*` | W429 report, evidence, W430 cooperation |
+| 6 | `.trinity/experience.md` | W429 learnings |
+| 7 | git/PR | squash-merge to `master`, close issue, open #? for W430 |
 
 ---
 
 ## Acceptance criteria
 
 ### Bundle A
-- [ ] AC-A1: P12 is wired to a logic-analyzer channel and real CCLK capture files exist for `OSCFSEL=6` and `OSCFSEL=7`.
+- [ ] AC-A1: Real CCLK capture for `OSCFSEL=6` and `OSCFSEL=7` exists.
 - [ ] AC-A2: `tri fpga measured-to-lean --csv/--vcd --raw-ns --standalone` generated Lean files build with `lake build`.
 - [ ] AC-A3: Measured CCLK satisfies the PVT-aware flash spec, or any exceedance is explicitly explained.
+- [ ] AC-A4: Cold-POR SPI flash boot for OSCFSEL 6/7 is documented with STAT reads.
 
 ### Bundle B
-- [ ] AC-B1: `tri fpga cold-por <bit> --relay-port <real>` performs an automated power-cycle and captures STAT.
-- [ ] AC-B2: The resulting log has `relay_mock: false` and a real STAT raw value.
-- [ ] AC-B3: `fpga/HARDWARE_SSOT.md` documents relay wiring and port syntax.
+- [ ] AC-B1: Real XADC readout lands, OR at least one external capture is imported end-to-end.
+- [ ] AC-B2: The import/readout path exposes no unhandled unit, voltage-unit, or noise cases.
+- [ ] AC-B3: Boot-log artifacts for OSCFSEL 6/7 include PVT/XADC context.
+- [ ] AC-B4: The captured/recorded operating point is linked to the W428 unified OSCFSEL theorems.
 
 ### Bundle C
-- [x] AC-C1: At least one additional instrument-import unit test lands (VCD `$comment` hardening + CSV `--csv-channel` explicit select).
-- [x] AC-C2: Rust and Lean tests verify PVT envelope monotonicity/antitonicity.
-- [x] AC-C3: The standalone lake-package workflow is documented end-to-end.
+- [ ] AC-C1: At least one new PVT-related theorem is added and builds.
+- [ ] AC-C2: One safe gen-verilog sub-fix lands without increasing the 7-failure yosys smoke count, or is explicitly deferred if unsafe.
+- [ ] AC-C3: `tri fpga` CLI or JSON output is measurably more actionable than in W428.
+- [ ] AC-C4: Competitor snapshot is updated if any new 2026 developments are found.
 
 ### Invariant checks
-- [x] `./scripts/tri test` parse/typecheck/gen/seal-verify phases pass.
-- [x] `lake build Trinity.TernaryFPGABoot` passes.
-- [x] `cargo test -p tri fpga::tests` passes.
+- [ ] `./scripts/tri test` parse/typecheck/gen/seal-verify phases pass.
+- [ ] `lake build Trinity.TernaryFPGABoot` passes.
+- [ ] `cargo test -p tri` passes.
 
 ---
 
 ## PR
+
 - Target: `master`
-- PR: #1360
-- Body: `Closes #1357`
-- Report: `docs/reports/WAVE_LOOP_419_REPORT.md`
-- Evidence: `docs/reports/FPGA_LOOP_EVIDENCE_W419_2026-07-05.md`
-- Cooperation W420: `docs/reports/FPGA_LOOP_COOPERATION_W420_2026-07-05.md`
+- PR: to open after work
+- Body: `Closes #1385`
+- Report: `docs/reports/WAVE_LOOP_429_REPORT.md`
+- Evidence: `docs/reports/FPGA_LOOP_EVIDENCE_W429_YYYY-MM-DD.md`
+- Cooperation W430: `docs/reports/FPGA_LOOP_COOPERATION_W430_YYYY-MM-DD.md`
 
 ---
 
 ## Default variant
 
-Execute **Variant A** if the analyzer and DLC10 cable are available. Otherwise
-try **Variant B** if a relay and DLC10 cable are available. Otherwise fall back
-to **Variant C**.
+Execute **Variant A** if P12 is wired and the analyzer is ready.  
+Otherwise execute **Variant B** if the board is reachable for real XADC readout
+or an external capture is available.  
+Otherwise fall back to **Variant C**.
+
+## Chosen variant
+
+**Variant C** is the current best default for W429.
+
+Rationale from the W428 close-out:
+- Bench is reachable via Digilent HS2 (`idcode 0x03636093`), but P12 is still
+  unwired, no relay/remote-power gate is available, the DLC10 cable is still
+  missing, and only OSCFSEL 0–5 bitstreams exist in `build/fpga/cclk_variants`
+  (no 6/7 variants).
+- No external CSV/VCD captures for OSCFSEL 6/7 were provided.
+- `./scripts/tri test` baseline shows the same 7 pre-existing
+  gen-verilog-yosys-smoke failures from weak point #1245; no new regressions.
+- Therefore Variant A and Variant B are blocked until hardware state changes.
 
 ---
 

.trinity/current_task/.commit_count

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