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Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma#1434

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Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma#1434
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Closes #1431.

Summary

Wave Loop 459 selects Variant B from the W459 cooperation plan: with the physical bench still blocked, continue gen-verilog backend hardening.

What changed

  • bootstrap/src/compiler.rs: array-parameter binding now recurses into test, invariant, and bench blocks; test-block assert_eq and bare calls are emitted as real Verilog statements inside the existing `ifndef SIMULATION guard; rom_style pragma is emitted as (* rom_style = "..." *) on const [N]T ROMs; new tests_w459 unit tests.
  • bootstrap/src/suite.rs: yosys smoke runner now defines SIMULATION during parsing and fails on unrecognized warnings; the documented gen_verilog_smoke_baseline.json remains empty.
  • New scratch specs w459_array_param_test_call.t27 and w459_rom_style_block.t27 with seals.
  • All 583 seals re-sealed.
  • Close-out artifacts: WAVE_LOOP_459_REPORT.md, FPGA_LOOP_EVIDENCE_W459_2026-07-01.md, FPGA_LOOP_COOPERATION_W460_2026-07-01.md; NOW.md and T27_VS_FORMAL_HDL_2026.md updated.

Verification

  • ./scripts/tri test --fast: 583/583 non-smoke PASS, 63/63 yosys smoke PASS, FPGA smoke gate OK, 0 baseline failures, 0 seal mismatches, TOTAL FAILURES: 0.
  • cargo test -p t27c --bin t27c tests_w459: PASS (3/3).
  • Full ./scripts/tri test cannot complete in this environment because Phase 3c-standalone stalls on an external lake download of batteries; the smoke-gate report itself passes.
  • cargo test -p t27c --bin t27c: 1521 passed, 3 pre-existing failures unrelated to this change.

🤖 Generated with Claude Code

Dmitrii Vasilev and others added 30 commits July 5, 2026 23:28
docs(w426): set up Wave Loop 426 current issue (#1376)
5d55d4c
@claude
docs(tri): W425 issue + NOW setup (#1374, wave-loop-425)
37e8496 
- Update .trinity/current-issue.md with W425 goal, plan, acceptance criteria

- Prepend W424 close-out and W425 setup to docs/NOW.md

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 420 — VCD exact-terminator + real-net auto-thre…
fc2b758 
…shold, PVT process-corner monotonicity

Closes #1361

Variant C fallback (bench still blocked: P12 unwired, DLC10 cable missing,
no relay). Instrument-import depth and formal guarding only.

- cli/tri/src/fpga.rs:
  - exact-token VCD $date/$version/$comment terminator with regression test
    for embedded $end-like tokens (closes W419 report/actual gap)
  - real-valued VCD net auto-threshold from observed voltage swing
  - PVT half-period process-corner monotonicity regression test
- proofs/lean4/Trinity/TernaryFPGABoot.lean:
  - pvt_half_ns_monotone_in_process_corner (ff ≤ tt ≤ ss)
- fpga/HARDWARE_SSOT.md: §3.6.17 documenting W420 VCD/PVT improvements
- .trinity/experience.md: W420 learnings
- docs/reports: W420 report, evidence, and W421 cooperation variants

Verification:
- cargo test -p tri vcd: 13/13 PASS
- cargo test -p tri pvt: 10/10 PASS
- cargo test -p tri fpga::tests: 48/48 PASS
- lake build Trinity.TernaryFPGABoot: PASS (2967 jobs)
- ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(now): record W420 PR #1362 and merge-pending status
37f74fe 
Refs: #1362
Closes #1361

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(issue): set current issue to Wave Loop 421
41fe15b 
Closes #1363

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined…
d989500 
… PVT monotonicity, competitor snapshot

Closes #1363

Variant C fallback (bench still blocked: openFPGALoader --detect reports 0 devices).

- cli/tri/src/fpga.rs:
  - apply vcd_line_ends_with_token to $timescale terminator
  - add test_parse_vcd_timescale_with_embedded_end_token
  - add test_parse_vcd_real_auto_threshold_us_timescale
  - add test_pvt_half_ns_monotone_combined
- proofs/lean4/Trinity/TernaryFPGABoot.lean:
  - add pvt_half_ns_monotone_combined
- fpga/HARDWARE_SSOT.md: §3.6.18 documenting W421 improvements
- docs/reports/T27_VS_FORMAL_HDL_2026.md: competitor comparison
- .trinity/experience.md: W421 learnings
- docs/reports: W421 report, evidence, and W422 cooperation variants

Verification:
- cargo test -p tri vcd: 15/15 PASS
- cargo test -p tri pvt: 11/11 PASS
- cargo test -p tri fpga::tests: 51/51 PASS
- lake build Trinity.TernaryFPGABoot: PASS (2967 jobs)
- ./scripts/tri test: 16 pre-existing yosys failures (#1245), no new ones

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
docs(issue): set current issue to Wave Loop 422\n\nCloses #1365\n\nCo…
cf2ec3f 
…-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword …
ac23469 
…escape, PVT worst-case bound

Closes #1365

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(issue): set current issue to Wave Loop 423
6b2c312 
Closes #1368

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT wor…
80855d9 
…st-case, competitor refresh (Closes #1368)

- cli/tri/src/fpga.rs: CSV ms/us/ns/sample-number normalization, VCD real-net
  slope filter, unknown timescale fallback, dumpoff/dumpon without timestamp,
  --pvt-worstcase mode; +10 regression tests (60/60 PASS).
- fpga/HARDWARE_SSOT.md: add §3.6.20 documenting W423 instrument-import depth.
- docs/reports/T27_VS_FORMAL_HDL_2026.md: refresh Sparkle/Verilean, Clash, CIRCT.
- docs/reports/WAVE_LOOP_423_REPORT.md, FPGA_LOOP_EVIDENCE_W423_2026-07-05.md,
  FPGA_LOOP_COOPERATION_W424_2026-07-05.md: W423 close-out + W424 variants.
- docs/NOW.md, .trinity/experience.md, .trinity/current-issue.md: W423 close-out
  and W424 setup.

Full sweep: 576 passed, 0 seal mismatches, 7 pre-existing gen-verilog yosys
smoke failures, 0 FPGA smoke failures.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
setup(igla): Wave Loop 424 branch and issue (#1371)
c6b0280 
Update .trinity/current-issue.md and cooperation file with the new W424
issue number.

Reference #1371

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV …
b4a6bff 
…voltage units, non-blocking continue, W425 setup

- Add non-blocking wait_for_continue helper for boot-log/cold-por/cclk-sweep

- Parse CSV voltage units (v/mv) and scale to volts before threshold detection

- Embed optional PVT context + XADC placeholder into boot-log JSON

- Expand default CCLK sweep to OSCFSEL 0..7

- Add Lean 4 ProcessCorner decidability/severity helpers

- W424 report, evidence, and W425 cooperation variants

Closes #1371

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
chore(tri): update session log and commit count after W424 close-out
9da4adb 
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(tri): correct W425 issue reference to #1374
e845536 
Closes #1371

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelop…
c9d8a11 
…e theorems (closes #1374)

- cli/tri/src/fpga.rs: expand cclk-sweep/smoke-gate default OSCFSEL range to 0–7
- proofs/lean4/Trinity/TernaryFPGABoot.lean: add pvt_half_ns_worst_case_is_upper_envelope
  and pvt_low_ns_worst_case_is_upper_envelope; move OSCFSEL_WORST_CASE_PVT_CONTEXT earlier
- docs/reports: W425 report, evidence, and W426 cooperation variants
- .trinity/current-issue.md + experience.md: W425 close-out learnings
- Variant C executed because P12 is still unwired and no relay gate is available

Verification: cargo test -p tri PASS, lake build PASS, tri test PASS (7 pre-existing gen-verilog yosys smoke failures unchanged)

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 426 — finite-grid PVT theorems, machine-readabl…
a3e02c4 
…e tri fpga JSON, competitor refresh (Variant C)

Wave 426 executed Variant C because the physical bench is still blocked:
P12 CCLK probe unwired, no relay gate, DLC10 missing.

Deliverables:
- proofs/lean4/Trinity/TernaryFPGABoot.lean:
  - pvt_half_ns_operating_rectangle_grid_bounded
  - pvt_low_ns_operating_rectangle_grid_bounded
  - exhaustive 75-point worst-case corner dominance proof
- cli/tri/src/fpga.rs:
  - cclk_nominal_hz mirror of the Lean CCLK table
  - pvt_envelope_margin_ns and recommendation_from_conclusion helpers
  - SweepLog, boot-log, and cold-por JSON now emit recommendation and margin
  - 8 new unit tests (101/101 pass)
- docs/reports/T27_VS_FORMAL_HDL_2026.md: Sparkle July 2026 Functional Matsuri
  talk, Clash 1.8.5 verification fixes, CIRCT/firtool notes
- docs/reports/W426_WEAK_POINTS_AND_COMPETITORS.md: updated weak-point scan
- docs/reports/WAVE_LOOP_426_REPORT.md and FPGA_LOOP_EVIDENCE_W426_2026-07-05.md
- docs/reports/FPGA_LOOP_COOPERATION_W427_2026-07-05.md: next-wave variants
- .trinity/experience.md: W426 learnings
- docs/NOW.md: W426 close-out / W427 setup
- .trinity/current-issue.md: mark Variant C acceptance criteria complete

Verification:
- cargo test -p tri: 101/101 pass
- lake build Trinity.TernaryFPGABoot: 2967 jobs, 0 errors
- ./scripts/tri test: parse/typecheck/gen/seal-verify PASS; 7 pre-existing
  gen-verilog-yosys-smoke failures (#1245) unchanged

Closes #1376

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
docs(w427): set up current issue for Wave Loop 427 (#1379)
ff99fb7
@claude
feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fp…
6c14c1f 
…ga sweep-report --json, competitor refresh (Variant C)

Closes #1379

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(issue): set current issue to Wave Loop 428 (#1383)
299f268 
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 428 — unified OSCFSEL PVT theorems, tri fpga pv…
28008bd 
…t-envelope --json, competitor refresh

Closes #1383

- Add four quantified OSCFSEL 0..7 PVT/transaction theorems in
  proofs/lean4/Trinity/TernaryFPGABoot.lean.
- Add --json output to tri fpga pvt-envelope with shared report builder
  and unit tests.
- Refresh T27_VS_FORMAL_HDL_2026.md with 2026 releases and emerging signals.
- Document W428 gen-verilog #1245 deferral.
- Add close-out reports and W429 cooperation variants.
- Update docs/NOW.md and .trinity/experience.md.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
chore(w429): seed current-issue.md for Wave Loop 429
c43ca2d 
Sets up W429 tracking issue #1385 and default Variant C rationale.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean…
835d954 
… --json, W429 report and W430 cooperation (Closes #1385)

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs: Wave Loop 430 current-issue setup (Refs #1388)
fb74923 
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs: Wave Loop 429 experience log
047f087 
Closes #1385

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
feat(igla): Wave Loop 430 — live XADC readout, PVT-envelope bridge, W…
5fb139e 
…431 cooperation\n\n- Add tri fpga read-xadc and --xadc flags on boot-log/cold-por/cclk-sweep.\n- Parse openFPGALoader --read-xadc output and embed live temp/vccint/vccaux in JSON logs.\n- Add XadcOperatingPoint formal bridge and worst-case-bound theorem in TernaryFPGABoot.lean.\n- Update fpga/HARDWARE_SSOT.md, T27_VS_FORMAL_HDL_2026.md, GEN_VERILOG_DEFECTS_REPRO.md.\n- Create WAVE_LOOP_430_REPORT.md and FPGA_LOOP_COOPERATION_W431_2026-07-01.md.\n- Verification: cargo test fpga:: 79/79, lake build pass, tri test pass except 7 pre-existing #1245 failures.\n\nCloses #1388\n\nCo-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
docs(trinity): W431 setup — current issue, NOW, experience (Wave Loop…
e622787 
… 430 close-out)\n\n- Point .trinity/current-issue.md and docs/NOW.md to W431 (#1389).\n- Add W430 learnings to .trinity/experience.md.\n\nCo-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envel…
2f5af00 
…ope, measured-to-lean --json summary hardening

Closes #1389

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs: record PR #1392 in NOW.md and experience.md
4c4cf74 
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorem…
2626755 
…s, master-merge feasibility probe, W432 close-out artifacts

Closes #1391

- Add cclk_variant_raw_ns_per_process_corner_pvt_satisfies_flash_spec and
  cclk_variant_raw_ns_per_process_corner_pvt_implies_transaction_ok in
  proofs/lean4/Trinity/TernaryFPGABoot.lean, quantifying PVT-aware safety over
  all documented OSCFSEL values (0..7) and all process corners (ff/tt/ss).
- Probed origin/master merge and cherry-pick of 507408f; fix set 701d79b is
  on a divergent master lineage not safely reachable from wave-loop-432.
- Refresh docs/reports/T27_VS_FORMAL_HDL_2026.md and
  docs/reports/GEN_VERILOG_DEFECTS_REPRO.md with W432 triage.
- Add W432 report, evidence note, and W433 cooperation variants.
- Update docs/NOW.md and .trinity/current-issue.md for W433 (#1393).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(experience): W432 learnings — per-process-corner theorem, master…
9e93632 
…-merge probe, blocked bench redirect

Closes #1391

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Dmitrii Vasilev and others added 10 commits July 6, 2026 15:13
@claude
docs(w454): point current-issue, NOW, and cooperation to W454 issue #…
7fd18f8 
…1424

Closes nothing — W454 setup commit.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 454 — high-VCCINT adversarial witness, duty-cyc…
fe50920 
…le asymmetry, bounded jitter theorems + Rust counterparts; reject master-merge as insufficient; W455 handoff

Closes #1424

- Add OUTSIDE_VCCINT_HIGH_W454_OPERATING_POINT and dashboard-gate rejection theorem
- Add cclk_oscfsel_7_duty_asymmetry_w454 and cclk_ideal_split_robust_to_1ns_jitter_w454
- Add cclk_variant_and_xadc_envelope_check Rust helper and 5 W454 unit tests
- Refresh T27_VS_FORMAL_HDL_2026.md and GEN_VERILOG_DEFECTS_REPRO.md W454 boundary
- Mint WAVE_LOOP_454_REPORT.md, FPGA_LOOP_EVIDENCE_W454, FPGA_LOOP_COOPERATION_W455
- Update NOW.md and current-issue.md for W455 (#1425) handoff

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(experience): W454 learnings — master-merge audit, adversarial/ro…
5327da2 
…bustness theorems, Variant C pivot

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 455 — clear 7 residual gen-verilog yosys smoke …
92167a8 
…failures by porting tuple/array backend

- Parser: tuple return types, tuple literals, let destructuring
- Verilog backend: tuple-return packed regs, let destructuring slice lowering,
  module-level const [N]T ROM lowering, function-local var [N]T arrays
- Keyword-safe full-token escape for flattened local-array element names
- Reseal 67 affected specs
- Restore cli/flash-spi workspace build with new FlashOpts defaults
- Docs: W455 report, evidence, W456 cooperation plan, NOW.md, current-issue

Closes #1425

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
docs(reports): W452–W455 competitor boundary refresh in T27_VS_FORMAL…
e66d236 
…_HDL_2026.md

Closes #1425
@claude
feat(igla): Wave Loop 456 — ROM read-only enforcement + regression spec
619964f 
- Typecheck rejects assignments to elements of immutable const arrays.
- Add scratch spec w456_rom_readonly.t27 exercising const ROM reads and a
  local-array write contrast.
- Add compiler unit tests verifying rejection of const-array writes and
  continued allowance of var-array writes.
- Reseal new spec.

Closes #1427

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
docs(w456): W456 close-out report, evidence, W457 cooperation plan, N…
5ca09d1 
…OW/current-issue refresh

Closes #1427

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 457 — RAM style pragma support for module-level…
fde21a9 
… arrays

- Add pragma token/parser state and ram_style attribute emission
- Add w457_ram_style_block/distributed regression specs + seals
- Add unit tests for block/distributed pragma emission and unknown-pragma rejection
- Close-out reports, evidence, and W458 cooperation plan

Closes #1428

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@claude
feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-leve…
2a764aa 
…l array parameters

Closes #1429

Wave Loop 458 selected Variant B (bench still blocked) and added two related
gen-verilog backend hardening items:

1. Module-level array access from functions. Functions inside a module can now
   reference module-level const/var arrays by name. A pub fn can declare an array
   parameter bound to a module-level array through a single module-level call
   site; the bound array is referenced by name inside the function.

2. Warning hygiene for the yosys smoke gate:
   - Replaced // synthesis translate_off/on with `ifndef SIMULATION / `endif.
   - f32/f64 scalar constants now emit parameter real / localparam real.
   - String literals are escaped before Verilog emission.

Also added bare module-level statement support, fixed a module-body recovery
infinite-loop edge case, added four unit tests in tests_w458, and added two
regression specs with seals.

Verification:
- cargo test -p t27c --bin t27c tests_w458: PASS (4/4)
- ./scripts/tri test --fast --json /tmp/tri_test_w458_fast.json: ALL TESTS PASSED
  (581/581 non-smoke PASS, 61/61 yosys smoke PASS, FPGA smoke gate OK, 0 seal
  mismatches). The default ./scripts/tri test could not complete because Phase
  3c-standalone stalls on an external lake dependency download; the --fast path
  is fully green.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
🤖 Generated with [Claude Code](https://claude.com/claude-code)
@claude
feat(igla): Wave Loop 459 — array parameters from test/invariant/benc…
91ef625 
…h, yosys warning gate with SIMULATION define, ROM style pragma, 583/583 non-smoke PASS + 63/63 yosys smoke PASS

Closes #1431

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-07-06 14:33:34 UTC

Summary

Status Count
Total Open PRs 34
PRs with Failing Checks 21
PRs with All Checks Green 13
READY 12
FAILING 21
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=a76e3c45d726 != manifest seal=49e55df6d444.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@claude
docs(w459): record PR #1434 in NOW.md and WAVE_LOOP_459_REPORT.md
f71a581 
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-07-06 14:34:22 UTC

Summary

Status Count
Total Open PRs 34
PRs with Failing Checks 21
PRs with All Checks Green 13
READY 12
FAILING 21
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=a76e3c45d726 != manifest seal=49e55df6d444.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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Wave Loop 459 — Select Variant A/B/C and close with green suite + cooperation plan

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@gHashTag