fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676

[gHashTag]

fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676

Closes #1444

Note: fpga-smoke / fpga-formal / fpga-synthesis checks are red by design because the hardware bench is unreachable in this PR; all software checks pass.

[github-actions]

📓 NotebookLM Notebook linked to this PR

• Notebook ID: b83263109fb055dc
• URL: https://notebooklm.google.com/notebook/b83263109fb055dc

This notebook contains session context, decisions, and artifacts for this work.

[github-actions]

PR Dashboard

Generated at: 2026-07-07 12:06:17 UTC

• fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676 #1445 fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676 | Created: 2026-07-07 | Updated: 2026-07-07 | 12 failing / 17 total
• fix(igla): harden auto-merge and brain-seal-refresh workflows #1441 fix(igla): harden auto-merge and brain-seal-refresh workflows | Created: 2026-07-07 | Updated: 2026-07-07 | 1 failing / 17 total
• fix(igla): remove duplicate workflow directory, enforce FROZEN_HASH, and unify L1 traceability regexes #1439 fix(igla): remove duplicate workflow directory, enforce FROZEN_HASH, and unify L1 traceability regexes | Created: 2026-07-07 | Updated: 2026-07-07 | 2 failing / 19 total
• chore(license): align README/Cargo.toml/.zenodo.json/CITATION.cff to Apache-2.0 #1437 chore(license): align README/Cargo.toml/.zenodo.json/CITATION.cff to Apache-2.0 | Created: 2026-07-07 | Updated: 2026-07-07 | 23 failing / 44 total
• Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma #1434 Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-level array parameters #1432 feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-level array parameters | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• feat(igla): Wave Loop 457 — RAM style pragma support for module-level arrays #1430 feat(igla): Wave Loop 457 — RAM style pragma support for module-level arrays | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• Wave Loop 454 — high-VCCINT adversarial witness + duty-cycle/jitter robustness theorems #1426 Wave Loop 454 — high-VCCINT adversarial witness + duty-cycle/jitter robustness theorems | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 26 total
• feat(igla): Wave Loop 436 — live XADC → PVT context in boot logs and sweep reports (closes #1402) #1406 feat(igla): Wave Loop 436 — live XADC → PVT context in boot logs and sweep reports (closes #1402) | Created: 2026-07-05 | Updated: 2026-07-05 | 5 failing / 27 total
• feat(igla): Wave Loop 435 — live XADC → PVT context CLI export, OSCFSEL 0..7 synthetic theorem matrix #1403 feat(igla): Wave Loop 435 — live XADC → PVT context CLI export, OSCFSEL 0..7 synthetic theorem matrix | Created: 2026-07-05 | Updated: 2026-07-06 | 10 failing / 52 total
• feat(igla): Wave Loop 434 — live XADC → PVT theorem, synthetic CCLK proof-of-pipeline #1400 feat(igla): Wave Loop 434 — live XADC → PVT theorem, synthetic CCLK proof-of-pipeline | Created: 2026-07-05 | Updated: 2026-07-06 | 1 failing / 6 total
• Wave Loop 433: formal bridge fallback (closes #1393) #1396 Wave Loop 433: formal bridge fallback (closes #1393) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorems, W432 close-out #1394 feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorems, W432 close-out | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 7 total
• feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envelope, measured-to-lean --json summary hardening #1392 feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envelope, measured-to-lean --json summary hardening | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 7 total
• Wave Loop 430 — live XADC readout and PVT-envelope bridge #1390 Wave Loop 430 — live XADC readout and PVT-envelope bridge | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation #1387 Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• Wave Loop 428 — unified OSCFSEL PVT theorems, pvt-envelope --json, competitor refresh #1384 Wave Loop 428 — unified OSCFSEL PVT theorems, pvt-envelope --json, competitor refresh | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fpga sweep-report --json, competitor refresh (Variant C) #1382 feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fpga sweep-report --json, competitor refresh (Variant C) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 4 total
• Wave Loop 426 — finite-grid PVT theorems, machine-readable tri fpga JSON, competitor refresh (Closes #1376) #1378 Wave Loop 426 — finite-grid PVT theorems, machine-readable tri fpga JSON, competitor refresh (Closes #1376) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelope theorems #1375 feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelope theorems | Created: 2026-07-05 | Updated: 2026-07-06 | 4 failing / 27 total
• feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV voltage units, non-blocking continue, W425 setup #1373 feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV voltage units, non-blocking continue, W425 setup | Created: 2026-07-05 | Updated: 2026-07-06 | 8 failing / 49 total
• feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh #1372 feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh | Created: 2026-07-05 | Updated: 2026-07-06 | 6 failing / 50 total
• Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword escape, PVT worst-case bound #1369 Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword escape, PVT worst-case bound | Created: 2026-07-05 | Updated: 2026-07-06 | 6 failing / 50 total
• feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined PVT monotonicity, competitor snapshot #1364 feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined PVT monotonicity, competitor snapshot | Created: 2026-07-04 | Updated: 2026-07-06 | 7 failing / 48 total
• feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity #1362 feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity | Created: 2026-07-04 | Updated: 2026-07-06 | 3 failing / 26 total
• docs(metrics): сводка ключевых метрик 83 числовых форматов (SSOT-derived) #1225 docs(metrics): сводка ключевых метрик 83 числовых форматов (SSOT-derived) | Created: 2026-06-28 | Updated: 2026-07-06 | 6 failing / 31 total
• ci(trust): OpenSSF Scorecard + SBOM + Sigstore signed releases #1141 ci(trust): OpenSSF Scorecard + SBOM + Sigstore signed releases | Created: 2026-06-15 | Updated: 2026-07-06 | 6 failing / 31 total
• fix(gen): untrack stale gen/numeric catalog artifacts (committed gen drifts 77 vs SSOT 83) -- Closes #1120 #1128 fix(gen): untrack stale gen/numeric catalog artifacts (committed gen drifts 77 vs SSOT 83) -- Closes #1120 | Created: 2026-06-14 | Updated: 2026-07-06 | 0 failing / 22 total

Summary

Status	Count
Total Open PRs	28
PRs with Failing Checks	18
PRs with All Checks Green	10
READY	9
FAILING	18
PENDING	0

Seal Status

• ⚠️ STALE -- sha256(compiler.rs)=197d6eb5a40b != manifest seal=49e55df6d444.
  The committed NMSE numbers were certified against an older compiler.rs.
  Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

[github-actions]

📓 NotebookLM Notebook linked to this PR

• Notebook ID: b83263109fb055dc
• URL: https://notebooklm.google.com/notebook/b83263109fb055dc

This notebook contains session context, decisions, and artifacts for this work.

[github-actions]

PR Dashboard

Generated at: 2026-07-07 12:15:34 UTC

• fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676 #1445 fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676 | Created: 2026-07-07 | Updated: 2026-07-07 | 10 failing / 17 total
• fix(igla): harden auto-merge and brain-seal-refresh workflows #1441 fix(igla): harden auto-merge and brain-seal-refresh workflows | Created: 2026-07-07 | Updated: 2026-07-07 | 3 failing / 17 total
• fix(igla): remove duplicate workflow directory, enforce FROZEN_HASH, and unify L1 traceability regexes #1439 fix(igla): remove duplicate workflow directory, enforce FROZEN_HASH, and unify L1 traceability regexes | Created: 2026-07-07 | Updated: 2026-07-07 | 5 failing / 24 total
• chore(license): align README/Cargo.toml/.zenodo.json/CITATION.cff to Apache-2.0 #1437 chore(license): align README/Cargo.toml/.zenodo.json/CITATION.cff to Apache-2.0 | Created: 2026-07-07 | Updated: 2026-07-07 | 23 failing / 44 total
• Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma #1434 Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-level array parameters #1432 feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-level array parameters | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• feat(igla): Wave Loop 457 — RAM style pragma support for module-level arrays #1430 feat(igla): Wave Loop 457 — RAM style pragma support for module-level arrays | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• Wave Loop 454 — high-VCCINT adversarial witness + duty-cycle/jitter robustness theorems #1426 Wave Loop 454 — high-VCCINT adversarial witness + duty-cycle/jitter robustness theorems | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 26 total
• feat(igla): Wave Loop 436 — live XADC → PVT context in boot logs and sweep reports (closes #1402) #1406 feat(igla): Wave Loop 436 — live XADC → PVT context in boot logs and sweep reports (closes #1402) | Created: 2026-07-05 | Updated: 2026-07-05 | 5 failing / 27 total
• feat(igla): Wave Loop 435 — live XADC → PVT context CLI export, OSCFSEL 0..7 synthetic theorem matrix #1403 feat(igla): Wave Loop 435 — live XADC → PVT context CLI export, OSCFSEL 0..7 synthetic theorem matrix | Created: 2026-07-05 | Updated: 2026-07-06 | 10 failing / 52 total
• feat(igla): Wave Loop 434 — live XADC → PVT theorem, synthetic CCLK proof-of-pipeline #1400 feat(igla): Wave Loop 434 — live XADC → PVT theorem, synthetic CCLK proof-of-pipeline | Created: 2026-07-05 | Updated: 2026-07-06 | 1 failing / 6 total
• Wave Loop 433: formal bridge fallback (closes #1393) #1396 Wave Loop 433: formal bridge fallback (closes #1393) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorems, W432 close-out #1394 feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorems, W432 close-out | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 7 total
• feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envelope, measured-to-lean --json summary hardening #1392 feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envelope, measured-to-lean --json summary hardening | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 7 total
• Wave Loop 430 — live XADC readout and PVT-envelope bridge #1390 Wave Loop 430 — live XADC readout and PVT-envelope bridge | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation #1387 Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• Wave Loop 428 — unified OSCFSEL PVT theorems, pvt-envelope --json, competitor refresh #1384 Wave Loop 428 — unified OSCFSEL PVT theorems, pvt-envelope --json, competitor refresh | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fpga sweep-report --json, competitor refresh (Variant C) #1382 feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fpga sweep-report --json, competitor refresh (Variant C) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 4 total
• Wave Loop 426 — finite-grid PVT theorems, machine-readable tri fpga JSON, competitor refresh (Closes #1376) #1378 Wave Loop 426 — finite-grid PVT theorems, machine-readable tri fpga JSON, competitor refresh (Closes #1376) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelope theorems #1375 feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelope theorems | Created: 2026-07-05 | Updated: 2026-07-06 | 4 failing / 27 total
• feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV voltage units, non-blocking continue, W425 setup #1373 feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV voltage units, non-blocking continue, W425 setup | Created: 2026-07-05 | Updated: 2026-07-06 | 8 failing / 49 total
• feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh #1372 feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh | Created: 2026-07-05 | Updated: 2026-07-06 | 6 failing / 50 total
• Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword escape, PVT worst-case bound #1369 Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword escape, PVT worst-case bound | Created: 2026-07-05 | Updated: 2026-07-06 | 6 failing / 50 total
• feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined PVT monotonicity, competitor snapshot #1364 feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined PVT monotonicity, competitor snapshot | Created: 2026-07-04 | Updated: 2026-07-06 | 7 failing / 48 total
• feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity #1362 feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity | Created: 2026-07-04 | Updated: 2026-07-06 | 3 failing / 26 total
• docs(metrics): сводка ключевых метрик 83 числовых форматов (SSOT-derived) #1225 docs(metrics): сводка ключевых метрик 83 числовых форматов (SSOT-derived) | Created: 2026-06-28 | Updated: 2026-07-06 | 6 failing / 31 total
• ci(trust): OpenSSF Scorecard + SBOM + Sigstore signed releases #1141 ci(trust): OpenSSF Scorecard + SBOM + Sigstore signed releases | Created: 2026-06-15 | Updated: 2026-07-06 | 6 failing / 31 total
• fix(gen): untrack stale gen/numeric catalog artifacts (committed gen drifts 77 vs SSOT 83) -- Closes #1120 #1128 fix(gen): untrack stale gen/numeric catalog artifacts (committed gen drifts 77 vs SSOT 83) -- Closes #1120 | Created: 2026-06-14 | Updated: 2026-07-06 | 0 failing / 22 total

Summary

Status	Count
Total Open PRs	28
PRs with Failing Checks	17
PRs with All Checks Green	11
READY	9
FAILING	17
PENDING	0

Seal Status

• ⚠️ STALE -- sha256(compiler.rs)=197d6eb5a40b != manifest seal=49e55df6d444.
  The committed NMSE numbers were certified against an older compiler.rs.
  Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

[github-actions]

📓 NotebookLM Notebook linked to this PR

• Notebook ID: b83263109fb055dc
• URL: https://notebooklm.google.com/notebook/b83263109fb055dc

This notebook contains session context, decisions, and artifacts for this work.

[github-actions]

PR Dashboard

Generated at: 2026-07-07 12:49:42 UTC

• fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676 #1445 fix(igla): align Vivado scripts and constraints header with HARDWARE_SSOT XC7A200T-FGG676 | Created: 2026-07-07 | Updated: 2026-07-07 | 7 failing / 16 total
• chore(license): align README/Cargo.toml/.zenodo.json/CITATION.cff to Apache-2.0 #1437 chore(license): align README/Cargo.toml/.zenodo.json/CITATION.cff to Apache-2.0 | Created: 2026-07-07 | Updated: 2026-07-07 | 23 failing / 44 total
• Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma #1434 Wave Loop 459 — gen-verilog array parameters from test/invariant/bench + yosys warning gate + ROM style pragma | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-level array parameters #1432 feat(igla): Wave Loop 458 — gen-verilog warning hygiene + module-level array parameters | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• feat(igla): Wave Loop 457 — RAM style pragma support for module-level arrays #1430 feat(igla): Wave Loop 457 — RAM style pragma support for module-level arrays | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 27 total
• Wave Loop 454 — high-VCCINT adversarial witness + duty-cycle/jitter robustness theorems #1426 Wave Loop 454 — high-VCCINT adversarial witness + duty-cycle/jitter robustness theorems | Created: 2026-07-06 | Updated: 2026-07-06 | 5 failing / 26 total
• feat(igla): Wave Loop 436 — live XADC → PVT context in boot logs and sweep reports (closes #1402) #1406 feat(igla): Wave Loop 436 — live XADC → PVT context in boot logs and sweep reports (closes #1402) | Created: 2026-07-05 | Updated: 2026-07-05 | 5 failing / 27 total
• feat(igla): Wave Loop 435 — live XADC → PVT context CLI export, OSCFSEL 0..7 synthetic theorem matrix #1403 feat(igla): Wave Loop 435 — live XADC → PVT context CLI export, OSCFSEL 0..7 synthetic theorem matrix | Created: 2026-07-05 | Updated: 2026-07-06 | 10 failing / 52 total
• feat(igla): Wave Loop 434 — live XADC → PVT theorem, synthetic CCLK proof-of-pipeline #1400 feat(igla): Wave Loop 434 — live XADC → PVT theorem, synthetic CCLK proof-of-pipeline | Created: 2026-07-05 | Updated: 2026-07-06 | 1 failing / 6 total
• Wave Loop 433: formal bridge fallback (closes #1393) #1396 Wave Loop 433: formal bridge fallback (closes #1393) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorems, W432 close-out #1394 feat(igla): Wave Loop 432 — per-process-corner raw-ns OSCFSEL theorems, W432 close-out | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 7 total
• feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envelope, measured-to-lean --json summary hardening #1392 feat(igla): Wave Loop 431 — XADC→PVT context bridge, computable envelope, measured-to-lean --json summary hardening | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 7 total
• Wave Loop 430 — live XADC readout and PVT-envelope bridge #1390 Wave Loop 430 — live XADC readout and PVT-envelope bridge | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation #1387 Wave Loop 429 — raw-ns OSCFSEL theorems, measured-to-lean --json, W430 cooperation | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• Wave Loop 428 — unified OSCFSEL PVT theorems, pvt-envelope --json, competitor refresh #1384 Wave Loop 428 — unified OSCFSEL PVT theorems, pvt-envelope --json, competitor refresh | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fpga sweep-report --json, competitor refresh (Variant C) #1382 feat(igla): Wave Loop 427 — per-OSCFSEL PVT envelope theorems, tri fpga sweep-report --json, competitor refresh (Variant C) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 4 total
• Wave Loop 426 — finite-grid PVT theorems, machine-readable tri fpga JSON, competitor refresh (Closes #1376) #1378 Wave Loop 426 — finite-grid PVT theorems, machine-readable tri fpga JSON, competitor refresh (Closes #1376) | Created: 2026-07-05 | Updated: 2026-07-06 | 0 failing / 5 total
• feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelope theorems #1375 feat(igla): Wave Loop 425 — OSCFSEL 0–7 sweep, PVT worst-case envelope theorems | Created: 2026-07-05 | Updated: 2026-07-06 | 4 failing / 27 total
• feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV voltage units, non-blocking continue, W425 setup #1373 feat(igla): Wave Loop 424 — FPGA tooling hardening, PVT context, CSV voltage units, non-blocking continue, W425 setup | Created: 2026-07-05 | Updated: 2026-07-06 | 8 failing / 49 total
• feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh #1372 feat(igla): Wave Loop 423 — CSV time units, VCD slope filter, PVT worst-case, competitor refresh | Created: 2026-07-05 | Updated: 2026-07-06 | 6 failing / 50 total
• Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword escape, PVT worst-case bound #1369 Wave Loop 422 — live XC7A200T SRAM boot, Verilog keyword escape, PVT worst-case bound | Created: 2026-07-05 | Updated: 2026-07-06 | 6 failing / 50 total
• feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined PVT monotonicity, competitor snapshot #1364 feat(igla): Wave Loop 421 — VCD $timescale exact terminator, combined PVT monotonicity, competitor snapshot | Created: 2026-07-04 | Updated: 2026-07-06 | 7 failing / 48 total
• feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity #1362 feat(igla): Wave Loop 420 — VCD exact-terminator + auto-threshold, PVT process-corner monotonicity | Created: 2026-07-04 | Updated: 2026-07-06 | 3 failing / 26 total
• docs(metrics): сводка ключевых метрик 83 числовых форматов (SSOT-derived) #1225 docs(metrics): сводка ключевых метрик 83 числовых форматов (SSOT-derived) | Created: 2026-06-28 | Updated: 2026-07-06 | 6 failing / 31 total
• ci(trust): OpenSSF Scorecard + SBOM + Sigstore signed releases #1141 ci(trust): OpenSSF Scorecard + SBOM + Sigstore signed releases | Created: 2026-06-15 | Updated: 2026-07-06 | 6 failing / 31 total
• fix(gen): untrack stale gen/numeric catalog artifacts (committed gen drifts 77 vs SSOT 83) -- Closes #1120 #1128 fix(gen): untrack stale gen/numeric catalog artifacts (committed gen drifts 77 vs SSOT 83) -- Closes #1120 | Created: 2026-06-14 | Updated: 2026-07-06 | 0 failing / 22 total

Summary

Status	Count
Total Open PRs	26
PRs with Failing Checks	16
PRs with All Checks Green	10
READY	9
FAILING	16
PENDING	0

Seal Status

• ⚠️ STALE -- sha256(compiler.rs)=197d6eb5a40b != manifest seal=49e55df6d444.
  The committed NMSE numbers were certified against an older compiler.rs.
  Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).